JPH04364077A - Non-volatile semiconductor storage element and non-volatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To provide an SISOS type byte EEOROM cell which has reduced a size of cell, can be mounted with simplified process on the same chip together with an SISOS type flash EEPROM cell and enables renewal of program by the byte. CONSTITUTION:A non-volatile semiconductor storage element and device comprises a memory transistor 60a consisting of an SISOS type flash EEPROM cell and a memory cell selection transistor 60b connected in the drain side of this memory transistor.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory element and a nonvolatile semiconductor memory device, and more particularly to an electrically erasable/rewritable EEPROM type nonvolatile semiconductor memory element and a nonvolatile semiconductor memory device.

0002

2. Description of the Related Art FIG. 5 shows a general block configuration of a microcomputer 50. CPU (central processing unit) section 51, RAM (static memory) section 52,
The main components are a ROM (read-only memory) section 53 and an I/O (input/output) section 54, which are mounted on the same chip.

[0003] The ROM section 53 is usually composed of two types: data memory and program memory. The above-mentioned data memory is required to be able to be rewritten in byte units and to be able to be rewritten about 104 times, but the capacity may be several kilobits, and generally, FLOTOX
It is composed of a nnel OXide) type EEPROM. Furthermore, the program memory is not required to be rewritten in byte units, and may be written in byte units and erased all at once, and the number of rewrites is 102.
However, a capacity of 512 kbit or more is required, and is generally constructed from a flash EEPEOM.

The above FLOTOX type EEPROM is shown in FIG.
As shown in the figure, since it has a two-transistor configuration of a memory transistor and a selection transistor, the cell size is large and it is not suitable for increasing capacity, but it is possible to rewrite in byte units and the number of rewrites is guaranteed to be about 104 times. With a proven track record, it meets the data memory specifications. In FIG. 6, 201 is a semiconductor substrate, 202 is a source region, 204 is a tunnel insulating film, 205 is a floating gate electrode, 206 is an interelectrode insulating film, 207 is a control gate electrode, 209 is a first gate insulating film, 211 212 is a first drain region, 212 is a second drain region, 213 is a second gate insulating film, and 214 is a control gate electrode.

However, the above FLOTOX type EEPROM
Since the tunnel region of the memory transistor in the cell is formed by resist patterning, there is a problem in that the cell size becomes large.

On the other hand, the flash EEPROM can be erased all at once, but because of its small cell size, it can be increased in capacity and meets the specifications of a program memory. Several types of flash EEPROM cells have been put into practical use, and as a conventional example, FIG.
(Advanced Contactless EEP
Figure 8 shows an ETOX (EPROM) type cell.
FIG. 9 shows a SISOS (Sidewall Select-g) type cell in which a sidewall selection transistor is provided on the source side.
2 shows a type of flash EEPROM cell.

In FIG. 7, 301 is a semiconductor substrate;
2 is a source region, 303 is a drain region, 304 is a tunnel insulating film, 305 is a floating gate electrode, 306 is an interelectrode insulating film, 307 is a control gate electrode, and 308 is a gate insulating film.

In FIG. 8, 401 is a semiconductor substrate;
2 is a source region, 403 is a drain region, 404 is a tunnel insulating film, 405 is a floating gate electrode, 406 is an interelectrode insulating film, and 407 is a control gate electrode.

In FIG. 9, 501 is a semiconductor substrate;
2 is a source region, 503 is a drain region, 504 is a tunnel insulating film, 505 is a floating gate electrode, 506 is an interelectrode insulating film, 507 is a control gate electrode, 508 is a sidewall insulating film, 509 is a gate insulating film, 510 is a selection This is the gate electrode. Note that a contact opening for bit line contact is provided in the insulating film (not shown) on the drain region 503.

However, the flash EEPROM using any of the flash EEPROM cells mentioned above and the FLO
When mounting a TOX type EEPROM on the same chip, the following problems arise.

First, among flash EEPROM cells, the ACEE type cell has the most process consistency when mounted together with a FLOTOX type EEPROM. This AC
The EE type cell is a FLOTOX type cell in which the selection transistor is omitted and the drain contact is shared, so if these are added, it becomes a FLOTOX type cell. However, since the ACEE type cell uses a half-select mode during programming, its write/erase operations are complicated and the configuration of its peripheral circuitry is complicated.

On the other hand, in the ETOX type cell, when a selection transistor is provided on the source side for byte erasing, writing with a single power supply (usually 5V) becomes difficult, so two power supplies are used as external power supplies for the chip. (usually 5V system and 12V system), and process compatibility with FLOTOX type cells is poor. The reason is that FLOTOX type cells require a voltage of approximately 20V for writing and erasing, so in addition to the 5V and 12V systems, 2
It is necessary to make three types of 0V series. In addition, as for the types of gate oxide film thickness, the gate oxide film of ETOX type cells and the tunnel oxide film of FLOTOX type cells (approximately 10 nm
m), gate oxide film in peripheral circuit area of ETOX type cell (approximately 2
It is necessary to form a total of four types: a gate oxide film (approximately 45 nm) in the FLOTOX type cell peripheral circuit area, and a gate oxide film (approximately 15 nm) in the logic circuit area.

[0013]

[Problems to be Solved by the Invention] As mentioned above, the conventional FLOTOX type EEPROM cell has a large cell size, and the ACEE type or ETOX type flash EEPROM cell has become larger.
If you try to mount it on the same chip as an EPROM cell,
The structure of the memory peripheral circuit becomes complicated, or two external power supplies are required, resulting in poor process consistency.

The present invention has been made to solve the above problems, and it is possible to reduce the cell size and improve SISO
It is an object of the present invention to provide a nonvolatile semiconductor memory element that simplifies the process when it is mixedly mounted on the same chip as an S-type flash EEPROM cell and can be rewritten in byte units.

The present invention also provides a flash EEPROM.
and byte EEOROM can be mounted together on the same chip through a simple process, and a half-selected state is not required for write/erase operations, making it possible to simplify the configuration of memory peripheral circuits.Moreover, write/erase operations can be performed using a single power supply. An object of the present invention is to provide a nonvolatile semiconductor memory device that can be erased and can be reduced in chip size.

[0016]

[Means for Solving the Problems] A nonvolatile semiconductor memory element of the present invention includes a memory transistor made of a SISOS type flash EEPROM cell, and a memory cell selection transistor connected to the drain side of the memory transistor. Features.

Further, in the nonvolatile semiconductor memory device of the present invention, SISOS type flash EEPROM cells are arranged in rows and columns, and the control gate electrodes and selection gate electrodes of each EEPROM cell in the row or column direction are commonly connected to each other,
Equipped with a flash EEPROM circuit section formed by commonly connecting the drain regions of each EEPROM cell in the column or row direction, a memory transistor formed of a SISOS type flash EEPROM cell, and a memory cell selection transistor connected to the drain side of this memory transistor. SISOS-type byte EEPROM cells are arranged in a matrix, and the control gate electrodes of the memory transistors of each EEPROM cell in the row or column direction are commonly connected to each other, the selection gate electrodes are connected to each other, and the selection gate electrodes of the memory cell selection transistors are commonly connected to each other. Alternatively, it is characterized by comprising a byte EEPROM circuit section formed by commonly connecting the memory cell drain regions of the memory cell selection transistors of each EEPROM cell in the row direction.

[0018]

[Operation] Since the nonvolatile semiconductor memory element has a two-transistor configuration of a memory transistor and a memory cell selection transistor, it is possible to rewrite data in units of bytes. Furthermore, since the memory transistor has the same configuration as the SISOS flash EEPROM cell and can be formed by the same manufacturing process, the memory transistor can be formed using the same manufacturing process.
This simplifies the process when mounting PROM cells on the same chip. In this case, since the memory transistor is formed by self-alignment, the cell size can be reduced.

Further, the nonvolatile semiconductor memory device has S
ISOS type flash EEPROM circuit section and this SI
SI using cells with memory transistors having almost the same configuration as cells in the SOS type flash EEPROM circuit section
An SOS type byte EEOROM circuit section is formed on the same chip. Therefore, writing and erasing operations can be performed using a single power supply (usually 5V), and since a half-selected state is not created for writing and erasing operations, the configuration of the memory peripheral circuit is simplified.
Most of the processes for ROM and SISOS-type byte EEOROM are common, simplifying the process.

[0020]

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a cross-sectional structure of a SISOS type byte EEPROM cell according to a first embodiment of the nonvolatile semiconductor memory element of the present invention. This byte EEPROM cell includes a memory transistor 60a having almost the same configuration as a SISOS type flash EEPROM cell, and a memory cell selection transistor 60b connected to the drain side of this memory transistor.

In the memory transistor (SISOS type flash EEPROM cell) 60a, 601 is a semiconductor substrate of a first conductivity type (for example, a P-type silicon substrate);
611 and 602 are provided on the surface of the semiconductor substrate 601, and are a first impurity region for a drain region and a source region having a second conductivity type opposite to that of the semiconductor substrate (for example, n+ type doped with arsenic or phosphorus). second for
This is an impurity region. Reference numeral 605 denotes one end of the first impurity region 611 on a part of the surface of the channel region between the first impurity region 611 and the second impurity region 602 of the semiconductor substrate 601 via a first gate insulating film (tunnel insulating film) 604. The first gate electrode for the floating gate is provided so as to overlap with the first gate electrode, and is made of, for example, a silicon oxide film formed by thermal oxidation.

Reference numeral 607 denotes an interlayer insulating film (interelectrode insulating film) 606 formed of, for example, a polycrystalline silicon thermal oxide film/CVD silicon nitride film/thermal oxide film on the first gate electrode 605.
This is a second gate electrode for a control gate made of, for example, phosphorus-doped polycrystalline silicon, which is provided through the gate electrode. This second
The gate electrode 607 is formed so as to be self-aligned with the first gate electrode 605 via the interlayer insulating film 606.

Reference numeral 610 denotes a thermal oxide film of, for example, polycrystalline silicon on the side wall of the second impurity region side 602 of the laminated structure of the first gate electrode 505 and the second gate electrode 507.
Side insulating film 60 made of VD silicon nitride film/thermal oxide film
8 and on a portion of the channel region surface.
This is a third gate electrode for the first selection gate provided through the gate insulating film 609. Note that the insulating film (not shown) on the first impurity region 611 for the drain region includes:
No contact openings are provided.

On the other hand, the memory cell selection transistor 6
0b, a third impurity region 612 for a memory cell drain region is provided on the surface of the semiconductor substrate 601, separated from a first impurity region 611 for a drain region of the memory transistor 60a, and a third impurity region 612 for a memory cell drain region is provided on the surface of the semiconductor substrate 601. 6
A fourth gate electrode 614 for a second selection gate is provided on the surface of the channel region between No. 11 and the third impurity region 612 with a third gate insulating film 613 interposed therebetween. The third impurity region 612 is made of a diffusion layer of the same conductivity type as the first impurity region 611 (for example, an n+ type doped with arsenic or phosphorus), and an insulating film (not shown) thereon is formed with bits. A contact aperture with the wire is provided.

The third gate insulating film 613 and the second gate insulating film 609 are made of the same material (for example, a composite film in which a thermal oxide film of substrate silicon/a CVD silicon nitride film/a thermal oxide film are laminated). and formed at the same time. Further, the fourth gate electrode 614 and the third gate electrode 610 have the same material.

SISOS type byte EEP of the above embodiment
According to the ROM cell, it has a two-transistor configuration of a memory transistor and a memory cell selection transistor, so
It is possible to rewrite in byte units. Further, since the memory transistor has the same configuration as the SISOS flash EEPROM cell and can be formed by the same manufacturing process, the process when mounting the memory transistor on the same chip as the SISOS flash EEPROM cell is simplified. In this case, since the memory transistor is formed by self-alignment, the cell size can be reduced. FIG. 2 shows an embodiment of the nonvolatile semiconductor memory device of the present invention.

In this nonvolatile semiconductor memory device, a flash EEPROM circuit section 21 and a byte EEOROM circuit section 22 are formed on the same chip.
It is mounted on a C (integrated circuit) card and used as a ROM part of a microcomputer.

The flash EEPROM circuit section 21 is a conventional SISOS type flash EE having a contact opening in the insulating film over the drain region as shown in FIG.
PROM cell 50 (this is the byte EEP shown in FIG.
This corresponds to a structure in which a contact opening is provided in an insulating film on the drain region 611 of the memory transistor 60a of the ROM cell. ) are arranged in a matrix, the control gate electrodes 507 and first selection gate electrodes 510 of each EEPRO cell in the row or column direction are commonly connected, and the drain regions 503 of each EEPRO cell in the column or row direction are commonly connected. It will be connected.

Furthermore, the byte EEPROM circuit section 22
is a SISOS type flash EEP that does not have a contact opening in the insulating film over the drain region as shown in Figure 1.
A SISOS-type byte EEP comprising a memory transistor consisting of a ROM cell and a memory cell selection transistor connected to the drain side of the memory transistor.
The ROM cells 60 are arranged in a matrix, and the control gate electrodes 607 of each EEPROM cell in the row or column direction, the first selection gate electrodes 610 and the second selection gate electrodes 61
4 are commonly connected to each EEPROM in the column or row direction.
The memory cell/drain regions 612 of the cells are commonly connected to each other.

According to the above nonvolatile semiconductor memory device, S
An ISOS type flash EEPROM circuit section 21 and a SISOS type byte EEOROM circuit section 22 using cells having memory transistors having almost the same configuration as the cells of this SISOS type flash EEPROM circuit section are formed on the same chip. SISOS type flash EE
The OROM cell 50 requires voltage application of 5V to the drain region 503, 12V to the control gate electrode 507, and 2V to the selection gate electrode 510 when writing data.

Here, 12V to the control gate electrode 507
The applied voltage can be created by boosting the external power supply input (5V) with a booster circuit inside the chip because the current flowing is small. It can be produced by lowering the pressure. Further, when erasing data, it is necessary to apply a voltage of 12V to the drain region 503 and 0V to the other gates. At this time,
A current flows in the drain region 503 due to sub-breakdown, but by dividing the cell array into small blocks and performing erasing, the amount of sub-breakdown current flowing in one erase can be reduced, and the required erase voltage of 12V can be reduced from the external power supply. 5V can be generated by internally boosting the voltage.

That is, SISOS type flash EEORO
Flash EEPROMs and byte EEPROMs with M-cell cores maintain the feature of being able to perform write and erase operations with a single power supply. Moreover, since a half-selected state is not created in write/erase operations, the configuration of the memory peripheral circuit is simplified. In addition, SISOS type flash E
Most of the processes for EPROM and SISOS type byte EEOROM are common, and the process is simple.

Furthermore, SISOS type flash EEOR
SISOS type byte EEPROM with OM cell as the core
In the cell, all memory transistors are formed by self-alignment, so the cell size is reduced and the chip size can be reduced.

Next, the SISOS type flash EEPROM cell and the SISOS type byte EEP in the manufacturing process of the integrated circuit equipped with the nonvolatile semiconductor memory device shown in FIG.
An example of a method for forming a ROM cell is shown in FIGS. 3(a) to 3(d).
This will be explained with reference to. Here, only N-channel transistors are shown as peripheral transistors.

First, as shown in FIG. 3(a), (100
) On a P-type silicon substrate 801 having a surface, an N well (not shown) is formed in a predetermined region by ion implantation and thermal diffusion, and then a field oxide film (not shown) is formed by selective oxidation (LOCOS). A region surrounded by this field oxide film is defined as an element region. Subsequently, after channel ion implantation for threshold control is performed in each element region, a first oxide film (tunnel oxide film) 802 with a thickness of about 10 nm is formed by thermal oxidation, and then a first polycrystalline silicon film 803 is formed.
is deposited to a thickness of approximately 100 nm by low pressure chemical vapor deposition (LPCVD), and doped with phosphorus by vapor phase diffusion of POCl3.

Further, after predetermined resist patterning and etching are performed to form cell slits (not shown), the first polycrystalline silicon film 803 is thermally oxidized, LPCV
By depositing a silicon nitride film by the D method and thermally oxidizing the silicon nitride film, a first composite insulating film 804 made of a composite film of silicon oxide film/nitride film/oxide film is formed.

Next, as shown in FIG. 3B, predetermined resist patterning is performed, the composite insulating film 804 and the first polycrystalline silicon film 803 on the memory peripheral circuit area are etched away, and NH4 The first
After removing the oxide film 802 by etching, a second oxide film (memory peripheral circuit gate oxide film) 805 with a thickness of about 25 nm is formed by thermal oxidation, followed by a second polycrystalline silicon film 806.
was deposited to a thickness of approximately 400 nm by the LPCVD method, and PO
Phosphorus is doped by a Cl3 vapor phase diffusion method. After that, predetermined resist patterning is performed to form the second polycrystalline silicon film 806 and the first composite insulating film 804 in the memory area.
, the first polycrystalline silicon film 803 is sequentially etched by reactive ion etching (RIE). As a result, the first polycrystalline silicon film 803 is separated between each cell to form a floating gate 807.
The patterned second polycrystalline silicon film 806 becomes a control gate 808. Next, a predetermined resist patterning is performed, and arsenic ions and phosphorus ions are implanted into the drain side of the memory cell to form a drain region 809.

Further, a predetermined resist patterning is performed, and the second polycrystalline silicon film 806 in the memory peripheral circuit area is etched by RIE. This forms the gate electrode 810 of the memory peripheral circuit.

After this, an oxide film is formed on the second polycrystalline silicon film 806 and the substrate 801 by thermal oxidation, for example, and then a silicon nitride film is deposited by LPCVD and the silicon nitride film is thermally oxidized. A second composite insulating film 811 made of a composite film of oxide film/nitride film/oxide film is formed.

Next, as shown in FIG. 3C, predetermined resist patterning is performed to form the second composite insulating film 811 and the second polycrystalline silicon film 806 on the logic circuit area.
, a first composite insulating film 804 and a first polycrystalline silicon film 803
RIE and chemical dry etching (CDE), respectively.
), and the first oxide film 802 is further etched away using NH4F solution. After this, a third oxide film (logic circuit gate oxide film) 8 is formed by thermal oxidation.
A third polycrystalline silicon film 813 is successively deposited to a thickness of about 400 nm by LPCVD, and is doped with phosphorus by a POCl3 vapor phase diffusion method.

Next, a predetermined resist patterning is performed, and the third polycrystalline silicon film 813 in the logic circuit area and memory area is etched by RIE. As a result, a first selection gate electrode 814, a second selection gate electrode 815, and a logic circuit gate electrode 816 are formed.

Furthermore, as shown in FIG. 3D, a prescribed resist patterning is performed, and the third polycrystalline silicon film 813 remaining on the memory peripheral circuit area and on the drain side of the memory area is etched away by CDE. Next, predetermined resist patterning is performed, and arsenic ions are implanted to form the source region 817 of the memory cell, and the source region 818 and drain region 819 of the n-channel transistor of the memory peripheral circuit and logic circuit. and BF2 in the source and drain regions (not shown) of the p-channel transistor of the logic circuit.
Perform ion implantation.

[0044] After this, for example, BPSG (Boron-Lin-
An insulating film 820 made of silicate glass or the like is deposited by CVD, and after reflowing, a predetermined resist patterning is performed to form a contact hole. Next, as a wiring material, for example, Al (aluminum)-Si (silicon)
An alloy film is deposited by sputtering, a predetermined resist patterning is performed, and etching is performed to form a wiring 821. Subsequently, after sintering, a passivation film 8 is formed.
A desired semiconductor integrated circuit is obtained by depositing 22 and forming a hole in a pad portion.

FIG. 4 shows a cross-sectional structure of a SISOS type byte EEPROM cell according to a second embodiment of the nonvolatile semiconductor memory element of the present invention. Compared to the SISOS type byte EEPROM cell shown in FIG. 1, this byte EEPROM cell has (1) a memory cell selection transistor 70b;
The source region of the memory transistor is not formed by diffusion, and the drain region of the memory transistor (the first impurity region 611
) is used as is, (2) during patterning after depositing the conductive film for forming the fourth gate electrode (second selection gate), the control gate electrode 607 is formed during the formation of the side insulating film 708. By leaving a part of the conductive film on the insulating film 715, the fourth gate electrode (second
The difference is that a part of the selection gate (selection gate) 714 is formed so as to extend and be stacked on the second gate electrode (control gate electrode) 607 via the insulating film 715, but otherwise the diagram is the same. The same symbols as in 1 are given.

SISOS type byte EE with such structure
According to the PROM cell, the distance between the second gate electrode 607 and the fourth gate electrode 714 is set by this SISOS type byte E.
It becomes possible to form a semiconductor integrated circuit smaller than the minimum processing size of a semiconductor integrated circuit including an EPROM cell, and the cell size can be reduced.

[0047]

[Effects of the Invention] As described above, according to the nonvolatile semiconductor memory element of the present invention, the cell size can be reduced,
The process when mounting a SISOS flash EEPROM cell on the same chip becomes simpler, and a SISOS byte EEOROM cell that can be rewritten in bytes can be realized.

Further, according to the nonvolatile semiconductor memory device of the present invention, SISOS type flash EE can be realized with a simple process.
PROM and SISOS-type byte EEOROM can be mounted on the same chip, simplifying the configuration of memory peripheral circuits, and writing and erasing can be performed using a single power supply, making it possible to reduce the chip size. It is suitable for being mounted on an IC card and used as a ROM section of a microcomputer.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing a SISOS type byte EEPROM cell according to a first embodiment of a nonvolatile semiconductor memory element of the present invention.

FIG. 2 is a block diagram showing a first embodiment of the nonvolatile semiconductor memory device of the present invention.

FIG. 3 is a process cross-sectional view showing an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention.

FIG. 4 is a cross-sectional view showing a SISOS type byte EEPROM cell according to a second embodiment of the nonvolatile semiconductor memory element of the present invention.

FIG. 5 is a block diagram showing the general configuration of a microcomputer.

FIG. 6 is a cross-sectional view showing a conventional FLOTOX type byte EEPROM cell.

FIG. 7 is a cross-sectional view showing a conventional ACEE type flash EEPROM cell.

FIG. 8 is a cross-sectional view showing a conventional ETOX-type flash EEPROM cell.

[Figure 9] Conventional SISOS type flash EEPROM
A cross-sectional view showing a cell.

[Explanation of symbols]

60a, 70a...Memory transistor (SISOS type flash EEPROM cell), 60b, 70b...Memory cell selection transistor, 601...Semiconductor substrate, 602...
Second impurity region for source region, 604...first gate insulating film (tunnel insulating film), 605...first impurity region for floating gate
Gate electrode, 606... interlayer insulating film (interelectrode insulating film), 6
07...Second gate electrode for control gate, 608, 708
... Side insulating film, 609... Second gate insulating film, 610... Third gate electrode for first selection gate, 611... First impurity region for drain region, 612... Third impurity for memory cell drain region Region, 613...Third gate insulating film,
614, 714...fourth gate electrode for second selection gate;
715... Insulating film, 21... Flash EEPROM circuit section, 22... Byte EEPROM circuit section.

Claims (8)

[Claims] [Claim 1] SISOS type flash EEPROM
1. A nonvolatile semiconductor memory element comprising a memory transistor made up of cells and a memory cell selection transistor connected to the drain side of the memory transistor. 2. The nonvolatile semiconductor memory element according to claim 1, wherein the memory transistor includes a semiconductor substrate of a first conductivity type and a second conductivity type provided on a surface of the semiconductor substrate and opposite to the semiconductor substrate. a first impurity region for a drain region, a second impurity region for a source region, and a first gate insulating film on a part of the surface of the channel region between the first impurity region and the second impurity region of the semiconductor substrate; a first gate electrode for a floating gate provided via an interlayer insulating film; a second gate electrode for a control gate provided on the first gate electrode via an interlayer insulating film; A first selection gate provided on the side wall of the stacked structure of the gate electrode on the second impurity region side with a side insulating film interposed therebetween, and on a part of the surface of the channel region with a second gate insulating film interposed therebetween. a third gate electrode, the memory cell selection transistor includes a third impurity impurity for a memory cell drain region having a second conductivity type provided at a distance from the first impurity region on the surface of the semiconductor substrate. and a fourth gate electrode for a second selection gate provided on the surface of the channel region between the third impurity region and the first impurity region of the semiconductor substrate with a third gate insulating film interposed therebetween. Characteristic non-volatile semiconductor memory elements. 3. The nonvolatile semiconductor memory element according to claim 2, wherein the second gate insulating film and the third gate insulating film are made of the same material, and the third gate electrode and the fourth gate electrode are made of the same material. A nonvolatile semiconductor memory element characterized in that these are made of the same material. 4. The nonvolatile semiconductor memory element according to claim 2, wherein the distance between the second gate electrode and the fourth gate electrode is smaller than the minimum processing dimension of a semiconductor integrated circuit including the nonvolatile semiconductor memory element. A nonvolatile semiconductor memory element characterized by its small size. [Claim 5] SISOS type flash EEPROM
Arrange the cells in a matrix, and each EEPRO in the row or column direction
A flash EEP in which the control gate electrodes and selection gate electrodes of M cells are commonly connected, and the drain regions of each EEPROM cell in the column or row direction are commonly connected.
A SISO having a ROM circuit section and the configuration according to claim 1.
S-type byte EEPROM cells are arranged in a matrix, and the control gate electrodes of the memory transistors of the EEPROM cells in the row or column direction, the selection gate electrodes of the memory cell selection transistors, and the selection gate electrodes of the memory cell selection transistors are commonly connected to each other. 1. A nonvolatile semiconductor memory device comprising a byte EEPROM circuit section formed by commonly connecting memory cell drain regions of memory cell selection transistors of each EEPROM cell in a row direction. 6. The nonvolatile semiconductor memory device according to claim 5, wherein the SISOS type byte EEPROM cell is the nonvolatile semiconductor memory element according to any one of claims 2 to 4. Non-volatile semiconductor memory device. 7. The nonvolatile semiconductor memory device according to claim 5 or 6, further boosting an external power input to provide a voltage required for the control gate electrode of the SISOS flash EEOROM cell during data writing. 1. A nonvolatile semiconductor memory device comprising a booster circuit that generates a voltage required for the drain region of the SISOS type flash EEOROM cell when erasing data. 8. A nonvolatile semiconductor memory device according to claim 5, wherein the nonvolatile semiconductor memory device is mounted on an IC card.