JPH04364044A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve cut-off frequency and reduce parasitic resistance and parasitic capacity by epitaxial growth a base layer and introducing self alignment process. CONSTITUTION:A silicon film which includes impurity material of a first conductivity type or silicon-germanium alloy is epitaxially grown on a substrate 1 to form a base layer 5. A silicon film which includes impurity material of a second conductivity type is epitaxially grown on the base layer 5 and an emitter layer 6 is formed. Then, the impurity material of a second conductivity type is introduced into the collector leading area of a polycrystal silicon film 9. An oxide film 10 is accumulated on the area. After accumulating an oxide film 11 on the whole plane of the substrate 1, etch back is performed and the oxide film 11 is left on the side wall of a mesa constituted of the oxide film 10 and the polycrystal silicon film 9. Such process of forming the side wall of the oxide film 11 allows the formation of an emitter/contact area 12 by self alignment.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a high-speed bipolar transistor.

0002

[Prior Art] In recent years, high-performance bipolar transistors have been used not only as elements for digital circuits such as processors and memories for high-speed calculations used in computers, but also as elements for analog circuits such as operational amplifiers and comparators, and for mixed digital/analog devices. It is also widely used as a DA/AD converter, and high speed and high integration are required.

By the way, in order to operate this type of bipolar transistor at high speed, it is necessary to reduce the base width and improve the cutoff frequency fT.

Conventionally, methods using low-acceleration ion implantation and solid-phase diffusion have been studied as techniques for controlling the base width of bipolar transistors to make them thinner, and these methods have been successful along with short-time diffusion. Furthermore, recently, in order to suppress the slope of the impurity distribution during ion implantation, a technique for forming a base layer by epitaxial growth has been developed, and has been verified at the level of a single transistor.

[0005]

In the conventional bipolar transistor mentioned above, it has been considered to form a thin base layer by forming the base layer by epitaxial growth. Transistors using such technology can be roughly classified into two types of structures. One is a planar type bipolar transistor, and the other is a mesa type bipolar transistor.

Generally, in a planar type bipolar transistor, a base is epitaxially grown after element isolation is performed using an insulating film. Then, an opening is formed in the insulating film formed on the base, and polysilicon is deposited in the opening, and emitter diffusion is performed to form an emitter. Therefore, the crystalline state of the epitaxially grown base differs greatly depending on whether the base is silicon or an insulating film. For example, the insulating film is made of polysilicon or amorphous silicon. For this reason, when the element isolation region and the active region are brought close to each other, there is a problem in that leakage current occurs in the region where the element isolation region and the active region are in contact due to poor crystalline state.

Furthermore, since the emitter is formed by diffusing polysilicon, control of the base width depends on fluctuations in diffusion conditions and the state of the polysilicon/silicon interface. Furthermore, when forming a thin film base, if the base concentration is low, the base layer will be covered with a depletion layer, causing leakage current to flow between the emitter and collector, and if the base concentration is high, the electric field between the emitter and the base will become stronger. Tunneling current increases. In addition, there are drawbacks such as the inability to freely control the profile of the emitter.To overcome these drawbacks, if the emitter is formed by epitaxial growth, the region where the emitter will be formed is surrounded by an insulating film, so epitaxial growth When performing this process, differences in epitaxial growth rate occur due to differences in crystal orientation.
It is not possible to uniformly embed silicon in a region surrounded by an insulating film. That is, there was a problem that facets were generated.

On the other hand, in mesa-type bipolar transistors, the base is epitaxially grown on a wide area of the silicon substrate, and the emitter is epitaxially grown on top of this, so there are no drawbacks seen in the planar-type bipolar transistors mentioned above. However, the mesa structure has a problem in that it does not match well with the self-alignment process and is not suitable for miniaturization.

By the way, in order to enable high-speed operation of bipolar transistors, it is necessary to improve the cut-off frequency and reduce parasitic capacitance and parasitic resistance.

[0010] When etching the insulating film on the base to form a window that will serve as an emitter, there are the following methods to ensure the thickness of the base formed accurately by epitaxial growth and to prevent damage to the base. . That is, this is a process in which holes are formed in the nitride film formed on the base and the oxide film by anisotropic dry etching, and the exposed oxide film is wet-etched using a solution. However, since a self-alignment process cannot be introduced, parasitic capacitance and parasitic resistance increase, making high-speed operation impossible. Furthermore, side etching of the oxide film increases the emitter area, resulting in a problem in that the emitter-base breakdown voltage deteriorates.

[0011] In view of the above-mentioned problems, an object of the present invention is to
The present invention provides a method for manufacturing a semiconductor device that improves the cutoff frequency, reduces parasitic capacitance and resistance, enables high-speed operation, and prevents deterioration of emitter-base breakdown voltage.

0012

[Means for Solving the Problems] In order to achieve the above-mentioned object, the present invention includes the following steps: forming a collector layer on the surface of a substrate; epitaxially growing a base layer and an emitter layer on the collector layer; A step of sequentially etching and removing the emitter layer and the base layer to expose the collector layer, a step of burying a first insulating film in the recessed portion obtained by the etching and planarizing it, and a step of etching the base layer on the obtained flat surface. a step of sequentially depositing a layer of the same conductivity type as the layer and a second insulating film, the second insulating film on the emitter layer,
A step of sequentially opening holes in the conductivity type layer, a step of forming a sidewall of a third insulating film on the sidewall of the opening, and a step of forming a sidewall of the same conductivity type as the emitter layer around the opening having the sidewall. The method includes a step of forming an emitter electrode.

[0013] Also, a step of forming a collector layer on the surface of the substrate, a step of epitaxially growing a base layer on the collector layer, depositing a first insulating film on the base layer, and etching the first insulating film. forming a sidewall of a second insulating film on a sidewall of the first insulating film;
selectively forming a layer of the same conductivity type as the base layer on the base layer exposed outside the mesa formed by the insulating film and the second insulating film and having the sidewall; and the first insulating film. The method includes the steps of forming an aperture by removing the aperture by wet etching with a solution, and forming an emitter layer within the aperture.

[0014]

[Operation] In the present invention, the base layer is grown epitaxially and a self-alignment process is introduced, so that
The cutoff frequency fT is improved and parasitic resistance and capacitance are reduced. Therefore, high-speed operation of the transistor is possible,
Variations in emitter area and deterioration in emitter-base breakdown voltage are prevented. Furthermore, since the emitter layer is epitaxially grown, it becomes easy to control the emitter impurity distribution and the base width.

[0015]

[Example] Below, an example related to the manufacturing method of the present invention is shown in Fig. 1.
This will be explained based on FIGS. 22 to 22.

First, a high concentration collector layer 2 having a second conductivity type is formed on a semiconductor substrate 1 having a first conductivity type, and
Furthermore, a low concentration collector layer 3 is laminated on the surface of this high concentration collector layer 2. Thereafter, an oxide film 4 for isolation between elements is formed (FIG. 1).

Next, a silicon film containing impurities of the first conductivity type or a silicon-germanium alloy containing impurities of the first conductivity type is epitaxially grown on the substrate 1,
A base layer 5 is formed. Furthermore, a silicon film containing second conductivity type impurities is epitaxially grown on this to form an emitter layer 6. At this time, the base layer 5 on the oxide film 4 does not necessarily have to be a single crystal (FIG. 2)
.

Subsequently, a pattern is formed using photoresist so as to leave the active region and the collector lead-out region, and the emitter layer 6 and base layer 5 are epitaxially grown by anisotropic dry etching using the photoresist as a mask. etching. At this time,
A recess 7 is formed in the emitter layer 6 and the base layer 5 (FIG. 3).

Next, an oxide film 8 is buried in the recess 7 and planarized (FIG. 4).

Subsequently, after depositing a polycrystalline silicon film 9 without impurity doping on the substrate 1, a layer is formed in a region that will become an extraction electrode at the base of the polycrystalline silicon film 9 by a method such as mask ion implantation using a photoresist. 1 conductivity type impurity is introduced. Similarly, impurities of the second conductivity type are introduced into the collector extraction region of the polycrystalline silicon film 9 by a method such as ion implantation using a photoresist mask. Then, an oxide film 1 is formed on the polycrystalline silicon film 9.
0 (Figure 5).

Furthermore, the oxide film 10 and polycrystalline silicon film 9 are sequentially etched by covering the portions of the base that will become the lead-out electrode and the portion that will become the collector lead-out region with a photoresist mask (FIG. 6).

Next, after depositing an oxide film 11 on the entire surface of the substrate 1, it is etched back to leave the oxide film 11 on the sidewalls of the mesa made up of the oxide film 10 and the polycrystalline silicon film 9. By this step of forming sidewalls of the oxide film 11, the emitter contact region 12 is formed in a self-aligned manner (FIG. 7).

Next, a polycrystalline silicon film of the second conductivity type is deposited on the substrate 1 and etched using a photoresist mask so that it remains only around the emitter contact region 12 to form the emitter electrode 13. Form. In this case, the second conductivity type impurity may be introduced into the polycrystalline silicon film at the same time as the polycrystalline silicon film is deposited, or after the deposition by a method such as ion implantation (FIG. 8).
.

Thereafter, a contact hole 10a is opened in the oxide film 10 in the region that will become the base extraction electrode and the collector extraction region.
A metal wiring 14 is formed around the emitter electrode 13 and on the emitter electrode 13 (FIG. 9).

As described above, according to the present invention, after the emitter layer and base layer are formed by epitaxial growth, the oxide film is buried in the recessed portions, so that the crystal state is good even in the portion where the element isolation region and the active region contact. , leakage current, etc. will not occur. Further, in the process shown in FIG. 7, the emitter contact region can be formed by self-alignment, and the device can be miniaturized.

Further, another embodiment will be described with reference to FIGS. 10 to 22.

First, a semiconductor substrate 20 having a first conductivity type is prepared.
After forming a high concentration collector layer 21 having a second conductivity type thereon, a low concentration collector layer 22 having a second conductivity type is formed on the surface of the high concentration collector layer 21. Thereafter, an oxide film 23 is formed to provide isolation between elements. Then, a silicon film containing impurities of the first conductivity type or a silicon film containing impurities of the first conductivity type is formed on the substrate 20 including the above-mentioned constituent elements.
After epitaxially growing a germanium alloy to form a base layer 24, an oxide film 25 is deposited on the base layer 24. At this time, the base layer 24 on the oxide film 23 does not necessarily have to be a single crystal (Fig.
).

Next, using the photoresist pattern formed so as to leave the oxide film 25 except for the area that will become the emitter, the oxide film 25 is anisotropically dry etched, and then a nitride film 26 is formed on the entire surface of the substrate 20. Deposit. Note that since the base layer 24 exposed by the etching is not used as an active region of the transistor, it does not matter if it is slightly damaged or thinned by the dry etching (FIG. 11).

Next, the nitride film 26 is etched by anisotropic dry etching, leaving only the sidewalls of the oxide film 25 (FIG. 12).

The base layer 24 is then etched using a resist pattern, leaving only the region that will become the external base (FIG. 13).

Furthermore, in order to form a highly doped layer for extracting the collector, impurities of the second conductivity type are ion-implanted into the lightly doped collector layer 22 using a resist pattern 27 that has holes only in the collector extracting region. Figure 14).

Thereafter, an oxide film 28 is deposited over the entire surface of the substrate 20 (FIG. 15).

Next, the oxide film 28 is left only in the collector extraction region by etching. This is to prevent the surface of the substrate 20 from being exposed and to ensure selective growth of single crystal silicon, polycrystal silicon, or silicide film in the next step (FIG. 16).

Thereafter, a film 29 is selectively grown on the exposed base layer 24 in the region that will become the external base. Here, as the film 29, single crystal silicon or polycrystalline silicon containing impurities of the first conductivity type, single crystal silicon or polycrystalline silicon containing no impurities, or a metal silicide film is used. However, if the film 29 used is single crystal silicon or polycrystalline silicon that does not contain impurities,
It is necessary to introduce impurities of the first conductivity type later using a method such as ion implantation (FIG. 17).

Next, a nitride film 30 is deposited over the entire surface of the substrate 20 (FIG. 18).

Subsequently, a resist pattern 31 is formed in which holes are formed only on the emitter region (FIG. 19).

Thereafter, the oxide film 25 is removed by etching using a hydrofluoric acid solution. At this time, since a hydrofluoric acid solution is used for etching, the base layer 24 is not etched and is not damaged. Furthermore, since the oxide film 25 to be removed is surrounded by the nitride film 26, there is no possibility of side etching causing the emitter area to vary or increase in size, and even less to cause deterioration of the emitter-base breakdown voltage ( Figure 20).

Subsequently, polycrystalline silicon or single crystal silicon is selectively or non-selectively deposited in the emitter region to form an emitter layer 32. Note that if polycrystalline silicon or single-crystalline silicon is deposited non-selectively, it must be etched later using a resist pattern so that the polycrystalline silicon or single-crystalline silicon remains only in the emitter region (Fig. 21 ).

Subsequently, a contact hole 33 is opened in the region that will become the external base and the collector lead-out region, and a metal wiring 34 is formed on the contact hole 33 and the emitter layer 32 (FIG. 22).

In this way, in the bipolar transistor of this embodiment, since the distance between the emitter and the external base is controlled by the thickness of the deposited nitride film 26, parasitic capacitance and parasitic resistance are small, and a fine transistor can be realized. can be formed,
Speeding up is possible.

[0041]

[Effects of the Invention] As explained above, according to the present invention, the base layer is epitaxially grown and a self-alignment process is introduced, so that the cutoff frequency fT can be improved.
Parasitic resistance and parasitic capacitance are reduced. Therefore, the transistor can operate at high speed, and variations in emitter area and deterioration in emitter-base breakdown voltage can be prevented. Also,
Since the emitter layer is epitaxially grown, the emitter impurity distribution and base width can be controlled.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of the manufacturing process of the method of the present invention.

FIG. 2 is a cross-sectional view of the manufacturing process of the method of the present invention.

FIG. 3 is a cross-sectional view of the manufacturing process of the method of the present invention.

FIG. 4 is a cross-sectional view of the manufacturing process of the method of the present invention.

FIG. 5 is a cross-sectional view of the manufacturing process of the method of the present invention.

FIG. 6 is a cross-sectional view of the manufacturing process of the method of the present invention.

FIG. 7 is a cross-sectional view of the manufacturing process of the method of the present invention.

FIG. 8 is a cross-sectional view of the manufacturing process of the method of the present invention.

FIG. 9 is a cross-sectional view of the manufacturing process of the method of the present invention.

FIG. 10 is a cross-sectional view of another manufacturing process of the method of the present invention.

FIG. 11 is a cross-sectional view of another manufacturing process of the method of the present invention.

FIG. 12 is a cross-sectional view of another manufacturing process of the method of the present invention.

FIG. 13 is a cross-sectional view of another manufacturing process of the method of the present invention.

FIG. 14 is a cross-sectional view of another manufacturing process of the method of the present invention.

FIG. 15 is a cross-sectional view of another manufacturing process of the method of the present invention.

FIG. 16 is a cross-sectional view of another manufacturing process of the method of the present invention.

FIG. 17 is a cross-sectional view of another manufacturing process of the method of the present invention.

FIG. 18 is a cross-sectional view of another manufacturing process of the method of the present invention.

FIG. 19 is a cross-sectional view of another manufacturing process of the method of the present invention.

FIG. 20 is a cross-sectional view of another manufacturing process of the method of the present invention.

FIG. 21 is a cross-sectional view of another manufacturing process of the method of the present invention.

FIG. 22 is a cross-sectional view of another manufacturing process of the method of the present invention.

[Explanation of symbols]

1, 20 Semiconductor substrate 2, 21 High concentration collector layer 3, 22 Low concentration collector layer 4, 10, 11, 23, 25, 28 Oxide film 5, 24
Base layer 6, 32 Emitter layer 9 Polycrystalline silicon film 13 Emitter electrode 14, 34 Metal wiring 26, 30 Nitride film 29 Film

Claims (2)

[Claims] 1. A step of forming a collector layer on a surface portion of a substrate, a step of sequentially epitaxially growing a base layer and an emitter layer on the collector layer, the emitter layer,
a step of sequentially etching away the base layer to expose the collector layer;
burying and planarizing an insulating film, sequentially depositing a layer of the same conductivity type as the base layer and a second insulating film on the obtained flat surface, the second insulating film on the emitter layer, A step of sequentially opening holes in the conductivity type layer, a step of forming a sidewall of a third insulating film on the sidewall of the opening, and a step of forming a sidewall of the same conductivity type as the emitter layer around the opening having the sidewall. 1. A method of manufacturing a semiconductor device, comprising: forming an emitter electrode. 2. A step of forming a collector layer on a surface portion of a substrate, a step of epitaxially growing a base layer on the collector layer, depositing a first insulating film on the base layer, and etching the first insulating film. and leaving a second insulating film on the sidewall of the first insulating film.
a step of forming a sidewall of an insulating film, and a layer of the same conductivity type as the base layer on the base layer formed by the first insulating film and the second insulating film and exposed to the outside of the mesa having the sidewall. a step of selectively forming an aperture, a step of removing the first insulating film by wet etching with a solution to form an aperture, and a step of forming an emitter layer in the aperture. Method of manufacturing the device.