JPH0436229Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a synchronization signal generation circuit that generates a signal synchronized with the cycle of input AC.

A DC-AC exchanger that converts AC into a DC signal generally includes a filter with a long time constant in order to remove ripples at the commercial frequency included in the converted DC output. By the way, switching to direct current requires high speed, but with low ripple,
In addition, in order to achieve a high-speed response, conventional C, R filters or active filters have limited characteristics at commercial frequencies.

In place of such a filter, high-speed response filters are also known, one of which is the interval averaging circuit shown in FIG. In this figure, IG is an integrator,
S is a sample and hold circuit. AC input
After EI is applied to the integrator IG and integrated, it becomes the DC signal EO through the sample-and-hold circuit S, and this output signal is negatively fed back to the integrator IG. In the circuit having this configuration, each time a sample pulse P arrives, an integral output of the difference between the input EI and the output EO is sampled and held and taken out as the output signal EO. Input as sample pulse P
By using pulses synchronized with the EI period,
A DC signal EO, which is the average of the input EI, is output for each section determined by the period of the input EI. In such an interval averaging circuit, the output signal EO is changed stepwise by the difference between the interval averages, so even though the ripple contained in the output signal EO is low, it is different from the conventional C. input AC at extremely high speed compared to R or active filters.
It has the feature of converting EI to DC signal EO.

In such an interval averaging circuit, in order to operate this circuit effectively, it is necessary to synchronize the sampling period with the period of the input AC EI as described above, and for this reason, the sample pulse P is used as the input AC
Requires pulses synchronized with EI. Generally, in such a case, the sample pulse P is obtained using the input EI. However, in that case, if the synchronization signal is no longer generated when the input AC EI is zero or extremely small, the output hold state will continue, resulting in an inappropriate signal as the output signal EO.

The present invention has been made in this regard, and is a simple synchronization signal generation circuit that can reliably obtain pulses P at a predetermined cycle by synchronizing with the cycle of input AC and self-generating when the input is small. This was achieved through the configuration. Note that the circuit of the present invention is not limited to generation of sampling pulses in the interval averaging circuit shown in FIG.
It is applied to various circuits that require pulses synchronized with the input cycle.

FIG. 2 is a circuit diagram of an embodiment of the present invention. In Figure 2, COP is a comparator, DIV is a differentiator,
INV is an inverter and OSC is a multivibrator. IN is the terminal to which AC input EI is applied,
OUT is an output terminal from which the output pulse P is taken out. The pulse P is used as a sample pulse P when the circuit of the present invention is applied to FIG. AC input EI is comparator COP, differentiator circuit DIV,
and added to the multivibrator OSC via the inverter INV.

In multivibrator OSC, NG is C-
The MOS NAND gate and CO are also converters made up of C-MOS NAND gates.

In CO, both input terminals of the NAND gate are short-circuited, making it one input. A threshold voltage exists in a C-MOS NAND gate. As described above, in a NAND gate using an inverter (inverter) with both input terminals shorted and one input, the polarity of the output is reversed when the input exceeds the threshold voltage. That is, when the value of the low level input increases and exceeds the threshold voltage, the output changes from high level to low level, and when the value of the high level input decreases and becomes smaller than the threshold voltage, the output is inverted and becomes high level.
In this way, the CO configured with a NAND gate with one input operates as a comparator.

R1, R2 and R3 are each a resistance element, C
is a capacitor, and D is a diode. One input terminal of the NAND gate NG is connected to the output terminal of the inverter INV, and the other input terminal is connected to the comparator
Connected to the output end of CO. nand gate
The output terminal of NG is connected to the output terminal OUT, and is also connected to the input terminal of the comparator CO via a series circuit of a capacitor C and a resistive element _R3 . The connection point Q between the capacitor C and the resistance element _R3 is connected to the connection point Q through the resistance element _R1 , and also between the diode D and the resistance element
Each is connected to the output terminal of the comparator CO via a series circuit consisting of _R2 . Resistance element R ₁ is
Its value is chosen to be sufficiently large compared to R ₂ . The operation of the circuit of the present invention having such a configuration will first be described in the case where the value of the AC input EI is zero or extremely small.

When AC input EI is zero or extremely small,
The output of the differentiating circuit DIV becomes "L" level, which is inverted by the inverter INV, and becomes "H" level as shown in Fig. 3A, and the multi-valve generator outputs the "L" level.
It will be added to NAND Gate NG, which makes up OSC.
At this time, the OSC does not depend on the AC input signal,
Works as a standalone multivibrator. When the output of the NAND gate NG goes from "L" to "H" level, the output of comparator CO goes to "L" level. In this case, the current passing through capacitor C is
If IC, this current IC flows through the resistive element _R2 via the diode D, and rapidly decreases as shown by A in FIG. 3B with a time constant determined by C and _R2 . Then, when the potential at the connection point Q between the capacitor C and the resistive element _R3 falls to the threshold voltage of the comparator CO, the output of the comparator CO is inverted.
The output level of CO becomes "H" and the output of NAND gate NG becomes "L" level. Then, the current flowing through the capacitor C is blocked by the diode D, so it does not pass through the resistance block _R2 .
It is supplied via _R1 , and its current waveform is as shown by B in FIG. The potential at the connection point Q is the resistance element
The potential increases gradually with a time constant determined by _R1 and C, and when the potential reaches the threshold voltage of the comparator CO, the output level of CO is reversed.
As a result, the output of the NAND gate NG becomes "H" level. Thereafter, the above operations are repeated. In this case, since the resistance element R ₁ has a value sufficiently larger than R ₂ , the signal taken out from the NAND gate NG has a period of “H” level that is sufficiently shorter than a period of “L” level. The pulse signal P as shown in FIG. 3C is obtained. Such a pulse signal P is output from the output terminal OUT.
taken out from

In this manner, the circuit of the present invention can generate a pulse signal P having a predetermined period even if the input EI is zero. Therefore, by using this pulse signal P as a sample pulse in the section averaging circuit shown in FIG. 1, for example, the circuit operates normally even when the input EI is zero.

Next, the case where there is input EI will be explained. This input EI is input by passing through the comparator COP.
It becomes a rectangular wave according to the period of EI. This rectangular wave output is differentiated by a differentiation circuit DIV. This differential output is passed through the inverter INV, so that the output of INV becomes as shown in FIG. 3D. Here, now, the inverter
INV output is “H” level, NAND gate is NG
When the output level of is “L” level, the input
When the output of the inverter INV goes to the "L" level as shown in _A1 in FIG. 3D in accordance with the period of EI, the output of the NAND gate NG is inverted to the "H" level. Therefore, the current IC passing through the capacitor C flows through the resistive element _R2 via the diode D. Then, when the potential at the connection point Q drops to the threshold voltage of the comparator CO, the output of the comparator CO becomes "H" level. As a result, current IC now flows into capacitor C via resistance element _R1 .
The potential at the connection point Q gradually rises, but the inverter INV raises it to the next "L" level according to the cycle of the input EI.
The level signal (A ₂ in Figure 3 D) is a NAND gate
When applied to NG, the output of the NAND gate NG is forced to go high before reaching the threshold voltage of the comparator CO. Therefore,
A signal P shown in FIG. 3E is taken out from the output terminal of the NAND gate NG.

In this way, in the circuit of this invention, the input EI
When is zero or extremely small, the multivibrator is allowed to run freely with a time constant determined by capacitor C and resistive element _R1 , and when input is applied, the multivibrator's oscillation cycle is controlled according to the input cycle. However, in this case, _the resistance element R ₁
and the value of capacitor C are selected. With this configuration, when an input is applied, the output level of the inverter INV becomes "L" before the free-running cycle ends, so the output of the NAND gate NG is inverted, and as a result, this multivibrator Synchronizes with the cycle of the inverter INV output. That is,
When the input EI is applied, the pulse P shown in FIG. 3E corresponding to this input is reliably generated. This pulse signal is taken out from the output OUT.

In this way, the circuit of the present invention is configured to allow the multivibrator to run freely when the input EI is zero or extremely small, and to control the oscillation cycle of the multivibrator according to the input cycle when there is an input. Therefore, it is extremely useful for use in circuits that utilize pulses depending on the input period, such as interval averaging circuits.

[Brief explanation of the drawing]

Figure 1 is an example circuit diagram for explaining the present invention.
FIG. 2 is a circuit diagram of an embodiment of the present invention, and FIG. 3 is a waveform diagram for explaining the operation of the circuit shown in FIG. COP...Comparator, DIV...Differential circuit, INV...
...Inverter, OSC...Multivibrator,
NG...Nand gate, CO...comparator,
C... Capacitor, R ₁ , R ₂ , R ₃ ... Resistance element,
D...Diode.

Claims (1)

[Scope of utility model registration request] A NAND gate configured of C-MOS and a comparator are connected in a subordinate manner, and the output terminal of the NAND gate is connected to the input terminal of the comparator via a capacitor, and the output terminal of the NAND gate is connected to the input terminal of the comparator via a first resistance element. A multivibrator is provided, each of which is connected to one input terminal of the NAND gate through a series circuit of a second resistive element whose resistance value is smaller than that of the resistive element and a diode, and an input alternating current is input to the other input terminal of the NAND gate. configured to be supplied via a comparator, a differentiating circuit and an inverter,
The values of the capacitor and the first resistive element are selected so that the oscillation period of the multivibrator that oscillates when the input AC value is zero or extremely small is longer than the oscillation period when there is input AC. Synchronous signal generation circuit.