SU1462470A1 - Pulsed interference simulator - Google Patents

Abstract

The invention relates to electrical engineering and can be used to control the immunity of equipment. The purpose of the invention is expansion-5; rheniyu functionality by introducing adjustments amplitude, duration and phase shift of the pulses of interference. The device contains a power source 1, an adjustable resistor 7, a trigger 29, a starting block 27, an I element 21. The device includes a power source 2, a low-pass filter 12, adjustable constant-voltage sources 17, 18, comparators 19, 20, shaper 22 pulses, linear voltage generator 23, pulse generator 24, unit 25 de-frequency or frequency, single pulse shaper 26, trigger 30, OR 31 element and delay unit 32. (L

Description

I. one

I The invention relates to electrical engineering, namely, devices | for determining or monitoring the degree of interference to the radio, digital, and other electronic devices from impulse interference. I The purpose of the invention is to expand I functionality of imitation-ipa pulsed noise by introducing adjustments of amplitude and duration of pulses, impulse phase shift in relation to the phase of the mains I voltage and the rate of increase of the I voltage, stabilizing the parameters: pulsed voltage at capacitive-I or shifted active-capacitive load, varying within wide limits.

Figure 1 shows the structural scheme of the device; figure 2 - diagrams; mains voltage, explaining their work j pulse pulse interference. The impulse noise simulator contains the first power supply 1, made, for example, in the form of rectifier 2 and a capacitor 3 connected in parallel to the output of the rectifier 2, the second power source 4, made, for example, in the form of a transformer 5 and capacitor B, connected parallel to the secondary winding of a transformer 5, a resistor 7 with controlled resistance, a first switch 8, for example, a transistor, a diode 9 connected in parallel, and a second switch 10, for example, a thyristor capacitor 11, a low-pass filter 12, made for example e l-shaped link from resistor 13 and capacitor 14, the first and second output buses 15 and 16 of which are the output of a pulse-noise simulator, the first and second sources 17 and 18 of adjustable constant voltage, the first and second comparators 19 and 20

An E13 element 21, a pulse shaper 22, a linearly increasing voltage generator 23, a pulse generator 24 in series, a frequency division block 25 and a single pulse shaper 26, a start block 27 containing a key 28, first and second triggers 29 and 30, a logical element OR 31 and block 32 delay.

First exit bus first isg. point 1 is connected to the first pin of the resistor 7, the second pin of which is connected to the input of the first key 8. The output of the last pin is connected to the cathode of diode 9, the first pin of the condenser 11, the first input bus of the filter 12 and the output of the second key 10. The second terminal of the capacitor 11 0 is connected to the second input bus 8 of the filter 12 and the first output bus of the second source 4, the second output bus of which is connected to the anode of the diode 9, the second output bus of the first source 3, the input of the second switch 10 and the first input of the first j comparator 19. Second entry last connected to the output of the first source 17.

 The control input of the first key 8 is connected to the output of the logic element 21, the first input of which is connected to the output of the first comparator 19. An additional output of the second source 35 is connected to the input of the driver 22, the direct output of which is connected to the input of the generator 23. Output the latter is connected to the first input of the second comparator 20, the second input 40 of which is connected to the output of the second source 18.

The inverse output of the imaging unit 22 is connected to the reset input of the second trigger 30, the synchronization input of which is connected to the output of the macerator5

20

1462470

l 26. The synchronization input of the latter in turn is connected to the output of the first trigger 29, the second input of the logic element 21 is connected to the output of the imager 26. The output of block 27 is connected to the information input and the inverse reset input of the first trigger 29.

The output of the second comparator 20 is connected to the input of the block 32. The inverse output of the imager 22 is connected to the first input of the logic element OR 31, the second input of which is connected to the output of the second trigger 30, and the third input to the output of the block 32. The output of the second comparator 20 is connected to the synchronization output the first trigger 29 and with the information input of the second trigger 30. The output of the logic element OR 31 is connected to the control input of the second key 10.

The impulse noise simulator operates as follows.

In the initial state, the AC supply voltage is supplied to the sources 1, 4, 17, 18. The capacitor 3 is charged. A variable voltage is applied to the capacitor 6. The former 22 forms, from a sinusoidal input voltage (diagram Q in Fig. 2), two rectangular voltages — in-phase with the input r.-. voltage diagram & figure 2) and antiphase him.

The common-mode rectangular voltage is applied to the generator 23 and, synchronously with the mains voltage, periodically starts it (diagram b in figure 2). The rising voltage is compared by the comparator 20 with the adjustable constant voltage of the source 18, and if the first voltage exceeds the second, the pulse arrives at the triggers 29 and 30 (diagram iiHa figure 2) .1.

The key 28 of the block 27 in the initial position is closed. Therefore, the flip-flop 29 is reset and blocks the passage of voltage pulses (G diagram in Fig.2), coming through block 25 from generator 24 to shaper 26, through this shaper. Therefore, the trigger 30 is reset first after the device is turned on with a pulse at the inverse output of the driver 22 and then saves the reset state.

right g che

that ne on on

10 peo mec pi

15 and li gi st

l al di

25 CI and but not on

30 ZO and Lego

3g fi so then wah

27 Sat

45 pu ag pi ho fi od ix. fuck them

55 ry on

40

50

19 cl

0

The voltage of the rectangular form, antiphase network, from the output of the imaging unit 22 is supplied through the logical element OR 31 to the key 10

in such a way that every first half-period of the mains voltage to the load flows through the switch 10 which closes for this time, and the second sub0 period through the diode 9. During a reactive load, a phase shift occurs between the current and the voltage in the switch 10 circuit. lock it at the time when the current

5 and the voltage in its circuit have different signs, through block 32 and the logic element OR 31, a switch voltage is supplied to the key 10, which improves the shape of the sinusoidal component of the output voltage.

Since there are no pulses at the output of the imager 26, the logical element I 21 is locked and the key 8 is in the open state. Ta

5 IMDs, on output lines 15 and 16, there is an alternating sinusoidal voltage with a slight phase lag relative to the mains voltage due to three phase-shifting elements: the internal resistance of source 4 and the capacitor 6} with the resistance of an open diode 9 or public key 10 and condenser 11

g filter 12 low frequencies. The choice of the corresponding parameters of the elements can make this phase lag arbitrarily small (the interval TO ... T1 in Fig.2).

When key 28 is opened in block 27 (time T2 in FIG. 2, level 1 is set at the reset inputs and information trigger 29 (chart T in figure 2), and the closest pulse from the output of comparator 20 is 5 (chart g in figure 2 ) writes 1 to the trigger 29. 1 at the output of the trigger 29 (diagram f in figure 2) allows the single imager 26 to extract from the input series (diagram Ж in figure 2). The nearest pulse equal in duration to the half-period of the input pulse train This pulse (chart

5 in FIG. 2) at time T4, the logic element I 21 and voltage 1 s in the code of the comparator are open.

0

0

19 enters through the element And 21 on the key 8, which causes its closure.

The current through the switch 8 and the resistor 7 closes the diode 9 and charges the capacitor 11 from source 1 until the reverse voltage on diode 9 exceeds the voltage from source 17. Once this happens, the output of the comparator 19 is set level O, and through the element I 21 he I opens the key 8.

I After that, due to the feedback on the diode 9, the voltage at the output of the source 17 is maintained. At | this 6m, the switch 8 periodically closes | and opens (diagram l in figure 2), | At the end of the pulse at the output of the former 26 (time T5 in Fig. 2) | key 8 is closed, the trigger 30 is written by | logical unit (diagram | Fig. 2), which passes through the logic element RSHI 31 | to key 10 (chart for Fig. 2 ) and opens it, causing a quick spread of capacitor 11 through source 4. This ends the formation of a pulse. Due to the series connection of sources 1 and 4, the generated I pulse is summed with the sinusoidal voltage (diagram m; fig.2) and the sum after smoothing the teeth on the top of the pulse 12 is fed to the output of the device.

; The use of inductive elements in the filter 12 is undesirable, since I may produce resonant waves that disturb the operation of the reverse circuit.

the voltage is made by changing the output voltage of the source 18; adjusting the amplitude of the pulse with a change in output voltage

source 17, the adjustment of the pulse pulse duration - by changing the resistance of the resistor 7; regulation- ka base pulse duration 10 by changing the division factor of the frequency divider 25.

In addition to expanding the functionality and stabilizing the pulse shape, the advantage of the proposed 15 pulse noise simulator compared to the known ones is that the summation of the pulse and continuous components of the output voltage in it is carried out without

20 of a transition capacitor, which makes it possible to form long-duration rectangular pulses without decay of the apex, and the use of a delay unit allows the shape of the output voltage to be improved.

Claims (1)

1. The impulse noise simulator containing the first power source, capacitors, adjustable resistor, first trigger, trigger unit and AND element, the output of which is connected to the control input of the first key, the output of which is connected to the first output of the capacitor, about the aphid. a pulse of pulses (comparator 19, element And 21 and key 8), Choosing capacitors 3 and 6 are larger than the capacitance of the capacitor 11, and the capacitance of the capacitor 11 is greater than the maximum capacity neither the functionality, 40 of it, the second key, the impulse pulse, the second trigger, as well as the second power source, the first and the second constant voltage source, diode, fil load, you can provide the necessary. 45 low frequency oscillator linear The stability of the form of the impulse voltage. The use of a stable oscillator 24, for example, stabilized by a quartz resonator in frequency, makes it possible to obtain a stable pulse base duration, and using stabilized sources 17 and 18 ensures stability, respectively, of the amplitude of the pulses and its phase shift relative to the phase of the AC network. Adjustment of the base shift relative to the network network functionality, 40 entered a second key, a pulse generator, a second trigger, as well as a second power source, the first and second adjustable constant voltage source, a diode, a filter 0 five the first and second comparators, a pulse generator, a frequency division unit, a single pulse shaper, an OR gate, a delay unit, the first output bus of the second power source connected to the second capacitor terminal, the first output bus of the first power source connected. through an adjustable reactor with the input of the first key, the first input of the element I is connected to the output of the first comparator whose first input is connected to the second output busbars of the power sources and to the diode anode parallel to The second key is connected to it, the cathode of the diode is connected to the output of the first key and to the first input bus of the low-pass filter, the second input bus of which is connected to the second capacitor output, the first input of the second comparator is connected to the output of the linear and auxiliary voltage generator the voltages are connected respectively to the second inputs of the comparators, the auxiliary output of the second power source is connected to the input of the pulse shaper, direct gr. the stroke of which is connected to the generator input of the linearly increasing voltage, and the inverse output is connected to the reset input of the second trigger and to the first input of the OR logic element, the second input of which is connected to the output of the second trigger, and the output connected to the control switch of the second key, output the start block is connected to the information input and the reset input of the first trigger, output. which is connected to the control input of the single pulse generator, the output of which is connected to the second input of the logic element And and to the synchronization input of the second trigger, whose information input is connected to the synchronization input0 of the first trigger and to the output of the second comparator, the output of the pulse generator is connected to a clock input of the single pulse generator, a delay block input is connected to the output of the second comparator, the output of the delay block is connected to the third input of the logic OR, while the reset input of the first trigger is inverse, the output of the low-pass filter is the output of the impulse noise simulator,. 2, the simulator according to claim 1, characterized in that the second power source is made in the form of a transformer, parallel to the secondary winding of which a capacitor is connected. s and uI I I h П n.n rl nhjjjn l p. i / and I THAT TG 72 FIG 2 X t I nj I N p nl n ifl g nJ II II P 4U4 II II th P 7G