JPH04361326A - Valid bit retrieval circuit - Google Patents

Abstract

PURPOSE:To retrieve the presence/absence of valid bits and the positions of those bits with a simple circuit to retrieve and output the presence/absence of the valid bits '0' or '1' in a bit train and the positions of those valid bits. CONSTITUTION:A first step retrieves the presence/absence of the valid bits for every 2 bits and outputs a bit search signal and a bit position signal to the second step. A (k)-th (0<k<=N) step of an arbitrary (i)-th step (2<=i<=n) from the second step to the final (n)-th step inputs bit search signals F1 and F2 outputted from 2k-th and 2k+1-th bits in the (i-1)-th step and bit position signals (P1 and P2) expressed by 1-1 bits to a multiplexer 1 in the (i)-th step, and the input of the multiplexer 1 is selected by the bit position signals (P1 and P2) of the 2k-th or (2k+1)-th bits. One bit of the bit search signals F1 and F2 of the 2k-th or (2k+1)-th bit is added to the output signal of i+1 bits from the multiplexer 1, and a bit position signal F of the (i)-th step expressed by (i) bits is outputted to the next (i+1)-th step.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a valid bit search circuit for searching and outputting the presence or absence of a valid bit of 0 or 1 in a bit string and the position of the valid bit. In computers, for example, whether or not to perform a certain control is determined by whether or not a valid bit is set at a specific position in an operand of an instruction code stored in an instruction register, and whether or not there is a valid bit in a bit string is determined. A hardware effective bit search circuit is used to search for bit positions. This effective bit search circuit is generally configured as a multi-input priority encoder, but as the number of bits increases, the gate circuit becomes more complex, and improvements in this point are desired.

0002

2. Description of the Related Art As a conventional effective bit search circuit, for example, one shown in FIG. 4 is known. Figure 4 shows a 2M bit string (a0,...aN-2, aN-1, aN
), and outputs a bit search signal (Found signal) F indicating the presence or absence of valid bit 1 in this bit string, and a bit position signal P expressed as log2 (N+1) bits indicating the bit position of valid bit 1. It shows the case.

That is, the most significant bit aN is sent to the encoder 3.
is input directly, and for the lower bits aN-1 to a0, AND gates 4N-1 to 40 are provided, and the own bits are input as they are, and the upper bits are inverted and input. Therefore, among the valid bits 1 in the bit string, the most significant bit 1 is selected preferentially and inputted to the encoder 3, and the encoder 3 log2 (N+1) bits indicating the input bit position of the valid bit 1. This constitutes a multi-input priority encoder circuit that outputs a bit position signal P of .

For example, an 8-bit string (a0 to
In the case of a7), the encoder 3 sends 3 bits (
A bit position signal P of log2(N+1)=log28=3) is output. Furthermore, the bit string (a0,...
・Each bit of aN-2, aN-1, aN) is OR
It is input to gate 5 and outputs a bit search signal (Found signal) F indicating the presence or absence of valid bit 1. This bit search signal becomes F=1 if a valid bit 1 exists (search success), and F=0 if a valid bit 1 does not exist (search unsuccessful).

Note that FIG. 4 takes as an example a 1 search that searches for valid bit 1, but for a 0 search that searches for valid bit 0, the bit string (a0, . . . aN-2,
aN-1, aN) may be inverted and input.

[0006]

[Problems to be Solved by the Invention] However, such conventional effective bit search circuits use a multi-input priority encoder circuit in which an AND gate is provided for each lower bit except the most significant bit. The number of inputs to the AND gate in the bit position with low priority increases according to the length of the bit string, and N+1 inputs are made to the AND gate in the least significant bit, making the circuit considerably complicated. there were.

The present invention has been made in view of these conventional problems, and an object of the present invention is to provide a valid bit search circuit that searches for the presence or absence of a valid bit and the bit position using a simple circuit.

[0008]

[Means for Solving the Problems] FIG. 1 is a diagram illustrating the principle of the present invention. First, the present invention uses 2M bit strings a0, a1
, a2 , . . . aN-1 , aN , search for the presence or absence of a valid bit in M bits (however, M=lo
The target is a valid bit search circuit that outputs a bit position signal P of g2 (N+1)).

In the present invention, as shown in FIG. 1(a), such a valid bit search circuit first searches for the presence or absence of a valid bit every two bits in the first stage and generates a bit search signal. The bit position signal is output to the second stage. Also, the kth (0<k≦2M−i+
1-1) is configured as shown in the general form of FIG. 1(b).

That is, regarding the bit position signal P, the bit position represented by the bit search signals F1 and F2 outputted from the 2k-th and 2k+1-th bits of the previous i-1 stage and the i-1 bit. Signals P1 and P2 are input to the i-th stage multiplexer 1. The multiplexer 1 selects and outputs an input based on the 2kth or 2k+1st bit position signals P1 and P2. Furthermore, 1 bit of the 2k-th or 2k+1-th bit search signals F1, F2 is added to the i+1-bit output signal from multiplexer 1, and the i-th bit position signal F expressed by i bits is converted to the next i+
Output to the first stage.

On the other hand, regarding the bit search signal F, 2
k-th or 2k+1-th bit search signals F1, F2
is input to the OR gate 2 to generate the i-th bit search signal F.
output to the next (i+1)th stage. Figure 1 (b) like this
) is repeated from the second stage to the last nth stage in FIG. 1(a).

The valid bit search circuit of the present invention searches for the presence and position of bit 0 or bit 1 in a 2M bit string as a valid bit. Further, the multiplexer 1 performs a forward search to output a bit position signal indicating the bit position of bit 0 or 1 standing at the lowest bit position in the 2M bit string. Also multiplexer 1
performs a backward search which outputs a bit position signal indicating the bit position of bit 0 or 1 standing at the highest bit position in the 2M bit string.

[0013]

[Operation] According to the effective bit search circuit of the present invention having such a configuration, from the second stage onward, the so-called low-input priority encoders, which are composed of multiplexers and OR gates having the same configuration, are hierarchically arranged in a pyramid shape. By using multiple small-input priority encoders with the same configuration and prioritizing them among the ones belonging to the same hierarchy, and repeating this configuration as the number of stages increases, it is possible to effectively function as a multi-input priority encoder. A bit search circuit can be easily configured.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 is a circuit diagram showing an embodiment of the present invention for searching for the presence or absence of a valid bit in a 4-bit string and the position of the valid bit. In FIG. 2, each of the 2M = 24 bit strings a0, a1, a2, a3 is
First, search select circuits 10-1, 10-2, 10-3
, 10-4. A 0/1 search select signal is given to the search select circuits 10-1 to 10-4, and when a 0 search is selected, the bit strings a0 to a3 are output as they are, and when one search is performed, the bit string a is output.
A signal obtained by inverting 0 to a3 is output. In the following embodiment, a case where 0 bit search is selected will be taken as an example.

A first stage circuit section is provided following the search select circuits 10-1 to 10-4. The first stage circuit section performs a bit search for every two bits in the bit strings a0 to a3 and outputs a bit search signal (FOUND signal) indicating the presence or absence of valid bit 0 and a bit position signal indicating the bit position of valid bit 0. .

That is, bits a0 and a1 are input to an OR gate 11 equipped with an inverting input, and inverted by an inverter 12 to generate a bit search signal F1 indicating whether or not there is a valid bit 0 among bits a0 and a1. Output. bit a
2, a3 as well, OR gate 1 with inverted input
3 and an inverter 14, bits a2 and a3
Bit search signal F indicating whether valid bit 0 is included in
Outputs 2.

Now, the bit strings a0 to a3 are [1011
], the output of the OR gate 11 becomes 1, and therefore the bit search signal F1 from the inverter 12 becomes F1=0, indicating the existence of a valid bit 0. On the other hand, OR
Gate 13 receives input of bits a2 = a3 = 1 and produces an output of 0, and the bit search signal F2 from inverter 14 becomes 1, indicating that there is no valid bit 0 in bits a2 and a3.

As for the bit position signal indicating the position of the effective bit in the first stage, the output of either bit a0 or a1 or bit a2 or a3 is used as is. In the second stage, the bit search signals F1 and F2 obtained by combining two bits each in the first stage and the bit position signal are input to multiplexers 1-1 and 1-2, respectively. Here multiplexer 1-1,1
-2 is provided because the multiplexer 1-1 performs a forward search for valid bit 0 to determine the bit position, and the multiplexer 1-2 performs a backward search to determine the bit position. be.

That is, the forward search by the multiplexer 1-1 searches for bit 0, which stands at the lowest bit position in the bit string a0 to a3, as a valid bit and outputs bit 1. On the other hand, the backward search of the multiplexer 1-2 searches for bit 0, which stands at the highest bit position in the bit strings a0 to a3, as a valid bit and outputs a bit position signal.

Multiplexer 1-1 for forward search
and the multiplexer 1-2 that performs reverse direction search are both N
It has the same circuit configuration as a 4-input priority encoder including AND gates 20 and 21 and an OR gate 22 with an inverted input. Therefore, the multiplexer 1-1 performs a forward search of the bit strings a0 to a3 and performs an OR operation.
A 2-bit bit position signal is generated by adding a signal OF1 consisting of the first stage bit search signal F1 to the output signal OF0 from the gate 22.

Specifically, bit string a0 to a3 =1
When the value is 011, OF1, OF0=01, indicating that bit a1 has a valid bit 0.

On the other hand, multiplexer 1-2 outputs bit string a
A backward search is performed for 0 to a3, and the valid bits are determined by the backward search using 2 bits, which is the signal OB0 inverted by the inverter 25 and the OB1 signal given by inverting the first stage bit search signal F2 by the inverter 26. Indicates bit position. Specifically, bit strings a0 to a3
=1011, OB1, OB0=01, indicating that valid bit 0 is in bit a1.

Furthermore, the bit search signals F1 and F2 from the first stage are inputted to the OR gate 23 having an inverting input at the second stage, and the output of the OR gate 23 is inverted by an inverter 24 to select the bits in the bit string a0 to a3. A bit search signal F3 indicating the presence or absence of a valid bit 0 is output. Bit string a0 = a
3 = 1011, the bit search signal F3 is F3 =
It becomes 0, indicating the existence of a valid bit of 0.

Of course, the bit position signals OF1, OF0 and OB1, OB0 have meaning only when bit search signal F3=0, indicating the existence of valid bit 0, and the bit position signals OF1, OF0 and OB1, OB0 have meaning, indicating that there is no valid bit 0. When signal F3=1, bit position signals OF1, OF0 and OB1, OB
0 is meaningless. FIG. 3 is a circuit diagram showing another embodiment of the present invention for processing an 8-bit string. In the embodiment of FIG. 3, search select circuits 10-1 to 10-8 are provided following the bit strings a0 to a7, and similarly to the embodiment of FIG. Search can be selected.

Following the first stage, the first stage circuit in FIG.
The circuit is provided in the direction of the bit string. That is, the bit strings a0 to a3 are the same as in the first row of FIG.
The remaining bit strings a4 to a7 are newly collected 2 bits at a time and sent to OR gates 15 and 17 and inverter 1.
A circuit consisting of inverters 16, 18 is provided.
Bit search signals F3 and F4 indicate the presence or absence of valid bit 0 in bits a4 and a5 and bits a6 and a7.
is outputting.

In the second stage, two circuits of the second stage shown in FIG. 2 are provided in the direction of the bit string. That is, bit string a0 to a3
The multiplexer 1-1 that performs a forward search and the multiplexer 1-2 that performs a backward search are the same as those in the embodiment shown in FIG.
Multiplexer 1-3 that performs forward search of ~a7
A multiplexer 1-4 is provided for performing a backward search.

Multiplexers 1-3 and 1-4 are both NA
It includes ND gates 20 and 21 and an OR gate 22. In addition, the bit search signal indicating the presence or absence of valid bit 0 in bit strings a0 to a3 is sent to OR gate 2 as in the case of FIG.
3 and inverter 24 as bit search signal F5, and bit strings a4 to a7 are output as bit search signal F6 by OR gate 26 and inverter 27.
is being output.

The third stage circuit has the function of an 8-input priority encoder that encodes the bit positions of the 8-bit bit string a0 to a7 by forward search, and similarly to the multiplexer 1-5, the bit positions of the bit string a0 to a7 are valid. A multiplexer 1-6 is provided as an 8-input priority encoder for encoding bit positions by backward search.

The third-stage multiplexers 1-5, 1-6 are composed of four NAND gates 30, 31, and 30, each having 8 inputs.
33, 34, an OR gate 32 with an inverted input that combines the outputs of the NAND gates 30 and 31, and an OR gate 32 with an inverted input that combines the outputs of the NAND gates 33 and 34.
A gate 35 is provided. The outputs of the OR gates 32 and 35 of the multiplexer 1-5, which generate the encoded output of the bit position by the forward search of the bit string a0 to a7, are the OF0 signal and the OF1 signal from the lower bit, and the 2
A 3-bit bit position signal to which the OF2 signal consisting of the bit search signal F5 of the stage is added is output.

Here, the 8-bit bit string a0 to a7
= 10111011, the bit position signal (OF2, OF1, O
F0)=001, indicating that valid bit 0 is in bit a1. On the other hand, the outputs of the OR gates 32 and 35 from the multiplexer 1-6, which produce the encoded output of the bit position of the valid bit by the backward search, are inverted by inverters 38 and 39, respectively, and the OB0 signal and OB
1 signal, and 3-bit bit position signals (OB2, OB1, OB0) obtained by adding OB2, which is obtained by inverting the second-stage bit search signal F6 by an inverter 40, are used to search the bit string a0 to a7 in the reverse direction to find the valid bit 0. Indicates bit position.

Specifically, a0 to a7 = 10111
In the case of 011, the bit position signal (O
B2, OB1, OB0) = 101, and 101 is 10
Since it is 5 in decimal, the valid bit is 0 by backward search.
is in bit a5. Furthermore, the bit search signals F5 and F6 from the second stage are collected by an OR gate 36 with an inverting input provided in the third stage and inverted by an inverter 37, so that the effective bit 0 in the bit string a0 to a7 is
If the bit string a0 to a7 = 10111011, the bit search signal F7 becomes 0, indicating that a valid bit 0 exists. Of course, if bit search signal F7=1 and there is no valid bit 0, bit position signals (OF2 to 0) and (OF2 to 0) from multiplexers 1-5 and 1-6 are
B2-0) are meaningless and ignored as bit position signals.

In the above embodiment, the search select circuit selects bit 0 existing in the bit string as a valid bit.
The search was taken as an example, but for a search in which bit 1 existing in a bit string is the valid bit,
By inverting the input bit string with a bit select circuit and outputting it, it is possible to search for the presence or absence of a valid bit 1 included in the bit string and the bit position of the valid bit 1 in exactly the same way as in the case of 0 search.

Furthermore, although the above embodiment takes as an example the search for 4-bit and 8-bit bit strings, the number of bit strings can be increased to 16 bits, 32 bits, and 64 bits in exactly the same way. If the bit string is increased to 2M as the bit string increases, an effective bit search circuit with M stages is constructed, and for the second and subsequent stages, each stage increases by converting the multiplexer into a 4-input priority encoder, an 8-input priority encoder, It is sufficient to use a 16-input priority encoder or a 32-input priority encoder, and the priority encoder in each stage can be expanded by adding a 4-input priority encoder circuit to satisfy the required number of output inputs, and the 4-input priority encoder circuit in the second stage is sufficient.
By adding a circuit using the input priority encoder as a basic unit, it is possible to realize a multi-input priority encoder circuit that easily searches for valid bits.

[0034]

As described above, according to the present invention, a simple circuit can be realized in which a plurality of multiplexers each having a small number of input priority encoders having the same configuration, for example, a 4-input priority encoder, is used as the number of circuit stages increases. With this configuration, it is possible to realize a so-called multi-input priority encoder that searches for the presence or absence of valid bits in a bit string and the bit position.

[Brief explanation of drawings]

[Fig. 1] Diagram explaining the principle of the present invention

FIG. 2 is an embodiment circuit diagram showing an embodiment of the present invention that processes a 4-bit string.

FIG. 3 is an embodiment circuit diagram showing another embodiment of the present invention that processes an 8-bit string.

[Figure 4] Explanatory diagram of a conventional circuit using a multi-input priority encoder circuit

[Explanation of symbols]

1: Multiplexer 1-1, 1-3: Multiplexer (forward search 4-input priority encoder) 1-2, 1-4: Multiplexer (reverse search 4-input priority encoder) 1-5: Multiplexer (forward search 8-input Priority encoder) 1-6: Multiplexer (reverse search 8-input priority encoder) 2: OR gates 10-1 to 10-8: Search select circuits 11, 13,
15, 17, 22, 23, 26, 32, 35, 36:O
R gates 12, 14, 16, 18, 24, 27, 37, 38-4
0: Inverter

Claims (5)

[Claims] Claim 1: 2M bit string (a0, a1, a2
, ...aN-1, aN), and a bit search signal (F) indicating whether or not the search for the valid bit is successful and the position of the valid bit when the search for the valid bit is successful. M bits indicating (however, M=log
In a valid bit search circuit that outputs a bit position signal P of 2 (N+1)), the first stage searches for the presence or absence of a valid bit every two bits, and the bit search signal and bit position signal are transmitted to the second stage. from the second stage to the last M
For the k-th (however, 0<k≦2n-i+1-1) of any i-th stage (however, 2≦i≦M) between the stages,
The bit search signals F1 and F2 output from the 2kth and 2k+1th stages of the previous i-1 stage and i-
The bit position signals P1 and P2 represented by 1 bit are input to the i-th stage multiplexer 1, and the input of the multiplexer 1 is input to the 2k-th or 2k+1-th bit position signal P1,
P2 and further select i+ from multiplexer 1.
Adding 1 bit of the 2k-th or 2k+1-th bit search signals F1 and F2 to the 1-bit output signal and converting the i-th bit position signal F expressed by i bits to the next i+
The configuration is such that the bit search signal F of the i-th stage is outputted to the first stage, the 2k-th or 2k+1-th bit search signals F1 and F2 are input to the OR gate (2), and the bit search signal F of the i-th stage is output to the next i+1-stage. A valid bit search circuit characterized by repetition. 2. In the effective bit search circuit according to claim 1, bit 0 in a 2M bit string is used as the effective bit.
1. A valid bit search circuit, characterized in that it searches for the presence/absence and position of a valid bit. 3. In the effective bit search circuit according to claim 1, bit 1 in a 2M bit string is used as an effective bit.
1. A valid bit search circuit, characterized in that it searches for the presence/absence and position of a valid bit. 4. In the effective bit search circuit according to claim 1, said multiplexer 1 outputs a bit position signal indicating the bit position of bit 0 or 1 located at the lowest bit position in the 2M bit string. An effective bit search circuit characterized by performing forward search. 5. In the effective bit search circuit according to claim 1, the multiplexer 1 outputs a bit position signal indicating the bit position of bit 0 or 1 located at the highest bit position in the 2M bit string. An effective bit search circuit characterized by performing a backward search.