JPH043598B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory having a CMOS transistor, and particularly to a semiconductor memory having a CMOS transistor.
This invention relates to an output circuit system using both channel MOS transistors and p-channel MOS transistors.

[Conventional technology]

This invention is most applicable to a dynamic MOS RAM constructed using CMOS transistors, so it will be explained using this.

With the increase in the capacity of dynamic MOS RAM,
CMOS circuits are being widely applied due to their high speed and low power consumption. By the way, RAM
CMOS is leading the way in static MOS RAM.

FIG. 3 is a circuit diagram of a data output stage used in a general static MOS RAM. In the figure, the load transistor Q1 is a p-channel
It consists of a MOS transistor, and its drain is connected to the power supply Vcc (usually +5V), its source is connected to the output terminal _D0 , its gate is connected to the clock _φ1 , and its substrate is connected to the power supply Vcc. The driver transistor Q ₂ is composed of an N-channel MOS transistor, and its drain is connected to the output terminal D ₀
The source is connected to ground level Vss, and the board is also connected to Vss.

4 is a cross-sectional view of the structure of the data output stage in FIG. 3, in which 1 is a p-type semiconductor substrate, 2 is an N-well formed in the p-type semiconductor substrate 1, and a
This becomes the substrate for MOS transistor _Q1 . 3 is a p ⁺ diffusion region that forms the drain of the p channel MOS transistor Q ₁ made in the N-well, 4 is a p ⁺ diffusion region that forms the source, 5 is an electrode region that forms the gate, and 6 is a p + diffusion region that forms the source. N ⁺ diffusion region forming the drain of the N-channel MOS transistor _Q2 made in the type semiconductor substrate 1, and N ⁺ diffusion region 7 forming the source.
A diffusion region, 8 is an electrode region forming a gate, 9 is an N ⁺ diffusion region for connecting the N-well 2 to the power supply Vcc, and 10 is an electrode region for connecting the p-type semiconductor substrate 1 to the ground level.
It is a p ⁺ diffusion region to connect to Vss.

The data output stage of the static MOS RAM is constructed as described above, and its operation is a simple inverter operation, so a detailed explanation of its operation will be omitted.

By the way, in the dynamic MOS RAM, conventionally, a negative voltage VBB of about -3V is usually applied to the p-type semiconductor substrate of the N-channel MOS transistor. This is necessary to prevent electrons generated from the p-n junction from being injected into the p-type semiconductor, and requires a negative voltage of about -3V.
VBB has been generated on-chip since 64k bit dynamic MOS RAM.

Figure 5 shows a dynamic output stage based on the data output stage used in the static MOS RAM shown in Figure 3, in which only the p-type semiconductor substrate of the N-channel MOS transistor (driver transistor Q2) is connected to the negative voltage VBB. FIG. 3 is a circuit diagram of a data output stage used in MOS RAM.

FIG. 6 is a structural sectional view of the data output stage of FIG. 5, and 1 to 9 are completely the same as those in FIG. 3.
11 is a p ⁺ diffusion region for connecting the p-type semiconductor substrate 1 to the negative voltage VBB generated on the same chip.

[Problem that the invention seeks to solve]

The drawbacks that occur in the data output stage configured as shown in FIG. 5 will be explained with reference to FIG. 7. When a dynamic MOS RAM is installed and used on a mounting board, it is inevitable that various noises from outside the chip will enter the input/output terminals.

Since the data output stage is a COMS inverter _, the clock φ ₁ applied to the gate of the load transistor _Q1 and the clock φ ₂ applied to the gate of the driver transistor Q ₂ are usually in phase with each other. Both _φ2 are “H”
Since the level is high, the output terminal _D0 becomes "L" level.
Further, at time _t2, when clocks _φ1 and _φ2 both go to the "L" level, the output terminal _D0 goes to the "H" level. However, at time _t3 , noise enters the output terminal _D0 from outside the chip, and the output terminal _D0
Suppose that the level of is equal to or higher than Vcc+VF (VF is the value at which the p-n junction becomes forward and current begins to flow, approximately 0.6 V). Since the N-well 2 is fixed to the power supply Vcc, when the level of _D0 becomes higher than Vcc+VF, the p-n junction formed by the p ⁺ diffusion region 4 and the N-well 2 becomes forward, and the holes ⁺ implanted from the diffusion region 4 into the N-well 2 (sixth
(see figure). Since the depth of the N-well 2 is on the order of several μm, the holes injected into the N-well 2 do not recombine with electrons within the N-well 2, and further enter the p-type semiconductor substrate 1. is injected up to. Then, the value of the negative voltage VBB generated on the chip is normally stable at around -3V, but due to the hole injection at time _t3 , the output impedance of the negative voltage generation circuit is high, so it drops from -3V to 0V. I'm trying to make a change in this direction. At time _t4 , when the noise is no longer mixed in, the hole injection is no longer present, and the negative voltage VBB attempts to return to -3V in a time determined by the output impedance of the negative voltage generation circuit. If the time τ during which noise is mixed in is long enough, the noise level is high, or if noise is mixed repeatedly, the value of the negative voltage VBB generated on the chip will eventually reach 0V. It had the disadvantage that it had a significant negative effect on the operation as a dynamic MOS RAM.

This invention has been made to solve the above-mentioned drawbacks, and provides a semiconductor memory having a data output stage that can prevent holes from being injected into a p-type semiconductor substrate even if noise of Vcc+VF or more is mixed into the output terminal. The purpose is to

[Means for solving problems]

The semiconductor memory according to the present invention has an N-channel MOS transistor for clamping connected to a data output stage consisting of a P-channel MOS transistor for loading and an N-channel MOS transistor for driver via a resistor.

[Effect]

In this invention, since a clamping transistor is provided in the data output stage, the output terminal has Vcc+
When noise of VF or higher enters, the transistor turns on and clamps the output terminal to Vcc + VTH (threshold voltage of the transistor), connecting the p ⁺ diffusion region and N
- It is possible to prevent the p-n junction formed from the well from going in the forward direction, and since the resistor is connected between the clamping N-channel MOS transistor and the data output stage, the clamping transistor can be clamped. The effect can be made stronger.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a basic circuit configuration diagram of a data output stage for explaining the principle of the present invention.
1 and Q2 are exactly the same as in FIG. Q3
is a clamping transistor, consisting of an N-channel MOS transistor, whose drain is connected to the power supply.
Connected to Vcc, source and gate are output terminal D ₀
and the board is connected to a negative voltage VBB. Here, it is assumed that the threshold voltage VTH of the clamping transistor Q3 is smaller than VF.

Next, the basic operating principle of the present invention will be explained.

In the data output stage configured as described above, when noise of Vcc+VF or more enters the output terminal _D0 , the clamping transistor Q3 turns on first and clamps the output terminal _D0 to the level of Vcc+VTH, so that p This prevents the pn junction (see FIG. 6) formed from the ⁺ diffusion region 4 and the N-well 2 from being in the forward direction.

FIG. 2 shows a circuit configuration of a data output stage according to an embodiment of the present invention. In the circuit of this embodiment, the connection point between the source of the load transistor Q1 and the drain of the driver transistor Q2 and the clamping transistor Q3 are connected to each other. A resistor R is inserted between them, and the other points are the same as the basic circuit configuration shown in FIG.

In this embodiment circuit, in addition to the basic clamping operation of the clamping transistor Q3 described above, noise is attenuated by the resistor R during clamping, making the clamping effect stronger.

In this way, in this embodiment, the data output stage is formed by serially connected load and driver transistors Q1 and Q.
2, and a clamping transistor Q3 is connected to the connection point between the two transistors, which becomes the output terminal, via a resistor R, so that the noise mixed in from the output terminal is clamped, attenuated, and applied to the p-type semiconductor substrate. The negative voltage applied to the substrate can be kept stable, and hole injection into the substrate can be effectively prevented.

In both of the above embodiments, a negative bias voltage is applied to the substrate of the clamping transistor Q3, but the substrate may be fixed to GND (0V). In this case, the threshold voltage of the transistor Q3 is
VTH becomes lower and noise absorption ability can be improved.

Furthermore, in both of the above embodiments, the dynamic MOS
Although the case of RAM has been described, it goes without saying that the present invention can also be applied to static MOS RAM, ROM, etc.

〔Effect of the invention〕

As described above, according to the semiconductor memory according to the present invention, a clamping transistor made of an N-channel MOS transistor is provided in the data output stage,
Furthermore, since a resistor is inserted between the data output stage and the clamping transistor, the noise introduced from the output terminal is clamped and attenuated to keep the negative voltage applied to the p-type semiconductor substrate stable. This has the effect of effectively preventing the injection of holes into.

[Brief explanation of drawings]

FIG. 1 is a basic circuit configuration diagram of a data output stage for explaining the principle of the present invention, FIG. 2 is a circuit diagram of a data output stage according to an embodiment of the present invention, and FIG.
The figure is a circuit diagram of the data output stage used in a general static MOS RAM, Figure 4 is a cross-sectional view of the structure of the data output stage in Figure 3, and Figure 5 is a data output stage used in a conventional dynamic MOS RAM. FIG. 6 is a structural sectional view of the data output stage of FIG. 5, and FIG. 7 is an explanatory diagram of the operation of the conventional circuit shown in FIG. 5. In the figure, Q1 is a load transistor consisting of a P-channel MOS transistor, Q2 is a driver transistor consisting of an N-channel MOS transistor, Q3 is a clamping transistor consisting of an N-channel MOS transistor, 1 is a p-type semiconductor substrate, 2 is an N-well, 4 is p ⁺ diffusion region, VBB
is a negative voltage of about -3V generated on the chip. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] 1. Having means for generating a negative voltage on the chip,
In the semiconductor memory in which the negative voltage is applied to the first conductivity type semiconductor substrate, a load transistor consisting of a first conductivity type MOS transistor, a driver transistor consisting of a second conductivity type MOS transistor, and a connection between the two transistors. A resistor having one end connected to a point, and a second conductivity type clamping MOS transistor having a drain connected to a power supply and a source and gate connected to the other end of the resistor. Features of semiconductor memory. 2. The semiconductor memory according to claim 1, wherein the threshold voltage of the clamping MOS transistor of the second conductivity type is smaller than the forward voltage of the pn junction. 3. The semiconductor memory according to claim 1, wherein the substrate of the clamping MOS transistor of the second conductivity type is fixed at 0V.