JPH04359556A - Method of manufacturing multi-chip-module - Google Patents
Method of manufacturing multi-chip-moduleInfo
- Publication number
- JPH04359556A JPH04359556A JP3134549A JP13454991A JPH04359556A JP H04359556 A JPH04359556 A JP H04359556A JP 3134549 A JP3134549 A JP 3134549A JP 13454991 A JP13454991 A JP 13454991A JP H04359556 A JPH04359556 A JP H04359556A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- wiring
- chip
- silicon oxide
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 7
- 238000000206 photolithography Methods 0.000 claims abstract description 6
- 230000008018 melting Effects 0.000 claims abstract description 3
- 238000002844 melting Methods 0.000 claims abstract description 3
- 229910052751 metal Inorganic materials 0.000 claims abstract description 3
- 239000002184 metal Substances 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 2
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims description 2
- 239000000919 ceramic Substances 0.000 abstract description 7
- 238000010884 ion-beam technique Methods 0.000 abstract description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- OAKJQQAXSVQMHS-UHFFFAOYSA-N Hydrazine Chemical compound NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 description 2
- 229910015367 Au—Sb Inorganic materials 0.000 description 1
- PIICEJLVQHRZGT-UHFFFAOYSA-N Ethylenediamine Chemical compound NCCN PIICEJLVQHRZGT-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明はマルチ・チップ・モジュ
ールの方法に関し、特に複数個の集積回路チップをセラ
ミック基板上に実装するマルチ・チップ・モジュールの
製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multi-chip module, and more particularly to a method for manufacturing a multi-chip module in which a plurality of integrated circuit chips are mounted on a ceramic substrate.
【０００２】0002
【従来の技術】従来のマルチ・チップ・モジュールの製
造方法は、図２に示す様にセラミック基板１上に配線パ
ターン２ａをフォトリソグラフィー技術により形成し集
積回路チップ３，４の表面を下にして、所謂フリップ・
チップ・ボンディング技術により実装していた。集積回
路チップ３ａ，４ａには接続部に半田ボール５を形成し
てからベルト炉中で加熱してセラミック基板１に接着し
ている。2. Description of the Related Art As shown in FIG. 2, a conventional method for manufacturing a multi-chip module involves forming a wiring pattern 2a on a ceramic substrate 1 by photolithography, with the surfaces of integrated circuit chips 3 and 4 facing downward. , the so-called flip
It was mounted using chip bonding technology. The integrated circuit chips 3a, 4a are bonded to the ceramic substrate 1 by being heated in a belt furnace after forming solder balls 5 at the connecting portions.
【０００３】0003
【発明が解決しようとする課題】この従来のマルチ・チ
ップ・モジュールの製造方法では、表面を下にして半田
ボール部でセラミック基板と接着しているので、接着面
積が小さく放熱効率が悪いという問題点があった。従っ
て、消費電力の大きな集積回路チップの実装が出来なか
った。[Problems to be Solved by the Invention] In this conventional multi-chip module manufacturing method, the surface is bonded to the ceramic substrate at the solder ball portion, so the problem is that the bonding area is small and heat dissipation efficiency is poor. There was a point. Therefore, it was not possible to mount an integrated circuit chip with large power consumption.
【０００４】0004
【課題を解決するための手段】本発明のマルチ・チップ
・モジュールの製造方法は、集積回路基板を異方性エッ
チングにより集積回路チップに分離する工程と、複数個
の前記集積回路チップを絶縁性台座基板上に接着する工
程と、化学気相成長法によりシリコン酸化膜を堆積する
工程と、フォトリソグラフィー技術により前記シリコン
酸化膜の配線接続部にコンタクト孔を開孔する工程と、
高融点金属を前記シリコン酸化膜の表面の一部に直接描
画により配線形成する工程とを含んで構成されている。[Means for Solving the Problems] A method for manufacturing a multi-chip module according to the present invention includes the steps of separating an integrated circuit board into integrated circuit chips by anisotropic etching, and separating a plurality of the integrated circuit chips with an insulating material. a step of adhering onto a pedestal substrate, a step of depositing a silicon oxide film by chemical vapor deposition, and a step of opening a contact hole in the wiring connection part of the silicon oxide film by photolithography technology;
The method includes a step of forming wiring with a high melting point metal on a part of the surface of the silicon oxide film by direct drawing.
【０００５】[0005]
【実施例】次に本発明について図面を参照して説明する
。図１は本発明の一実施例を説明するためのマルチ・チ
ップ・モジュールの断面図である。まず、プロセスを終
了した集積回路基板のスクライブ領域を結晶面方位に対
して異方性のあるエッチング液、例えばヒドラジン，Ｋ
ＯＨ，エチレン・ジアミンによりエッチングしてチップ
分離すると、断面が５４．７４°の角度を成す台形状の
集積回路チップ３，４が得られる。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 is a sectional view of a multi-chip module for explaining one embodiment of the present invention. First, the scribe area of the integrated circuit board that has completed the process is etched with an etching solution that is anisotropic with respect to the crystal plane orientation, such as hydrazine or K.
When chips are separated by etching with OH and ethylene diamine, trapezoidal integrated circuit chips 3 and 4 having cross sections forming an angle of 54.74° are obtained.
【０００６】次にセラミック基板１に異方性エッチング
により分離した集積回路チップ３及び４をＡｕ−Ｓｂ等
の合金により接着する。Next, the integrated circuit chips 3 and 4 separated by anisotropic etching are bonded to the ceramic substrate 1 using an alloy such as Au-Sb.
【０００７】次に化学気相成長法により常圧でシリコン
酸化膜ｂを全面に約５０μｍの厚さに堆積する。Next, a silicon oxide film b is deposited to a thickness of about 50 μm over the entire surface at normal pressure by chemical vapor deposition.
【０００８】続いて配線接続する部分のシリコン酸化膜
をフォトリソグラフィー技術によりエッチングしコンタ
クト孔を開孔する。Subsequently, the silicon oxide film at the portion to be connected to the wiring is etched by photolithography to form a contact hole.
【０００９】次に集積回路チップ間の配線を形成する為
にレーザビームやイオンビームを用いて配線パターン２
を直接描画する。Next, in order to form wiring between integrated circuit chips, a wiring pattern 2 is formed using a laser beam or an ion beam.
Draw directly.
【００１０】例えばレーザビームを用いる場合はＷ（Ｃ
Ｏ）６ガスを表面に吸着させた後、レーザビームを照射
すると照射した部分のみにタングステンＷ配線層が形成
される。For example, when using a laser beam, W(C
After adsorbing O)6 gas on the surface, a laser beam is irradiated to form a tungsten W wiring layer only in the irradiated area.
【００１１】配線を形成する領域にイオンビームを走査
して行けばマスクを使わずに配線が形成される。Wiring can be formed without using a mask by scanning an ion beam over a region where wiring is to be formed.
【００１２】ＹＡＧレーザを用いた場合は、０．１μｍ
／ｓの描画速度で１０〜２０μΩ／ｃｍのＷ配線が形成
される。[0012] When using a YAG laser, 0.1 μm
W wiring with a thickness of 10 to 20 μΩ/cm is formed at a drawing speed of /s.
【００１３】最後にカバー酸化膜を化学気相成長法によ
り１００μｍの厚さに形成する（図示せず）。Finally, a cover oxide film is formed to a thickness of 100 μm by chemical vapor deposition (not shown).
【００１４】本実施例では２チップの実装例を示したが
３チップ以上でも適用できる。In this embodiment, an example of mounting two chips is shown, but the present invention can also be applied to mounting three or more chips.
【００１５】[0015]
【発明の効果】以上説明したように本発明は、集積回路
チップの接着面積が大きく放熱量が大きいので消費電力
の大きい集積回路チップでも実装できるという効果を有
する。As described above, the present invention has the advantage that even integrated circuit chips with high power consumption can be mounted because the bonding area of the integrated circuit chip is large and the amount of heat dissipated is large.
【００１６】また異方性エッチングにより断面を台形状
としているので配線描画する場合に傾斜部にもビームが
照射され配線が形成される。従来のダイシングによるチ
ップ分離では断面が垂直となり、配線が形成されないの
に更に直接描画により配線形成すれば従来のフォトリソ
グラフィーでは焦点深度が浅く、段差のある部分にパタ
ーン形成できなかったが、マスクが不要で段差のある所
でも配線形成できる。Further, since the cross section is made into a trapezoidal shape by anisotropic etching, when wiring is drawn, the beam is irradiated even on the sloped part, and the wiring is formed. When separating chips using conventional dicing, the cross section is vertical and no wiring is formed.However, if wiring is formed by direct writing, conventional photolithography has a shallow depth of focus and cannot form patterns in stepped areas. Wiring can be formed even in areas where there are unnecessary steps.
【図１】本発明の一実施例を説明するためのマルチ・チ
ップ・モジュールの断面図である。FIG. 1 is a cross-sectional view of a multi-chip module for explaining one embodiment of the present invention.
【図２】従来のマルチ・チップ・モジュールの一例の断
面図である。FIG. 2 is a cross-sectional view of an example of a conventional multi-chip module.
１ セラミック基板 ２ 配線パターン ３ 集積回路チップ ４ 集積回路チップ ５ 半田ボール ６ シリコン酸化膜 1 Ceramic substrate 2 Wiring pattern 3 Integrated circuit chip 4 Integrated circuit chip 5 Solder ball 6 Silicon oxide film
Claims (1)
り集積回路チップに分離する工程と、複数個の前記集積
回路チップを絶縁性台座基板上に接着する工程と、化学
気相成長法によりシリコン酸化膜を堆積する工程と、フ
ォトリソグラフィー技術により前記シリコン酸化膜の配
線接続部にコンタクト孔を開孔する工程と、高融点金属
を前記シリコン酸化膜の表面の一部に直接描画により配
線形成する工程とを含むことを特徴とするマルチ・チッ
プ・モジュールの製造方法。1. A step of separating an integrated circuit board into integrated circuit chips by anisotropic etching, a step of bonding a plurality of the integrated circuit chips onto an insulating pedestal substrate, and a step of separating silicon oxide by chemical vapor deposition. A step of depositing a film, a step of forming a contact hole in the wiring connection portion of the silicon oxide film using photolithography technology, and a step of forming a wiring by directly drawing a high melting point metal on a part of the surface of the silicon oxide film. A method for manufacturing a multi-chip module, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3134549A JPH04359556A (en) | 1991-06-06 | 1991-06-06 | Method of manufacturing multi-chip-module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3134549A JPH04359556A (en) | 1991-06-06 | 1991-06-06 | Method of manufacturing multi-chip-module |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04359556A true JPH04359556A (en) | 1992-12-11 |
Family
ID=15130915
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3134549A Pending JPH04359556A (en) | 1991-06-06 | 1991-06-06 | Method of manufacturing multi-chip-module |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04359556A (en) |
-
1991
- 1991-06-06 JP JP3134549A patent/JPH04359556A/en active Pending
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19991026 |