JPH04358471A - Scanning light beam synchronization controller - Google Patents

Abstract

PURPOSE:To simplify the circuit configuration and to improve the reliability by providing a pulse generating circuit generating one timing clock pulse every time a prescribed number of delay outputs is generated after a synchronizing signal is generated. CONSTITUTION:When a synchronizing signal S is generated and a Q output (e) of a flip-flop FF5 rises, an output e' of an inverter 30 falls down and a reset state of FF1-FF4 is released. Delay outputs c4, c1, c2 appearing just after the reset set relevant FFs 4,1,2. When Q outputs of the FF1-FF4 all rise, an output of an AND gate A3 goes to 1 and a timing clock pulse T is generated. The pulse T resets the FF1-FF4 and releases them again just after resetting. The leading of the pulse T is caused after lapse of t-5t/4 after the signal S, and the final pulse T is a pulse train whose period is (t). When a counter 25 counts 3000 pulses T, the counter outputs a level 1 to reset the FF1-5 and the state is latched till a succeeding signal S comes.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] This invention relates to a scanning light beam synchronization control device that synchronously controls the timing when a scanning light beam scans an object to be scanned, and in particular, achieves cost reduction by simplifying the circuit configuration. The present invention relates to a scanning light beam synchronization control device with improved reliability.

0002

2. Description of the Related Art Conventionally, image recording, processing, or , devices for reading information, etc. are well known.

In this type of apparatus, timing clock pulses are used to set positions corresponding to a plurality of dots included in one scanning line. Further, the timing clock pulse must always be accurately synchronized with the scan start position of the object to be scanned for each scan. Therefore, a scanning light beam synchronization control device is used to always match the generation start timing of the timing clock pulse with respect to the object to be scanned, thereby minimizing the error in dot position for each scan.

FIG. 3 is a schematic diagram of a general laser printer described in, for example, Japanese Patent Publication No. 62-26221. In the figure, 11 is a laser light source that emits a scanning light beam B made of laser light, 12 is an optical modulator that modulates the scanning light beam B according to an optical modulation signal W', and 1
3 is a magnifying lens disposed in the optical path of the modulated scanning light beam B; 14 is a rotating polygon mirror rotated by a motor 14'; 15 is a scanning light beam Bs reflected by the rotating polygon mirror 14;
An imaging lens 16 is arranged in the optical path of the imaging lens 1.
An object to be scanned, that is, a recording medium, is irradiated with the scanning light beam Bs via 5, and 17 is a photodetector disposed at a position before the start of scanning of the recording medium 16, and generates a synchronization signal S when the scanning light beam Bs is irradiated. 18 is an optical modulator control circuit that generates an optical modulation signal W' based on the synchronization signal S and print information W.

Next, the operation of the general laser printer shown in FIG. 3 will be explained. The scanning light beam B emitted from the laser light source 11 is transmitted to the optical modulator 12 and the magnifying lens 1.
The scanning light beam Bs reaches the rotating polygon mirror 14 through the imaging lens 1 and is reflected by the rotating polygon mirror 14.
5 to the recording medium 16.

At this time, the rotating polygon mirror 14 is moved by the motor 14'.
Since the scanning light beam Bs reflected by each mirror surface on the rotating polygon mirror 14 is scanned along the recording medium 16 in the direction of the arrow X, the scanning light beam Bs reflected by the next mirror surface flies back to the starting point of arrow X again. Note that the recording medium 16 is rotated and fed by a predetermined pitch in the direction of arrow Y for each scan.

On the other hand, the optical modulator 12 uses the optical modulation signal W' corresponding to the print information W from the optical modulator control circuit 18 to
The scanning light beam B is intermittently blocked or transmitted, thereby forming a printed dot pattern on the recording medium 16. The optical modulator control circuit 18 also includes a reference oscillator (
(to be described later), and outputs print information W synchronized with the timing clock pulse to the optical modulator 12 as an optical modulation signal W'.

At this time, the photodetector 17 is placed on the extension of the arrow
is fixed, and the first dot position is defined after a certain period of time (after counting certain timing clock pulses) from the time when the scanning light beam Bs passes through the photodetector 17.

That is, in order to use the synchronization signal S from the photodetector 17 as the timing to start generating the timing clock pulse, the first rising edge of the timing clock pulse is generated as soon as possible after the synchronization signal S is generated. It should be done as follows. Ideally, the first rising timings of the synchronizing signal S and the timing clock pulse should almost match.

FIG. 4 is a circuit block diagram showing a conventional scanning light beam synchronization control device described in the above-mentioned publication, which is included in the optical modulator control circuit 18 in FIG. In the figure, 21 is a reference oscillator that generates an oscillation output a with a constant period, 22 is a waveform shaping circuit that generates a waveform shaping oscillation output b,
23 is a delayed output generation circuit that generates a plurality of delayed outputs c1 to c4 by delaying the waveform-shaped oscillation output b by a predetermined amount;
4 is a delay output selection circuit that selects one of the delay outputs c1 to c4.

In this case, the four delayed outputs c1 to c4 are:
The timing is set by dividing the constant period t of the oscillation output a into equal intervals. Further, the delayed output selection circuit 24 is activated in response to the synchronization signal S, and selects the delayed outputs c1 to c4.
Based on this, a pulse generation circuit is configured to generate timing clock pulses T of the number of pulses corresponding to one scan of the scanning light beam Bs.

FF1 to FF5 are D-type flip-flops (hereinafter simply referred to as flip-flops) in which logic "1" is input to each D terminal.
A signal corresponding to each of the delayed outputs c1 to c4 is input to the C terminal of F4, and a synchronization signal S is input to the C terminal of flip-flop FF5.

A1-1 to A1-4 are the respective delay outputs c1 to c
4 and the Q output e of the flip-flop FF5, and each output f1 to f4 is input to the C terminal of the flip-flop FF1 to FF4. OR1 is each output f of AND gates A1-1 to A1-4
This is an OR gate that calculates the logical sum of 1 to f4, and its output is input to the CLR (clear) terminal of flip-flop FF5.

A2-1 to A2-4 are flip-flops F
Each Q output g1 to g4 of F1 to FF4 and each delay output c1 to
An AND gate OR2 that individually performs a logical product with c4 is an OR gate that performs a logical sum of the outputs of the AND gates A2-1 to A2-4 and outputs a timing clock pulse T. A counter 25 counts timing clock pulses corresponding to one scan of the scanning light beam Bs, and its output is input to each CLR terminal of the flip-flops FF1 to FF4.

FIG. 5 is a block diagram showing a configuration example of the delayed output generation circuit 23 in FIG. 4, and 26 to 28 are a t/4 delay circuit, a t/2 delay circuit, and a 3t/4 delay circuit, respectively. be. However, t is the oscillation output a and the waveform shaping oscillation output b
The period is The delay circuits 26 to 28 commonly receive the waveform-shaped oscillation output b, and the undelayed waveform-shaped oscillation output b is the delayed output c1, and the output of the t/4 delay circuit 26 is the delayed output c2, t/4.
The output of the 2-delay circuit 27 is a delay output c3, and the output of the 3t/4 delay circuit 28 is a delay output c4.

In this manner, the delayed output generation circuit 23 provides four delayed outputs c1 to c4 by giving a delay of, for example, t/4 to the pulse period t of the waveform-shaped oscillation output b based on the oscillation output a. generate. Then, the delay output selection circuit 2
4 selects one delayed output having the minimum phase shift with the synchronizing signal S from among the delayed outputs c1 to c4, and sets this as the timing clock pulse T.

Therefore, the optical modulator control circuit 18 shown in FIG. 3 generates an optical modulation signal W' containing print information W and supplies it to the optical modulator 12 at the timing specified by the timing clock pulse T. do. As a result, a printed dot pattern with extremely small dot misalignment (less than a fraction of a dot) is secured on the recording medium 16.

Next, the operation of the conventional scanning light beam synchronization control device shown in FIG. 4 will be specifically explained with reference to the timing chart of FIG. FIG. 6 shows each output signal a, b, c1 to c4, S, e, f3, g3 and T in FIG.
shows the pulse waveform and timing of .

First, the oscillation output a of a constant frequency sent out from the reference oscillator 21 has its pulse width narrowed by the waveform shaping circuit 22 to become a waveform shaped oscillation output b, which is input to the delayed output generation circuit 23. The delayed output generation circuit 23 individually sends out delayed outputs c1 to c4 whose phases are shifted by t/4 with respect to the period t of the oscillation output a from four output terminals. This is to reduce the dot position deviation to a fraction of a dot or less, ie, to 1/4 of the period t of the timing clock pulse T, as described above.

Now, if the synchronization signal S is output from the photodetector 17 at the timing shown by the solid line in FIG.
is set and logic "1" is applied to the D terminal, so its Q output e rises. As a result, AND gates A1-1 to A1-4 are opened simultaneously, and the delayed output c1
~c4 are respective AND gates A1-1 to A1-
4 can be passed.

On the other hand, each AND gate A1-1 to A1-4
The output of AND gate A is input to the CLR terminal of flip-flop FF5 via OR gate OR1.
The flip-flop FF5 is reset by the delayed outputs c1 to c4 that first pass through any one of A1-1 to A1-4, and its Q output e falls. In this case, as is clear from FIG. 6, the delayed output that first appears after the synchronizing signal S rises is c3, and the Q output e of the flip-flop FF5 falls due to the delayed output c3.

[0022] As a result, AND gates A1-1 to A1
-4 are all closed at the same time, and the subsequent delayed outputs c1 to c4
is not applied to the C terminals of flip-flops FF1 to FF4. Therefore, as mentioned above, the AND gate A
The only delayed output c3 that passed through 1-3 first is input to the C terminal of flip-flop FF3, and only flip-flop FF3 is set, and the other flip-flop FF1
, FF2 and FF4 remain reset. and,
The Q output g3 of the flip-flop FF3 rises and does not fall thereafter until it is reset.

As a result, flip-flops FF1 to FF
AND gate A2 to which each Q output g1 to g4 of 4 is input.
A2-3 of -1 to A2-4 is opened, and only the delayed output c3 input to the AND gate A2-3 is allowed to pass through. Therefore, the delayed output c3 that has passed through the AND gate A2-3 becomes the desired timing clock pulse T via the OR gate OR2. As is clear from FIG. 6, this timing clock pulse T is obtained with a response of t/4 or less after the appearance of the synchronization signal S, and the timing clock pulse T is obtained with a response of t/4 or less after the synchronization signal S appears, and the position of the first dot of the printed dot pattern is shifted by a fraction of a dot or less. Can be set within.

After that, the timing clock pulse T is
Since printing information W for one scanning line is converted into a light modulation signal W' corresponding to a dot pattern, a predetermined number (for example, 3000
After outputting a pulse train of 1), the pulse train for the next scanning line is started. Among the 3000 pulses, for example, the first several hundred pulses correspond to the distance from the photodetector 17 to the leading end of the recording medium 16.

At this time, the counter 25 counts the timing clock pulses T, and when 3000 pulses have been counted, simultaneously resets the flip-flops FF1 to FF4 to return to the initial state, and similarly applies to the next scanning line. Repeat the operation. The timing at which the next synchronization signal S appears is random; for example, if it appears at the timing indicated by the dotted line in FIG. 6, the delayed output c2 that first appears within t/4 becomes the timing clock pulse T. .

[0026]

[Problems to be Solved by the Invention] As described above, in the conventional scanning light beam synchronization control device, the delayed output selection circuit 24 selects the delayed output that appears within t/4 after the synchronization signal S is generated by using the timing clock pulse. Since the delay output selection circuit 24 is selected as T, the configuration of the delayed output selection circuit 24 becomes complicated, the number of pattern wiring and gates on the circuit board increases, and it is easily affected by noise.Furthermore, there are problems in that cost reduction cannot be realized. Ta.

The present invention has been made to solve the above-mentioned problems, and aims to provide a scanning light beam synchronization control device that simplifies the circuit configuration, reduces costs, and improves reliability. purpose.

[0028]

[Means for Solving the Problems] A scanning light beam synchronization control device according to the present invention provides one timing clock pulse every time a predetermined number of delayed outputs are generated after a synchronization signal is generated.
It is equipped with a pulse generation circuit that generates pulses.

[0029]

[Operation] In this invention, even if the timing clock pulse is not generated at an early point after the synchronization signal is generated, it is functionally sufficient as long as the dot position shift at the starting point of each scanning line is small. By generating one timing clock pulse every time a predetermined number of delayed outputs are generated, a circuit for selecting delayed outputs is not required.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention, in which 21-23, 25, FF1-FF5, a, b, c1
~c4, e, g1~g4, S and T are the same as described above. Further, an apparatus to which the scanning light beam synchronization control device of FIG. 1 is applied is, for example, a laser printer shown in FIG. 3.

A3 is a timing clock pulse T obtained by ANDing each Q output of flip-flops FF1 to FF4.
30 is a flip-flop FF
This is an inverter that inverts the Q output e of No. 5. OR3 is an OR gate that takes the logical sum of the output e' of the inverter 30, the output of the counter 25, and the timing clock pulse T, and its output h is applied to each CLR terminal of the flip-flops FF1 to FF4.

The flip-flops FF1 to FF4, the AND gate A3, the OR gate OR3, and the counter 25 are activated in response to the synchronization signal S, and the delayed outputs c1 to c
4, a pulse generation circuit 31 that generates a timing clock pulse T corresponding to one scan is configured, and the timing clock pulse T is generated every time M delay outputs c1 to c4 are generated after the synchronization signal S is generated. Generate 1 pulse.

Next, the operation of the embodiment of the present invention shown in FIG. 1 will be explained with reference to the timing chart of FIG. When the synchronization signal S is not generated in the initial state, the Q output e of the flip-flop FF5 is logic "0", so the output e' of the inverter 30 is logic "0".
1'', which passes through the OR gate OR3 and is applied to each CLR terminal of the flip-flops FF1 to FF4. Therefore, flip-flops FF1-FF4 are in a reset state, each Q output g1-g4 is logic "1", and no timing clock pulse T is generated.

Now, the synchronizing signal S is generated at the timing shown by the solid line in FIG. 2, and the Q output e of the flip-flop FF5 is
When e' rises, the output e' of inverter 30 falls, and the reset states of flip-flops FF1 to FF4 are released. Thereafter, each flip-flop FF1 to FF4 is reset each time the output h of the OR gate OR3 appears.

First, the delayed output c3 that appears immediately after the reset of the flip-flops FF1 to FF4 is released sets the flip-flop FF3 and raises its Q output g3. Below, delayed outputs c4, c1, and c appear sequentially.
2 are flip-flops FF4 and FF1 corresponding to each
and FF2, and its Q outputs g4, g1 and g2
launch. In this way, flip-flops FF1 to F
When all the Q outputs of F4 rise, the output of AND gate A3 becomes logic "1", and the timing clock pulse T
Generates only one pulse.

On the other hand, the timing clock pulse T passes through the OR gate OR3 and becomes the output h, which resets the flip-flops FF1 to FF4 and causes the Q outputs g1 to g4 to fall at the same time. As a result, the timing clock pulse T falls immediately after rising, causing the flip-flops FF1 to FF4 to be reset again. Thereafter, the same operation is repeated, and one timing clock pulse T is generated every time all of the Q outputs g1 to g4 rise (that is, every time four delayed outputs are generated in this case).

At this time, the first rise of the timing clock pulse T occurs after a time corresponding to t~5t/4 has elapsed since the synchronization signal S was generated.
Further, the subsequent rises of the timing clock pulses T occur after a period of time corresponding to t has elapsed, and the timing clock pulse T finally obtained has a constant period t.
This becomes a pulse train.

As described above, when the counter 25 counts 3000 timing clock pulses T corresponding to one scanning line, the counter 25 sets the output to logic "1", raises the output h of the OR gate OR3, and outputs the output from the flip-flop FF1. ~
All FF4 are reset, and at the same time, flip-flop FF5 is reset. As a result, the inverter 30
The output e' rises and the flip-flops FF1 to F
The reset state of F4 is maintained until the next synchronization signal S is generated.

Then, at the time when the next synchronizing signal S is generated, a predetermined number of timing clock pulses T are generated again. At this time, for example, if the synchronization signal S is generated at the timing shown by the dotted line in FIG. 2, the first delayed output that appears is c2, but the first timing clock pulse T
is generated at a period of t after t~5t/4 has elapsed since the generation of the synchronization signal S, and no large deviation occurs in the printed dot positions.

Therefore, by using the pulse generating circuit 31 having a simple configuration with a small number of gates, it is possible to reduce the print dot position deviation to a fraction of a dot or less, as in the conventional case. As a result, cost reduction is achieved, and reliability is also improved since it is less susceptible to noise.

In the above embodiment, the scanning light beam B is applied to a laser printer, but any device using a scanning light beam may be applied to a processing device, an information reading device, etc. . Further, although the case where four delayed outputs c1 to c4 are used has been shown, by changing the number of flip-flops in the pulse generation circuit 31, any number of delayed outputs can be used.

Furthermore, the AND gate A3 outputs the delayed output c1
All flip-flops FF1 to FF compatible with ~c4
Although we have shown the case where the logical product of the Q outputs g1 to g4 of 4 is taken,
One timing clock pulse T may be generated each time an arbitrary predetermined number of delay signals different from the number of types of delay outputs are generated.

[0043]

As described above, according to the present invention, since a pulse generation circuit is provided that generates one timing clock pulse every time a predetermined number of delayed outputs are generated after generation of a synchronization signal, delayed output This eliminates the need for a circuit for selecting a scanning light beam, which simplifies the circuit configuration, reduces costs, and provides a scanning light beam synchronization control device with improved reliability.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a timing chart showing waveforms of each output signal in FIG. 1;

FIG. 3 is a configuration diagram showing a general laser printer.

FIG. 4 is a block diagram showing a conventional scanning light beam synchronization control device.

FIG. 5 is a block diagram showing a configuration example of the delayed output generation circuit in FIG. 4;

6 is a timing chart showing waveforms of each output signal in FIG. 4. FIG.

[Explanation of symbols]

16 Recording medium (object to be scanned) 17 Photodetector 21 Reference oscillator 23 Delayed output generation circuit 25 Counter 31 Pulse generation circuit A3 AND gates FF1 to FF5 Flip-flop OR3
OR gate Bs Scanning light beam S Synchronizing signal T Timing clock pulse a Oscillation output c1 to c4 Delay output t Constant period

Claims (1)

[Claims] 1. A photodetector disposed at a position before the start of scanning of an object to be scanned and generating a synchronizing signal when irradiated with a scanning light beam; a reference oscillator generating an oscillation output with a constant period; and a reference oscillator generating an oscillation output with a constant period. a delayed output generation circuit that generates a plurality of delayed outputs delayed by a predetermined amount in order to obtain timing divided at equal intervals; and a delayed output generation circuit that is activated in response to the synchronization signal and based on the delayed outputs. a scanning light beam synchronization control device comprising: a pulse generation circuit that generates timing clock pulses of a number corresponding to one scan for each scan, wherein the pulse generation circuit generates the delayed output after generating the synchronization signal; A scanning light beam synchronization control device, characterized in that one pulse of the timing clock pulse is generated every time a predetermined number of timing clock pulses are generated.