JPH04354282A - Afc circuit - Google Patents

Abstract

PURPOSE:To provide an AFC circuit which resolves the erroneous operation of a frequency error detection circuit occurring from noise when a CN ratio is dropped and maintains the excellent modulation characteristics of a phase modulator, in a sound PCM broadcasting receiver for satelite broadcasting. CONSTITUTION:This circuit is provided with a control means 22 consisting of a frequency conversion circuit 4 converting the frequency of an input signal, a band pass filter 5 selecting a desired signal, a phase modulator 6, a synchronization detection circuit 33 detecting the synchronizing state of the phase modulator 6, a frequency error detection circuit 23 inputting a carriage signal reproduced in the phase modulator 6 and detecting the deviation of the frequency and a microcomputer inputting the output signal of the frequency error detection circuit 23 and the output signal of the synchronization detection circuit 33 and controlling the oscillation frequency of a local oscillator 20, and when the synchronization detection is not obtained, a second intermediate frequency is swept, and when the synchronization detection is obtained, normal AFC retraction control is performed.

Description

[Detailed description of the invention]

0001

[Industrial Field of Application] The present invention is directed to the voice P by a communication satellite.
This relates to the AFC circuit of a CM broadcast receiver.

0002

2. Description of the Related Art In recent years, services using communication satellites (CS) have been expanding, and audio PCM broadcasting services using CS are about to start. This system occupies the band (27MHz) of one transponder, which is normally used to transmit television signals including video and audio for one channel, and provides high-quality PCM audio equivalent to that of satellite broadcasting (BS). 6 channels are digitally multiplexed and transmitted. In this system, it is planned to take into account the input/output nonlinear characteristics of the transponder of a communication satellite and transmit the digitally multiplexed PCM audio signal after MSK modulation. Audio PCM to receive this
The broadcasting receiver is constructed from a block diagram as shown in FIG. 2. (Reference: "Multi-channel PCM audio satellite broadcasting" NHK Giken R&D, published February 15, 1990, by Kameda and Kawai) In (Fig. 2), 1 is the IF input terminal of the audio PCM broadcast receiver. This terminal 1 receives the signal from the satellite received by the antenna.
A 2 GHz band radio wave is frequency-converted to a 1 GHz band by a down converter, and a first intermediate frequency signal guided indoors via a coaxial cable is applied. 2 is a first intermediate frequency amplification circuit;
3 is an image filter, 4 is a frequency converter, 20 is a local oscillator, 21 is a PLL frequency control circuit, 22 is a microcomputer circuit that performs AFC control, 23 is a frequency error detection circuit, 5 is a band pass filter, and 6 is a MSK demodulator, 7 is a high-order multiplex decoder, 8 is an audio signal processing circuit, 9, 1
0 is an audio output terminal, 33 is a synchronization detection circuit, 34 is a squaring circuit, 36 is a multiplication circuit, 37 is a low-pass filter circuit, 3
8 is a comparator, 39 is a reference voltage, and 35 is a frequency dividing circuit.

The operation of the audio PCM broadcast receiver configured as described above will be explained below. The first intermediate frequency amplification circuit 2, image filter 3, frequency converter 4, local oscillator 20, and PLL frequency control circuit 21 constitute a channel selection circuit. 1GHz by tuning circuit
The band MSK signal is converted to a second intermediate frequency. At this time, the first intermediate frequency amplification circuit 2 is a low NF wideband amplifier so that the NF at the subsequent stage does not affect the input terminal. The image filter 3 is a filter for preventing image disturbance from occurring, and is for removing an image frequency component that is the sum of twice the first intermediate frequency and the second intermediate frequency. Frequency converter 4, local oscillator 20, PLL
The frequency control circuit 21 constitutes a frequency conversion circuit with high frequency accuracy using a frequency synthesizer method. When the image filter 3 selects the second intermediate frequency in the 140 MHz band, in order for the image frequency to fall within the band of the first intermediate frequency, it is necessary to change the image frequency to follow the first intermediate frequency signal to be tuned. be. This is called frequency tracking of the image filter, and it is important that these frequencies match accurately and that the frequency characteristics do not change.

The bandpass filter 5 is a filter for extracting only the MSK signal and removing noise and signals of other channels, and generally a Gaussian characteristic filter with excellent phase group delay characteristics is employed. This filter plays an important role in determining the demodulation characteristics of the receiver, and a surface acoustic wave band pass filter (SAW BPF) is suitable in consideration of the stability of frequency characteristics and phase group delay characteristics. As shown in FIG. 3, the spectrum of the MSK modulated wave spreads over a wide band, and the spectrum near the center frequency is nearly flat.

[0005] The MSK demodulator 6 has mutually orthogonal I and Q signals.
It plays the role of extracting the baseband signal. The demodulation stage of MSK demodulation divides the reproduced carrier signal into two components, in-phase and quadrature, and synchronously detects the input signal using each component. Signal distribution and synchronous detection are performed at the second intermediate frequency. The 140 MHz band is suitable as the frequency in consideration of the phase stability of the signal splitter, etc.

[0006] The high-order multiplex decoder 7 inputs the baseband signal and separates the MSK demodulated digitally multiplexed audio signal for six channels into respective channels, and also uses digital processing to prevent deterioration of the transmission system. It functions to correct bit errors that occur. Audio signal processing circuit 8
inputs the separated digital signal for one channel and performs interleaving, which is PCM decoding processing, and processing of range bits and control signals. The D/A converter converts the digital signal into an analog signal, and outputs the audio baseband signal (R, L) to the output terminal 9 via the LPF.
, 10.

The frequency error detection circuit 23 is a detection circuit for ensuring that the second intermediate frequency becomes a predetermined frequency. The demodulation characteristics of the MSK demodulator 6 are significantly degraded by frequency shifts. Therefore, the frequency deviation of the second intermediate frequency is ±1
It is necessary to keep the frequency below 00kHz. Therefore, the frequency step of the frequency synthesizer consisting of the frequency converter 4, local oscillator 20, and PLL frequency control circuit 21 is 30.
It should be set to about kHz. As shown in FIG. 4, the frequency error detection circuit 23 includes a first frequency divider 50, a second frequency divider 52, a reference crystal oscillator 51, a phase detector 53, a low-pass filter circuit 54, and a Schmitt trigger circuit 55. Become. The first frequency divider 50 and the second frequency divider 52 are so-called programmable counters whose frequency division ratios can be set by the microcomputer 22. At ±20kHz of the input second intermediate frequency, the phase detector 53
the first frequency divider 50 to match the frequency input to the
and the frequency division ratio of the second frequency divider 52 are set by the microcomputer 22. In this way, at each of those frequencies, the output signal of each individual Schmitt trigger circuit 55 is inverted. Note that the low-pass filter circuit 54 plays a role of smoothing harmonic components of the phase detector 53. The frequency error detection circuit 23 provides an output signal to the microcomputer 22 when the second intermediate frequency deviates from its center frequency by approximately ±20 kHz. Using this signal, the microcomputer 22 controls the frequency synthesizer circuit to set the second intermediate frequency to a predetermined frequency.

On the other hand, the PLL constituting the MSK demodulator 6 has a capture range of at most ±100 kHz in order to improve phase noise characteristics. For this purpose, due to the frequency drift of the voltage controlled oscillator of the carrier wave regeneration circuit,
Carrier waves may not be synchronized during AFC pull-in. In order to restore normal synchronization from such a state, the MSK demodulator 6 is normally equipped with a synchronization detection circuit 3 as shown in FIG.
3 is added. As shown in FIG. 4, the synchronization detection circuit 33 divides and squares the clock signal 32 output from the MSK demodulator 6 and the I signal or Q signal 31 of the output data signal by two, and then performs phase detection using a multiplier 36. , only the DC component is extracted by the low-pass filter 37, and the reference voltage 39
The clock signal 32 is compared with the clock signal 32 by a comparator 38.
By detecting the synchronization state between the output data signal 31 and the output data signal 31, a synchronization detection signal 40 is obtained. Microcomputer 2
2 inputs the synchronization detection signal 40, and when the MSK demodulator 6 is not synchronized, sweeps the second intermediate frequency. This makes it possible to avoid an asynchronous state at the time of AFC pull-in.

[0009]

[Problem to be solved by the invention] As mentioned above, the voice P
CM broadcast receivers employ a phase modulation method, and the spectrum of the modulated wave is spread over a wide band. Furthermore, the spectrum near the center frequency is nearly flat. Therefore, the output of the bandpass filter 5 is used to
If the frequency deviation of the intermediate frequency is detected using a programmable counter as in the past, the frequency error detection circuit 23 malfunctions due to noise when the CN ratio decreases, and the detected frequency changes as shown in FIG. Along with that, the second
There was a problem in that the intermediate frequency shifted significantly and the demodulation characteristics of the MSK demodulator 6 deteriorated.

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide an AFC circuit that is less likely to malfunction even when the CN ratio decreases.

[0011]

[Means for Solving the Problems] In order to solve the above problems, the AFC circuit of the present invention includes a frequency converter that converts the frequency of an input signal, a local oscillator, a PLL frequency control circuit, and a frequency converter. a bandpass filter that receives the output signal of the input signal and passes only the desired signal;
a phase demodulator that receives the output signal of the bandpass filter; a synchronization detection circuit that detects a synchronization state of the phase demodulator;
A frequency error detection circuit that inputs the carrier signal reproduced by the phase demodulator to detect frequency deviation, and a local oscillator included in the frequency conversion circuit that inputs the output signal of the frequency error detection circuit and the output signal of the synchronization detection circuit. This device is equipped with a control means such as a microcomputer that controls the oscillation frequency of the AFC circuit, and when synchronization detection is not obtained, the second intermediate frequency is swept, and when synchronization detection is obtained, the normal AFC circuit is used. It is characterized by performing frequency pull-in control.

0012

According to the present invention, the input signal is frequency-converted by the frequency conversion circuit, passed through the band-pass filter, and inputted to the phase demodulator. The phase demodulator regenerates the carrier signal, and the synchronization detection circuit detects the synchronization state of the phase demodulator. Furthermore, when synchronous detection is obtained, the frequency of the carrier signal matches the center frequency of the phase modulated wave that is the input signal. Therefore, when the synchronization signal is obtained, the frequency error detection circuit
The carrier wave signal reproduced by the phase demodulator is inputted, the deviation of the second intermediate frequency is detected, and the oscillation frequency of the local oscillator included in the frequency conversion circuit is controlled by the microcomputer. On the other hand, when the synchronization detection signal indicating the synchronization state of the phase demodulator is not detected, the microcomputer controls the oscillation frequency of the local oscillator included in the frequency conversion circuit to sweep the second intermediate frequency. . After the synchronization detection signal is detected by sweeping the second intermediate frequency, the output signal of the frequency error detection circuit is used to perform normal frequency pull-in control of the AFC circuit.

[0013] As described above, the signal input to the frequency error detection circuit is a carrier wave signal regenerated by a phase demodulator, and therefore has no phase modulation component. Moreover, when the CN ratio of the input signal is low, the input noise component is reduced by the narrow band characteristics of the PLL of the phase demodulator. Therefore, deterioration in the operation of the AFC circuit due to noise is reduced, and deterioration in demodulation characteristics due to frequency shift of the phase demodulator can be reduced.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, 1 is an input terminal for a first intermediate frequency signal, 2 is a first intermediate frequency amplification circuit, 3 is an image filter, 4 is a frequency converter, 5 is a band pass filter, and 6 is a first intermediate frequency signal input terminal.
is an MSK demodulator, 7 is a high-order multiplex decoder, 8 is an audio signal processing circuit, 9 and 10 are audio output signal terminals, 20 is a local oscillator, 21 is a PLL frequency control circuit, and 22 is a control means for controlling AFC. A microcomputer circuit, 23
3 is a frequency error detection circuit, 33 is a synchronization detection circuit, and 40 is a synchronization detection signal.

The operation of the AFC circuit configured as described above will be explained below. The 1 GHz band MSK signal input to the input terminal 1 is converted to the 140 MHz band MSK signal by a tuning circuit consisting of a first intermediate frequency amplifier circuit 2, an image filter 3, a frequency converter 4, a local oscillator 20, and a PLL frequency control circuit 21. converted into two intermediate frequencies. The bandpass filter 5 is a channel filter for extracting only the MSK signal and removing noise and signals of other channels, and generally a Gaussian characteristic filter with excellent phase group delay characteristics is employed.

[0017] The MSK demodulator 6 is an MSK demodulator in the 140 MHz band.
It plays the role of inputting the K signal and extracting I and Q baseband signals that are orthogonal to each other. The MSK demodulation stage divides the reproduced carrier signal into two components, in-phase and quadrature, and synchronously detects the input signal using each component. Since the MSK demodulator 6 has a large deterioration in demodulation characteristics due to frequency deviation, the frequency deviation of the second intermediate frequency is ±
It is necessary to keep the frequency below 100kHz. Therefore, the frequency step of the frequency synthesizer composed of the frequency converter 4, local oscillator 20, and PLL frequency control circuit 21 is 3.
Set to about 0kHz.

The high-order multiplex decoder 7 receives the MSK demodulated 6
It functions to separate the digitally multiplexed audio signals for each channel into their respective channels, and to correct bit errors caused by deterioration of the transmission system through digital processing. The digital signal output from the high-order multiplex decoder 7 is guided to the audio signal processing circuit 8. The audio signal processing circuit 8 performs interleaving, which is PCM decoding processing, range bit processing, and control signal processing. Also, with the D/A converter,
Converts the digital signal to an analog signal and outputs the audio baseband signal (R, L) through the LPF to the output terminals 9 and 10.
This is what is output to.

The frequency error detection circuit 23 is a detection circuit for inputting the carrier signal reproduced by the MSK demodulator 6 so that the second intermediate frequency becomes a predetermined frequency. When the synchronization signal is obtained, the frequency error detection circuit 23
gives an output signal to the microcomputer 22 when the oscillation frequency of the reproduced carrier wave and the second intermediate frequency deviate from the center frequency by about ±20 kHz. Using this signal, the microcomputer 22 controls the frequency synthesizer circuit to set the second intermediate frequency to a predetermined frequency. When synchronization detection is not obtained, the frequency error detection circuit 23 does not operate normally, so the frequency pull-in operation of the AFC circuit cannot be executed. Therefore, the second intermediate frequency is swept by the microcomputer 22. After synchronization detection is obtained with the sweep, the output signal of the frequency error detection circuit 23 is used to perform normal frequency pull-in control of the AFC circuit.

According to this configuration as described above, the signal input to the frequency error detection circuit 23 is a carrier wave signal reproduced by a phase demodulator, so there is no phase modulation component, and the CN ratio of the input signal is When low, the PL of the phase demodulator
Since the noise component is reduced by the narrowband characteristic of L, C
Even when the N ratio is low, malfunctions in AFC operation are reduced. Furthermore, if the output data of the frequency error detection circuit 23 is taken in five times in succession by the microcomputer 22 and subjected to majority decision, an integral effect can be obtained, resulting in an even lower CN.
MSK demodulator 6 enables accurate AFC operation up to the ratio
Deterioration of demodulation characteristics is reduced.

Note that in the above embodiment, the synchronization detection signal 4
0 is the output of the synchronization detection circuit 33, but a high-order frame synchronization signal output from the high-order multiplex decoder 7 may also be used. Furthermore, although the synchronization detection signal 40 is the output of the synchronization detection circuit 33, it is a low-order frame output from the audio signal processing circuit 8.
A system synchronization signal may also be used.

[0022]

As described above, according to the present invention, there is provided a frequency conversion circuit including a frequency converter for converting the frequency of an input signal, a local oscillator, and a PLL frequency control circuit; a bandpass filter that passes only a signal; a phase demodulator that receives an output signal of the bandpass filter; a synchronization detection circuit that detects a synchronization state of the phase demodulator; and a carrier wave regenerated by the phase demodulator. a frequency error detection circuit that inputs a signal and detects a frequency deviation; and an output signal of the frequency error detection circuit and an output signal of the synchronization detection circuit are input to control the oscillation frequency of a local oscillator included in the frequency conversion circuit. The control means sweeps the second intermediate frequency when synchronization detection is not obtained, and performs normal frequency pull-in control when synchronization detection is obtained.
Malfunction of the AFC circuit when the ratio is low is greatly improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an audio PCM broadcast receiver in an embodiment of the present invention.

[Fig. 2] Block diagram of a conventional audio PCM broadcast receiver

[Figure 3] Spectrum of MSK modulated wave

[Figure 4] Block diagram of frequency error detection circuit

[Figure 5]CN
Ratio versus detection frequency characteristic diagram

[Explanation of symbols]

1 Input terminal for first intermediate frequency signal 2 First intermediate frequency amplifier 3 Image filter 4 Frequency converter 5 Bandpass filter 6 MSK demodulator 7 High-order multiplex decoder 8 Audio signal processing circuit 9, 10 Audio output signal terminal 20 Local Oscillator 21 PLL frequency control circuit 22 Microcomputer circuit that controls AFC 23 Frequency error detection circuit 33 Synchronization detection circuit 34 Square circuit 35 Divide-by-2 circuit 36 Multiplier 37 Low-pass filter circuit 38 Comparator 39 Reference voltage

Claims (1)

[Claims] 1. A frequency conversion circuit comprising a frequency converter, a local oscillator, and a PLL frequency control circuit that converts the frequency of an input signal; a bandpass filter that receives an output signal of the frequency conversion circuit and passes only a desired signal; a phase demodulator that receives the output signal of the bandpass filter; a synchronization detection circuit that detects a synchronization state of the phase demodulator; and a carrier wave signal regenerated by the phase demodulator that receives the carrier wave signal and detects a frequency shift. A frequency error detection circuit, and a control means for controlling an oscillation frequency of a local oscillator included in a frequency conversion circuit by inputting an output signal of the frequency error detection circuit and an output signal of the synchronization detection circuit, and the synchronization detection is achieved. An AFC circuit that sweeps the second intermediate frequency when the synchronization is not detected, and performs normal frequency pull-in control when synchronization is detected.