JPH04354004A - Duplex system for programmable controller - Google Patents

Abstract

PURPOSE:To improve a reliability without using a duplex unit, to make a program processing constitution simple, and to easily change a backup processing. CONSTITUTION:Status/command buses 62 and 63 for mutually detecting and communicating the state of the other side, status/command bus input and output ports 48 and 49 which interface those status/command buses, and programmable controllers 40 and 41, continue to execute a control at the time of a backup. This device is equipped with a data bus for transferring the executed result information, and data bus interfaces 50 and 51 which interface the data bus. And also, this device is equipped with buffer memories 52 and 53 for receiving and transmitting the executed result information, and memories 46 and 47 having management tables for dividing the executed state of their own into plural phases, always communicating it to the other side process controller, and deciding the phase for transition next to their own from the phases of the other and their own process controllers.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a duplexing device for a standby type programmable controller used, for example, in a programmable controller for controlling a plant system in which a system failure is not allowed.

0002

2. Description of the Related Art Conventionally, as an example of this type of programmable controller duplication device, there is one constructed as shown in FIG. A duplex unit 3 is arranged between two programmable controllers PC1 (hereinafter referred to as controller 1) and programmable controller PC2 (hereinafter referred to as controller 2).

The redundant unit 3 includes a monitoring section 5 that monitors the controllers 1 and 2, and controls switching signals between the active side and the standby side based on the monitoring results of the monitoring section 5, and controls the transmission/reception status of docking data from the controller. 1 and 2, and a buffer memory 7.

A stator bus (STS 1) 8 for notifying and detecting the operating state of the controller 1 is arranged between the monitoring section 5 and the controller 1, and a status bus (STS 1) 8 for notifying and detecting the operating state of the controller 1 is arranged between the monitoring section 5 and the controller 2. A status bus (STS2) 9 is provided to notify and detect the operating state.

[0005] Between the duplication control section 6 and the controller 1,
An interrupt bus 10 (INT1) and a control bus 12 (C
An interrupt bus 11 (INT2) and a control bus 13 (CNT2) for notifying transmission and reception of switching signals and tracking data are arranged between the duplication control section 6 and the controller 2.

Furthermore, a data bus (DBS1) 14 for transmitting and receiving tracking data is arranged between the buffer memory 7 and the controller 1, and a data bus (DBS1) for transmitting and receiving tracking data is arranged between the buffer memory 7 and the controller 2. A bus (DBS2) 15 is arranged. An IO bus (
An IO bus (IOBS2) 17 is arranged between the controller 2 and the I/O unit 4.

[0007] Now, assuming that controller 1 is on the operating side and controller 2 is on standby, the monitoring section 5 of the redundant unit 3 communicates with both controllers 1 via status buses 8 and 9.
, 2. The controller 1 on the operating side periodically writes tracking data, which is the control result, to the buffer memory 7 of the duplexing unit 3 through the data bus 14, and notifies the duplexing control section 6 of the duplexing unit 3 via the control bus 12 when the writing is completed. However, the duplex control unit 6 is connected to the standby controller 2 via the interrupt bus 11.
controller 2 on the standby side connects data bus 1.
5, read the tracking data and import it into yourself. When the reading is completed, the duplex control section 6 of the duplex unit 3 is notified via the control bus 13. In response, the duplication control unit 6 notifies the active controller 1 of the completion of reading via the interrupt bus 10. During this period, the controller 1 on the active side does not write tracking data for the next cycle.

If the controller 1 on the active side goes down due to a fatal abnormality, the duplexing unit 3 detects this via the status bus 8, and the duplexing control section 6 sends the controller 1 on the standby side via the interrupt bus 11. A switching signal is notified to the controller 2. When the controller 2 on the standby side receives the switching signal, it becomes active and continues to perform control based on the tracking data that has been captured up to that point.

[0009]

In the conventional system described above, the duplex system is established with the duplex unit 3 always intervening. Therefore, duplex unit 3
must be highly reliable.

Therefore, the present invention is capable of monitoring each other's operating status and sending and receiving tracking data using only the functions of the controller without using a redundant unit, and which constantly detects the other party's operating status and performs backup operations with high precision. An object of the present invention is to provide a programmable controller duplication device that can control the programmable controller.

[0011]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides two program controllers in which one of the program controllers is in an operating state and the other is in a standby state in preparation for backup, and the program controllers are mutually connected to each other. In a programmable controller duplication device that monitors the status of the other party, and if the active side goes down, the standby side detects it and continues to control the active side, preventing system failure, detects and notifies each other of the status of the other programmable controller. A status/command bus to interface with the status/command bus input/output port, and execution result information, which is data for the programmable controller to continue executing control during backup, to the other programmable controller. a data bus for interfacing with the data bus, a buffer for receiving and transmitting the execution result information, and dividing the execution state of the own process controller into multiple phases and communicating the status/commands with each other. It constantly notifies the other party's process controller via the bus and is equipped with a phase management table for determining the next phase of the own process controller from the other party's process controller phase and the own process controller's phase. This feature is characterized by controlling the backup operation processing of.

0012

[Operation] According to the present invention, by simply providing a status/command bus, a status/command input/output port that interfaces with the status/command bus, and a data bus and a data bus interface that interfaces with the status/command bus, there is no need to use a duplex unit. A highly reliable programmable controller duplication device can be constructed.

[0013]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of the present invention, including a programmable controller PC1 (hereinafter referred to as controller 20), a programmable controller P
C2 (hereinafter referred to as controller 21) is configured as follows, and a status/command bus 30 and a data bus 31 are arranged between the two.

The controllers 20 and 21 have the same configuration, and include processors 22 and 23 that control the overall control and output a reset signal from a reset signal line for switching between the transmission/reception mode and the reset mode;

It is possible to exchange status signals and command signals bidirectionally via the status/command bus 30, and it is also possible to generate an interrupt to the other party by sending a command signal. Status/command input/output ports 24 and 25 that can reset the output of the status signal to zero by issuing a reset signal to the reset signal lines 32 and 33, and temporarily store received tracking data. buffer memories 28 and 29 for
Data bus 31 connecting between buffer memories 28 and 29
and,

Buffer memories 28, 29 and main bus 3
4 and 35, and is capable of bidirectional data exchange, and can be switched between transmission/reception mode and reset mode by reset signals from reset signal lines 32 and 33 from the processors 22 and 23, Furthermore, in send/receive mode, data is sent to the other party's buffer memory 2.
It is possible to write directly to the buffer memories 28 and 29, and also to read the data in the own buffer memories 28 and 29. Moreover, in the reset mode, the data in the own buffer memories 28 and 29
data bus interfaces 26 and 27 that can only read data 8 and 29 but cannot transmit data;

Memories 36 and 37 in which phase transition management data for determining the backup operation of the controller, which will be described later, are stored in advance, and an I/O interface 38,
It is equipped with 39.

The memories 36 and 37 are each provided with a phase transition management table 200 as shown in FIG. The opponent's phase 202 is placed in each phase row, and the player's own phase 204 to be transitioned to next can be determined from the correlation on the X axis. In the figure, 205 indicates the direction of checking the opponent's phase, 206 indicates the direction of detecting your next phase, 207 indicates your current phase, 208 indicates the next phase to transition to, and 209 indicates the current opponent's phase.

In such a configuration, the status/command input/output ports 24 and 25 can notify the other controller of their own status as a phase via a status signal via the status/command bus 30. Status bus/command 30 to check the status of the other party
It can be known as a phase through . Then, from the phase transition management table 200, check the current opponent's phase 209 that corresponds to the row of your current phase 207 in the direction of 205, and if there is a corresponding one,
Phase 208 to transition to next in 206 directions at that time
and execute the processing.

Now, when an error occurs in the operating controller 20, for example, the processor 22 automatically makes the signal on the reset signal line 32 inactive and clears the own status signal output of the status/command input/output port 24 to zero. do. As a result, the controller on the standby side, for example 21, can detect an error down of the other party when the status signal of the other party at the status/command input/output port 25 becomes zero-cleared, and at that timing, the controller on the active side 20 can be launched. When the command signal is outputted via the status/command bus 30, it can be used to interrupt the other party's controller, and can be used to notify a tracking data transmission completion interrupt signal or the like. The data bus interfaces 26 and 27 allow the active side to directly transmit tracking data to the other party's buffer memories 28 and 29 through the data bus 31. When the transmission completion interrupt signal is notified to the other controller through the status/command bus 30, the transmission completion interrupt occurs on the standby side, and at that timing, the buffer memories 28 and 29 are
The tracking data written in the data can be captured, and when the capture is completed, the completion of reception can be notified to the operating side via the status bus/command bus 30.

Specific embodiments of the present invention will be described below with reference to FIGS. 3 to 12. FIG. 3 is a block diagram showing this configuration, and the controllers 40 and 41 include processors 42 and 43 that manage overall control, a program execution process (FIG. 4), a tracking process (FIG. 5), and a tracking data reception process (described later). A memory P4 that stores the overall control program and plant control program (73 in FIG. 4) shown in FIG. 11, including the program for monitoring processing (FIG. 7)
4, 45, memories D 46, 47 capable of storing calculation data and I/O data, and an I/O interface 54, which interfaces between the I/O units 56, 57.
55, a status/command input/output port 48 that interfaces between a status bus (SBS) 62, a command bus (CBS) 63, and main buses 58 and 59;
49, data bus (DBS) 64 and buffer memory 5
2, 53 and main buses 58, 59, and a buffer memory 5 that temporarily stores received tracking data.
2,53 and status/command input/output port 48,
49 and data bus interface 50,
Reset signal lines 60, 6 for switching the operation mode of 51
1 and the status/command input/output ports 48 and 49; a data bus 64 that connects the data bus interfaces 52 and 53; a data bus 64 that connects the data bus interfaces 52 and 53;
4, 45 and memory D46, 47 and I/O interface 54, 55 and status/command input/output port 4
8, 49 and data bus interfaces 50, 51; and an I/O bus that connects I/O interfaces 54, 55 and I/O units 56, 57. 65 and 66.

The status/command input/output port 48 is configured as shown in FIG. If so, it will be output as is, and the reset signal 48
If 6 is active, register with reset (OR)
It is reset to zero at 481 and becomes a zero output. The input of the status bus 487 is once latched into the register (RR) 482 and can be read out at any time.

The output of the command bus 488 is once latched in the register with reset (OR) 483, and if the reset signal 486 is active, it is output as is, and if it is inactive, the register with reset 483 is reset to zero and the output is zero. Become. The input of the command bus 488 is once latched in the register (RR) 484 and can be read out at any time, and is further latched into the interrupt output register (RR) 484.
IR) At the same time, the interrupt is latched to 485 and the interrupt is on the interrupt line 4.
90. The status/command input/output port 49 has the same configuration as the status/command input/output port 48 described above.

Data bus interface 50, 5 in FIG.
1, data is transmitted through a transmission gate (not shown), and if the reset signal is inactive, data is transmitted to the data bus 64, and if active, no data is transmitted to the data bus 64. The received data is written to the buffer memory 52 as is. The data in the buffer memory 52 can be read out as is.

Next, a method for creating a phase transition management table will be explained with reference to the phase transition diagram shown in FIG. As shown in the phase transition diagram of FIG. 9, the phase 300 includes power ON (power on) 302, semi-standby 303, and standby 3.
It consists of seven phases: 04, in operation 305, individual operation 306, and down/power OFF (power off) 307.

Power ON 302 indicates when the power is turned on, semi-standby 303 indicates preparation for operation or standby, and standby 3
04 indicates a state in which the program is switched to operation at any time, 305 in operation indicates a state in which a program is being executed, and 306 in independent operation indicates that the active side is operating in a state in which the standby side is not on standby. In phase 300, the next phase is determined based on the correlation between your phase and the opponent's phase.

A phase transition management table 400 shown in FIG. 10 is stored in the memories D 46 and 47 in order to determine the next phase. This table 400 is
Your phase is set in row 401, and each row lists the opponent's phase 403. Check the row of the corresponding own phase and if there is a corresponding phase of the opponent, move to the next phase 40 in that column.
It has a structure that allows it to take out phase 2 as the next phase to transition to.

An overall control program shown in FIG. 11 is stored in the memories P 44 and 45, and its execution starts when the power is turned on. That is, when the power is turned on (500), it starts (501), first performs initialization processing (502), performs overall initialization, then performs phase transition check processing (503), and The phase to which the next transition should be made is extracted from the phase of , and the phase of the opponent, and the corresponding phase 504 to 504 of the independent operation processing phase 504, the operation processing phase 505, the standby processing phase 506, and the standard standby processing phase 507 is extracted.
Execution can be moved to the routine 507. When entering a new phase, a predetermined program execution process is executed (508), and the next phase transition check process is executed (509), thereby making it possible to extract the phase to which the next transition should be made. Perform program execution processing (508
), when an abnormality is detected, the process goes down (5
10).

The phase transition check process (600) is as follows:
As shown in FIG. 12, first, one's own phase is output to the other controller 608 (601), and then the phase of the other controller 608 is read (602). Then, the phase to which the next transition should be made is extracted based on the phase transition management table (200 in FIG. 2) (603). Compare this phase with your current phase (604), and if they are the same, there is no transition and a return without transition (606), and if they are different, it is a return with transition (605).

Next, the operation of the programmable controller duplication device configured as described above will be explained. Now, in Figure 11, turn on the power (500, 50
1), the initialization process is first executed according to the overall control program (502), and the controller 40 in FIG.
41 is normal, the processors 42 and 43 activate the signals on the reset signal lines 60 and 61 to the status/command input/output ports 48 and 49 and the data bus interfaces 50 and 51, enable status output, and connect the data bus The operation mode of the interfaces 50 and 51 is set to transmit/receive mode. Then, as a result of turning on the power of one's own phase and executing a phase transition check process (503), the next phase to be transitioned to is extracted and the process of the corresponding phase is executed (504 to 507). At this time,
The phase transition check process 503 checks the power ON row of the phase transition management table 400 shown in FIG. 10, and sets the next phase to semi-standby. When entering the semi-standby phase process 507, the phase transition check process 50 is performed again.
3 and take out the next phase. At this time, if the opponent's phase is power OFF, solo operation processing phase 5
04, and if it is on standby, the in-operation processing phase 505,
If it is in operation, take out the standby processing phase 506,
Executes the next phase process. Also, if other than that,
Extract the semi-standby processing phase and perform semi-standby phase processing 5
Re-run 07. Independent operation processing 504, operation processing 5
05, the program execution process 508 is executed, and the program execution process 71 shown in FIG. 4 is executed by the scan cycle interrupt 70.

Here, if the controller 40 is the active system and the controller 41 is the standby system, the processor 42 of the active controller 40 executes the program execution process 71 shown in FIG. Execute repeatedly. Among these, batch input/output processing 72
, inputs I/O data from the I/O unit 56, and inputs the batch input/output memory 461 in the memory D 46.
and outputs the calculation result of the previous cycle of the batch input/output memory 461 to the I/O unit 56. Next, the plant control program, which is a user application, is executed (73), and calculations are performed based on the I/O data on the batch input/output memory 461 and the data on the data memory 462 stored in the memory D 46, and the results are batch input/output. Write to memory 461 and data memory 462.

Next, the tracking process 80 shown in FIG. 5 is executed, and first, the reception completion signal 9 of the standby controller 41 is
0 via the status bus 62, checks whether the previous reception has been completed (81), and waits until it is completed. Once completed, the tracking data transmission process 82 reads data from the data memory 462 and batch input/output memory 461 and transmits it to the buffer memory 53 of the standby controller 41 as tracking data. When the transmission is completed, a tracking transmission completion notification process 83 notifies the standby side controller 41 of a transmission completion interrupt signal 91 via the command bus 63, and starts the tracking data reception process 89 of the standby side controller 41.

The processor 43 on the standby side starts and executes the tracking data reception process 100 shown in FIG. 6 in response to the transmission completion interrupt signal 109 from the controller 40 on the active side. First, tracking data read processing 101 is executed to read the tracking data transmitted to the buffer memory 52 and import it into the memory D 47 including the batch input/output memory 471 and data memory 472. When the capture is completed, a reception completion signal 108 is sent to the active controller 40 via the status bus 62. The active controller 40 executes the phase transition check process 75 shown in FIG. 4, extracts the next phase, and if it is the same as the current one, continues the process as it is; if it is different, moves to the corresponding phase process.

In the embodiments described above, an example has been described in which the controller 40 is on the active side and the controller 41 is on the standby side, but since the operation will be the same even if this is reversed, the explanation thereof will be omitted.

As described above, the controllers 40, 4
status/command input/output ports 48 and 4 that interface the status bus 62 and command bus 63 for exchanging status signals and command signals with the 1;
9, and a bus interface 50 that interfaces with the data bus 64 for transmitting and receiving tracking data.
51 and buffer memories 52 and 53 for receiving tracking data, and by connecting the controllers 40 and 41 with a status bus 62, a command bus 63, and a data bus 64, a duplex system can be configured. Further, for example, when the active controller 40 goes down due to an error, the processor 42 inactivates the reset signal 60 so that the standby controller 40
The status signal that notifies the state is cleared to zero, that is,
The system enters the down phase, whereby an abnormality in the active controller 40 can be automatically detected, and at the same time, the bus interface 50 of the data bus 64 also automatically stops transmitting. In other words, since it is inevitably equipped with a fail-safe function, a highly reliable redundant system can be constructed. Furthermore, the operating state of the controller can be managed by phases, and the phase to be processed next can be clearly determined from the opponent's phase and one's own phase using a phase transition management table, thereby simplifying the program processing configuration. Can be done.

[0036]

[Effects of the Invention] According to the present invention, a highly reliable duplex system can be constructed without using a duplex unit, and the state of the controller is managed in a phase manner, and a phase transition management table is provided, thereby performing the following processing. It is possible to provide a programmable controller duplication device that can simplify the program processing configuration, improve reliability, and easily change backup processing by rewriting the phase transition management table according to the purpose. .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a programmable controller duplication device according to the present invention.

FIG. 2 is a diagram showing a phase transition management table for explaining memories 36 and 37 in FIG. 1;

FIG. 3 is a block diagram showing a specific embodiment of the present invention.

FIG. 4 is a diagram showing a program execution process executed by the active controller to explain the operation of FIG. 3;

FIG. 5 is a diagram showing tracking processing executed by the active controller to explain the operation of FIG. 3;

FIG. 6 is a diagram showing tracking reception processing executed by the standby controller to explain the operation of FIG. 3;

FIG. 7 is a diagram showing a monitoring process executed by a standby controller to explain the operation of FIG. 3;

FIG. 8 is a diagram showing an equivalent circuit of the status/command input/output port in FIG. 3;

FIG. 9 is a diagram showing the states of the controller by phase transitions to explain the operation of FIG. 3;

FIG. 10 is a diagram showing a phase transition management table of FIG. 3;

FIG. 11 is a diagram for explaining the overall control program of FIG. 3;

FIG. 12 is a diagram showing phase transition check processing for explaining the operation of FIG. 3;

FIG. 13 is a block diagram showing a schematic configuration of an example of a conventional programmable controller duplication device.

[Explanation of symbols]

40, 41...Programmable controller, 42, 43
...Processor, 44,45...Memory P, 46,47...Memory D, 48,49...Status/command input/output port, 50,51...Data bus interface, 52,5
3... Buffer memory, 54, 55... I/O interface, 60, 61... Reset signal line, 62... Stator bus,
63...Command bus, 64...Device bus, 65, 66...I
/O bus.

Claims (1)

[Claims] Claim 1: Of the two program controllers, one is in an operating state and the other is in a standby state in preparation for backup, and each of the program controllers mutually monitors the other's status, and if the operating side goes down, the standby side In a programmable controller duplication device that detects and continuously executes control on the operating side and prevents system failure, a status/command bus that detects and reports the status of each other's programmable controllers and a status that interfaces it. /Command bus input/output port, data bus for transferring execution result information, which is data for the programmable controller to continue executing control during backup, to the other programmable controller, and a data bus interface for interfacing it. A buffer for receiving and transmitting the execution result information, a buffer for receiving and transmitting the execution result information, and a process controller that divides the execution status of its own process controller into multiple phases and constantly notifies the process controller of the other party via the status/command bus. A programmable system characterized by having a phase management table for determining the process controller phase of the process controller, and a phase management table for determining the next phase of the own process controller from the phase of the own process controller, and controlling the next backup operation process. Controller duplication device.