JPH04351799A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce testing man-hours by providing a testing circuit which simultaneously compares stored data read out into the corresponding bit lines from plural memory cells, connected to the selected word lines of each memory array, per bit line and per word line unit. CONSTITUTION:X address coders XD0 and XD1 decode internal address signals and selectively make the corresponding word lines of memory arrays ARY0 or ARY1 a high level selected condition. As a result, arrays ARY0 or ARY1 are selectively activated and the n+1 memory cells, which are connected to the selected word lines, output minute read out signals corresponding to the respective holding data against corresponding complementary bit lines B0* to Bn*. And the arrays ARY0 and ARY1 are selectively activated according to internal signals when a dynamic type RAM becomes a normal write in or a read out mode and simultaneously activated by the dynamic type RAM.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a dynamic RAM (random access memory) having a relatively large storage capacity and a technique particularly effective for testing its functionality.

0002

[Background Art] As the capacity of dynamic RAM, etc. continues to increase, one way to efficiently perform functional tests is to write and read multiple bits of stored data at the same time in one memory access and compare and check. The so-called multi-bit test is JEDEC (Joint Elect
ron Device Engineering
Council). In addition, in order to further improve the efficiency of functional testing of dynamic RAM, a word test method has been proposed in which the read data of all memory cells connected to a selected word line of a memory array are compared and verified in units of word lines. ing.

Regarding multi-bit testing of dynamic RAM etc., for example, see "Nikkei Microdevices" 198
It is described on pages 53 to 62 of the May 7 issue.

0004

[Problem to be Solved by the Invention] In the above-mentioned multi-bit test, the number of bits of stored data that can be written or read simultaneously is limited by the number of main amplifiers provided in a dynamic RAM, etc., and is about 4 to 16 bits. . For this reason, in dynamic RAMs and the like whose capacity has significantly increased, a huge amount of time is required for functional testing of all addresses, which hinders cost reduction. On the other hand, the word test method uses an AND or OR circuit to compare and match read data, so it is necessary that the read data of all memory cells connected to a selected word line be at the same logic level. Condition. Therefore, arbitrary test data cannot be written to each adjacent memory cell, and the detectable failure modes are limited. To deal with this, it may be possible to provide a test register that holds expected value data for each bit line of the memory array, but this would increase the amount of hardware dedicated to functional testing, and it is still necessary to reduce the cost of dynamic RAM, etc. This results in interference.

[0005] An object of the present invention is to provide an efficient test method for dynamic RAM, etc., which is not limited by test data while suppressing an increase in the amount of hardware. Another object of the present invention is to
The objective is to reduce the number of man-hours required for testing AM, etc., to promote lower costs, and to increase the failure detection rate in functional tests, thereby increasing the reliability of dynamic RAM, etc.

[0006]

[Means for Solving the Problems] A brief overview of typical inventions disclosed in this application is as follows. That is, a memory array such as a dynamic RAM is divided into at least two parts, these memory arrays are simultaneously activated in a predetermined test mode, and a plurality of memories coupled to a selected word line of each memory array are activated simultaneously. A test circuit is provided which compares and verifies the stored data read out from the cells to the corresponding bit lines, bit line by bit line and word line by word line.

[0007]

[Operation] According to the above means, while suppressing the increase in the amount of hardware, and without being restricted by test data,
Functional tests regarding a plurality of paired memory arrays can be performed simultaneously and word line by word line. As a result, it is possible to reduce the number of man-hours required for testing dynamic RAMs and the like, thereby promoting cost reduction, and to increase the failure detection rate in functional tests, thereby increasing the reliability of dynamic RAMs and the like.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a block diagram of an embodiment of a dynamic RAM (DRAM) to which the present invention is applied. In addition, FIG. 2 shows the dynamic type RA of FIG.
A partial circuit diagram of an embodiment of a test circuit included in M and its peripheral portion is shown. Based on these figures, an overview of the configuration and operation of the dynamic RAM of this embodiment as well as its characteristics will be described. Note that the circuit elements in FIG. 2 and the circuit elements constituting each block in FIG. 1 are formed on a single semiconductor substrate such as single crystal silicon using conventional semiconductor integrated circuit manufacturing techniques. In the circuit diagrams below, the MOSFET (metal oxide semiconductor field effect transistor; in this specification, MOSFET is a general term for insulated gate field effect transistors) whose channel (back gate) part is marked with an arrow. is a P-channel MOSFET, and is shown to be distinguished from an N-channel MOSFET that is not marked with an arrow. Further, all illustrated transistors (in this specification, bipolar transistors are simply referred to as transistors) are NPN transistors.

In FIG. 1, the dynamic RAM of this embodiment includes, although not particularly limited to, two memory arrays ARY0 and ARY1, and X address decoders XD0 and XD provided corresponding to these memory arrays.
1, sense amplifiers SA0 and SA1, column switch C
It includes S0 and CS1 and Y address decoders YD0 and YD1. Among these, memory arrays ARY0 and ARY1 are m+ arranged in parallel in the vertical direction in the figure.
One word line and n+ lines arranged in parallel in the horizontal direction
A set of complementary bit lines B0* to Bn* (here, for example, non-inverted bit line B0 and inverted bit line B0B are collectively expressed as complementary bit line B0*. Also, when it is enabled, selective So-called inverted signals or inverted signal lines, etc., which are at low level in (m+1)×(
n+1) dynamic memory cells.

The word lines constituting memory arrays ARY0 and ARY1 are coupled to corresponding X address decoders XD0 or XD1, respectively, and are alternatively brought into a selected state. The X address decoders XD0 and XD1 are commonly supplied with i-bit internal address signals x0 to xi-1 excluding the most significant bit from the X address buffer XAB, and internal control signals XG0 or XG from the timing generation circuit TG.
1 is supplied respectively. Also, X address buffer
AB is supplied with i+1-bit X address signals X0 to Xi in a time-division manner via external terminals A0 to Ai, and is supplied with an internal control signal XL from the timing generation circuit TG.

[0011] The X address decoders XD0 and XD1 are
When the corresponding internal control signal XG0 or XG1 is set to high level, it is selectively put into an operating state. In this operating state, the X address decoders XD0 and XD1 are
The internal address signals x0 to xi-1 are decoded to selectively set the corresponding word line of the memory array ARY0 or ARY1 to a high level selection state. As a result, memory arrays ARY0 and ARY1 are selectively activated, and data stored in each of the n+1 memory cells coupled to the selected word line is transferred to the corresponding complementary bit lines B0* to Bn*. A corresponding minute readout signal is output. In this example, internal control signals XG0 and
G1 is selectively set to a high level according to the internal address signal xi of the most significant bit when the dynamic RAM is placed in a normal write or read mode, and simultaneously set to a high level when the dynamic RAM is placed in a predetermined test mode. It is said that Therefore, the memory array ARY
0 and ARY1 are selectively activated according to the internal address signal xi when the dynamic RAM is placed in normal write or read mode, and the dynamic RAM
When M is placed in the test mode, it is activated at the same time.

[0012] The X address buffer XAB is connected to an external terminal A.
The X address signals X0 to Xi, which are supplied in a time-division manner via 0 to Ai, are taken in according to the internal control signal XL, and based on these X address signals, the internal address signals x0 to
form xi. Of these, the most significant bit internal address signal xi is supplied to the timing generation circuit TG and data input/output circuit IOC, which will be described later, and the other internal address signals x0 to xi-1 are supplied to the X address decoder XD0 as described above. and XD1.

Next, memory arrays ARY0 and ARY1
As illustrated in FIG. 2, complementary bit lines B0* to Bn* constituting the
or the corresponding unit amplifier circuit USA0 to USAn of SA1
and on the other hand column switch CS0
Alternatively, it is selectively connected to the common data line CD0* or CD1* via a corresponding pair of switch MOSFETs of CS1. Sense amplifiers SA0 and SA1 are supplied with internal control signals PA0 and PA1, respectively, from timing generation circuit TG. Further, column switches CS0 and CS1 have corresponding Y address decoders YD0 or Y
Each of n+1 bit line selection signals is supplied from D1. Further, the Y address decoders YD0 and YD1 are supplied with i+1 bit internal address signals y0 to yi from the Y address buffer YAB, and are supplied with an internal control signal YG0 or YG1 from the timing generation circuit TG, respectively. The Y address buffer YAB is supplied with Y address signals Y0 to Y via the external terminals A0 to Ai.
i is supplied in a time-division manner, and an internal control signal YL is supplied from the timing generation circuit TG.

Here, sense amplifiers SA0 and SA1 are connected to memory array ARY0 or A, as shown in FIG.
It includes n+1 unit amplifier circuits USA0 to USAn provided corresponding to complementary bit lines B0* to Bn* of RY1. These unit amplifier circuits are the unit amplifier circuit USA in FIG.
0, a P-channel MOSFE
TQ3 and N-channel MOSFETQ13 and P
Channel MOSFETQ4 and N-channel MOSF
Its basic configuration is a latch formed by cross-connecting a pair of CMOS inverters made up of ETQ14. The sources of P-channel MOSFETs Q3 and Q4 constituting each latch are commonly coupled to a common source line SP0 or SP1, and the corresponding P-channel drive MOSFETQ
1 or Q2 to the circuit power supply voltage. In addition, N-channel MOSFETQ13 that constitutes each latch
The sources of Q14 and Q14 are common source line SN0 or SN
1, and further coupled to the ground potential of the circuit via the corresponding N-channel drive MOSFET Q11 or Q12. In this embodiment, the circuit power supply voltage is a positive power supply voltage, such as +5V.

Internal control signals PA0 or PA1 are supplied to the gates of N-channel type drive MOSFETs Q11 and Q12 of sense amplifiers SA0 and SA1, respectively, and these internal control signals are supplied to the gates of P-channel type drive MOSFETs Q1 and Q2. An inverted signal by a signal inverter N1 or N2 is supplied. As a result, the n+1 unit amplifier circuits USA0 to USAn constituting the sense amplifiers SA0 to SA1 receive the internal control signal PA0 or PA
1 is set to high level and the drive MOSFETs Q1 and Q11
Alternatively, by turning both Q2 and Q12 on, the device is selectively brought into operation. In this operating state, each unit amplifier circuit is connected to memory array ARY0 or ARY
The micro read signals outputted from the n+1 memory cells coupled to one selected word line via the corresponding complementary bit lines B0* to Bn* are amplified and converted into high level or low level binary read signals. do. Needless to say, the sense amplifiers SA0 and SA1 are connected to the memory array AR.
Corresponding to Y0 and ARY1, when the dynamic RAM is placed in the normal write or read mode, it is alternatively activated according to the internal address signal xi of the most significant bit, and when the dynamic RAM is placed in the test mode. At the same time, it is brought into operation.

On the other hand, column switches CS0 and CS1 connect complementary bit lines B of memory array ARY0 or ARY1.
It includes n+1 pairs of switch MOSFETs provided corresponding to 0* to Bn*. One of these switch MOSFETs is coupled to the non-inverted or inverted signal line of the corresponding complementary bit line B0* to Bn* of the memory array ARY0 or ARY1, and the other is coupled to the common data line CD0* or CD
Commonly coupled to 1* non-inverting or inverting signal line. Each pair of switches M forming column switches CS0 and CS1
The gates of the OSFETs are commonly coupled, and a corresponding bit line selection signal is supplied from the Y address decoder YD0 or YD1. This allows column switch CS0
The switch MOSFETs of each pair of MOSFETs and CS1 are selectively turned on when the corresponding bit line selection signal is alternatively set to high level, and the switch MOSFETs of each pair of the memory array ARY0 or A
The complementary bit lines B0* to Bn* corresponding to RY1 are selectively connected to the common data line CD0* or CD1*.

Y address decoders YD0 and YD1 are as follows:
When the corresponding internal control signal YG0 or YG1 is set to high level, it is selectively put into an operating state. In this operating state, Y address decoders YD0 and YD1 are
The internal address signals y0 to yi are decoded, and the corresponding bit line selection signal is alternatively set to high level. Y
Address buffer YAB takes in Y address signals Y0-Yi supplied time-divisionally via external terminals A0-Ai according to internal control signal YL, and generates internal address signals y0-yi based on these Y address signals. form,
It is supplied to Y address decoders YD0 and YD1. Y address decoders YD0 and YD1 are dynamic type R
When the AM is placed in a normal write or read mode, it is selectively activated according to the internal address signal xi, and when the dynamic RAM is placed in a predetermined test mode, neither of them is activated.

Common data lines CD0* and CD1*, to which complementary bit lines B0* to Bn* of memory array ARY0 or ARY1 are selectively connected, are coupled to data input/output circuit IOC. The data input/output circuit IOC is supplied with the most significant bit internal address signal xi from the X address buffer XAB, and is also supplied with internal control signals DWC and DOC from the timing generation circuit TG.

The data input/output circuit IOC includes two write amplifiers and a main amplifier provided corresponding to common data lines CD0* and CD1*, and a data input buffer and a main amplifier provided in common to these write amplifiers and main amplifiers. Contains data output buffer. Among these, the input terminal of the data input buffer is coupled to the data input terminal Din, and its output terminal is commonly coupled to the input terminals of the two write amplifiers. Output terminals of these write amplifiers are coupled to corresponding common data lines CD0* or CD1*, respectively. On the other hand, the input terminal of each main amplifier is coupled to the corresponding common data line CD0* or CD1*, and the output terminal thereof is commonly coupled to the input terminal of the data output buffer. The output terminal of this data output buffer is coupled to the data output terminal Dout. Data input/output circuit IOC 2
The write amplifiers are commonly supplied with the internal control signal DWC, and are each supplied with a non-inverted or inverted signal of the internal address signal xi. Further, the two main amplifiers of the data input/output circuit IOC are each supplied with a non-inverted or inverted signal of the internal address signal xi, and the data output buffer is supplied with an internal control signal DOC.

The data input buffer of the data input/output circuit IOC takes in write data supplied via the data input terminal Din when the dynamic RAM is in the write mode, and transmits it to the two write amplifiers. Each write amplifier is selectively brought into operation by setting the internal control signal DWC to a high level and setting the internal address signal xi to a corresponding logic level. In this operating state, each write amplifier forms a predetermined complementary write signal based on the write data supplied from the data input buffer, and generates a predetermined complementary write signal on the corresponding common data line CD0* or C
Write to the selected memory cell of memory array ARY0 or ARY1 via D1*.

On the other hand, the two main amplifiers of the data input/output circuit IOC are selectively activated by setting the internal address signal xi to the corresponding logic level. In this operating state, each main amplifier has memory array A
The binary read signal output from the selected memory cell of RY0 or ARY1 via the common data line CD0* or CD1* is further amplified and transmitted to the data output buffer. The data output buffer is selectively brought into operation by setting the internal control signal DOC to a high level. In this operating state, the data output buffer transfers the read signal supplied from the main amplifier to the data output terminal D.
Output via out. In addition, the data input/output circuit IO
C, that is, the data output buffer has the function of receiving an output signal TE of a test circuit TST, which will be described later, and outputting it from a data output terminal Dout when the dynamic RAM is placed in a predetermined test mode.

The timing generation circuit TG receives a row address strobe signal RASB, a column address strobe signal CASB, a write enable signal WEB, and an X address buffer XA, which are supplied as activation control signals from the outside.
Internal address signal xi of the most significant bit supplied from B
Based on this, the various internal control signals described above are selectively formed and supplied to each part of the dynamic RAM.

By the way, the dynamic type R of this embodiment
As described above, the AM includes a test circuit TST provided in common to the two memory arrays ARY0 and ARY1. This test circuit TST is laid out between memory arrays ARY0 and ARY1, that is, between sense amplifiers SA0 and SA1, and receives an internal control signal TM from a timing generation circuit TG. Here, the internal control signal TM is
Although not particularly limited, it is normally set to low level, and selectively set to high level when the dynamic RAM is placed in a predetermined test mode.

As shown in FIG. 2, the test circuit TST includes n+1 unit test circuits UTC0 to UTCn provided corresponding to complementary bit lines B0* to Bn* of the paired memory arrays ARY0 and ARY1; An error detection circuit EDC provided in common to these unit test circuits is provided. Among these, unit test circuit UTC0~UTC
n is one common node, that is, the level judgment node TP
and the other common node TN, that is, the ground potential of the circuit (first
Two sets of P-channel (first conductivity type) MOSFETQ5 (first MOSFET
SFET) and N-channel (second conductivity type) MOSFE
It includes TQ15 (second MOSFET), P-channel MOSFET Q6 (third MOSFET), and N-channel MOSFET Q16 (fourth MOSFET). MOSFETQ5 and Q constituting each unit test circuit
The gates of No. 6 are respectively coupled to non-inverted or inverted signal lines of corresponding complementary bit lines B0* to Bn* of one memory array ARY0 via corresponding switch MOSFETs Q19 and Q20. Switch MOSFET Q19
An internal control signal TM is commonly supplied to the gates of Q20 and Q20.

Similarly, MO constituting each unit test circuit
The gates of SFETQ15 and Q16 are connected to the corresponding complementary bit lines B0* to Bn of the other memory array ARY1 via corresponding switch MOSFETs Q21 and Q22.
* are respectively coupled to the non-inverting or inverting signal line. The internal control signal TM is commonly supplied to the gates of the switch MOSFETs Q21 and Q22. As a result, the unit test circuits UTC0 to UTCn are dynamic type R
When AM is in a predetermined test mode and the internal control signal TM is set to high level, the corresponding unit amplifier circuits USA0 to USAn of sense amplifier SA0 or SA1, that is, the corresponding complementary bit line of memory array ARY0 or ARY1, are selectively activated. Connected to B0* to Bn*.

Next, the error detection circuit EDC of the test circuit TST includes a pair of differential transistors T1 and T2. The collectors of these transistors are coupled to the supply voltage of the circuit via the corresponding load resistors R2 or R3, and between their commonly coupled emitters and the circuit ground potential they receive a constant voltage VG on their gates. An N-channel MOSFET Q23 is provided. The base of the transistor T1 is coupled to the level determination node TP and also to the power supply voltage of the circuit via a resistor R1. Further, a predetermined reference potential VBB is supplied to the base of the transistor T2. This allows MOSFET
Q23 acts as a constant current source, and the differential transistor T1
and T2, together with MOSFET Q23 and resistors R2 and R3, are set at the reference potential VBB with respect to the base potential of transistor T1, that is, the potential of level determination node TP.
It functions as a current switch circuit with a logic threshold of . The collector potential of the transistor T1 is supplied to the data input/output circuit IOC as the output signal TE of the test circuit TST.

As mentioned above, the level judgment node TP is
The input node of each unit test circuit is coupled to the ground potential of the circuit through unit test circuits UTC0 to UTCn, and the input node of each unit test circuit is selectively connected to the memory array A when in a predetermined test mode.
Complementary bit lines B0* to B corresponding to RY0 or ARY1
Connected to n*. At this time, one memory array AR
The logic level of the binary read signal established on the complementary bit lines B0* to Bn* of Y0 is the same as that of the other memory array ARY1.
2 established on the corresponding complementary bit lines B0* to Bn*
If it matches the value read signal, unit test circuit UTC
MOSFET Q5 and Q15 and Q from 0 to UTCn
6 and Q16 are not turned on at the same time. Therefore, the level judgment node TP is set to a high level similar to the power supply voltage of the circuit via the resistor R1, and the output signal TE of the test circuit TST is determined by the operating current supplied via the MOSFET Q23 and the resistance value of the resistor R2. It becomes a predetermined low level determined by. The low level of the output signal TE is output from the data input/output circuit IOC to the outside via the data output terminal Dout.

On the other hand, the logic level of the binary read signal established on the complementary bit lines B0* to Bn* of the memory array ARY0 is the binary read signal established on the corresponding complementary bit line B0* to Bn* of the memory array ARY1. If even one signal does not match, the corresponding unit test circuit UTC0~
A combination of MOSFETs Q5 and Q15 or Q6 and Q16 of UTCn is simultaneously turned on. Therefore, the level determination node TP is coupled to the ground potential of the circuit, that is, the low level, through these MOSFETs, and the output signal TE of the test circuit TST is
It becomes a high level like the power supply voltage of a circuit. Output signal T
Similarly, the high level of E is output from the data input/output circuit IOC via the data output terminal Dout.

In other words, the dynamic type RA of this embodiment
In M, by monitoring the output signal TE of the test circuit TST output from the data output terminal Dout, the n+ signal connected to the selected word line of the memory array ARY0 is
Read data of one memory cell and memory array AR
It can be determined for each word line whether all the read data of the n+1 memory cells coupled to the selected word line of Y1 match. In addition, since the comparison and verification of these read data is performed independently for each bit line, it is possible to write any test data to the memory cells that make up each memory array, and it is also possible to add a large amount of hardware. does not require. As a result, it is possible to reduce the number of testing steps for dynamic RAMs and the like, thereby promoting cost reduction, and also to increase the failure detection rate in functional tests, thereby increasing the reliability of dynamic RAMs and the like.

As shown in the above embodiment, by applying the present invention to a semiconductor memory device such as a dynamic RAM, the following effects can be obtained. That is,
(1) Divide a memory array such as a dynamic RAM into at least two parts, activate these memory arrays simultaneously in a predetermined test mode, and activate multiple memory arrays connected to selected word lines of each memory array. By providing a test circuit that simultaneously compares and matches the stored data read from memory cells to the corresponding bit lines for each bit line and word line, it is possible to suppress the increase in the amount of hardware while also being subject to test data constraints. The effect is that functional tests of a plurality of memory arrays forming a pair can be performed simultaneously and word line by word line without any problem. (2) According to the above item (1), it is possible to reduce the number of man-hours required for testing dynamic RAM and the like, thereby promoting cost reduction. (3) Item (1) above provides the effect of increasing the failure detection rate in functional tests and increasing the reliability of dynamic RAMs and the like.

[0031] Above, the invention made by the present inventor has been specifically explained based on examples. However, this invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. It goes without saying that there is. For example, in FIG. 1, memory arrays ARY0 and ARY1
may be activated simultaneously in normal write and read modes. Further, the number of memory arrays configuring the dynamic RAM may be three or more. In this case, storage data read from a plurality of memory cells coupled to selected word lines of three or more memory arrays may be compared and verified all at once, or two memory arrays may be configured in pairs and paired. The above-described comparison and verification operation of stored data can be performed simultaneously or selectively in each of the memory arrays. The output signal TE of the test circuit TST may be output from an external terminal exclusively for testing, or may be output from a pad to the test device without going through an external terminal. Dynamic RAM
may adopt an address non-multiplex method in which the X address signal and Y address signal are output from separate external terminals, or may adopt a direct sense method in which common data lines for writing and reading are provided separately. You can also do that.

In FIG. 2, unit test circuits UTC0 to UTCn constituting test circuit TST can be replaced with exclusive OR circuits consisting of ordinary logic gates. In this case, the level determination node may be selectively set to a low level by the output signal of the exclusive OR circuit. For example, the error detection circuit EDC of the test circuit TST is shown in FIG.
As shown in FIG. 2, a P-channel MOSFET Q9 precharges the level judgment node TP when the internal control signal TM is set to a low level, and its input terminal is coupled to the level judgment node TP, and its output signal is sent to the test circuit TS.
It may also be configured with a CMOS inverter N3 which serves as the output signal TE of T.

Furthermore, the output signal TE of the test circuit TST
The logic level of each internal control signal is not limited by these embodiments, and may vary depending on the block configuration of the dynamic RAM, the specific circuit configuration of the test circuit TST, the polarity of the power supply voltage, the conductivity type of the MOSFET, etc. Embodiments can be adopted.

In the above explanation, the invention made by the present inventor was mainly applied to a dynamic RAM, which is the field of application that formed the background of the invention.
The present invention is not limited thereto, and can be applied to various memory integrated circuits mounted on static RAM, high-speed logic integrated circuit devices, etc., for example. The present invention can be widely applied to semiconductor memory devices that include at least word lines and bit lines, and digital integrated circuit devices that include such semiconductor memory devices.

[0035]

Effects of the Invention: A memory array such as a dynamic RAM is divided into at least two parts, these memory arrays are simultaneously activated in a predetermined test mode, and the memory arrays are connected to a selected word line of each memory array. By providing a test circuit that simultaneously compares and matches the stored data read out from multiple memory cells to the corresponding bit lines for each bit line and word line, it is possible to suppress the increase in hardware amount while also limiting the amount of test data. A dynamic R
A test method such as AM can be realized. As a result, it is possible to reduce the number of man-hours required for testing dynamic RAMs and the like, thereby promoting cost reduction, and to increase the failure detection rate in functional tests, thereby increasing the reliability of dynamic RAMs and the like.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a dynamic RAM to which the present invention is applied.

FIG. 2 is a partial circuit diagram showing an embodiment of a test circuit included in the dynamic RAM of FIG. 1 and its peripheral parts;

FIG. 3 is a circuit diagram showing another embodiment of the test circuit included in the dynamic RAM of FIG. 1;

[Explanation of symbols]

DRAM...Dynamic RAM, ARY0~AR
Y1...Memory array, TST...Test circuit, X
D0~XD1...X address decoder, XAB...
X address buffer, SA0-SA1...Sense amplifier, CS0-CS1...Column switch, YD0-Y
D1...Y address decoder, YAB...Y address buffer, IOC...data input/output circuit, TG...
・Timing generation circuit. USA0~USAn...Unit amplifier circuit, UTC0~U
TCn...unit test circuit, EDC...error detection circuit. T1-T2...NPN type bipolar transistor, Q
1~Q10...P channel MOSFET, Q11~
Q24...N-channel MOSFET, R1 to R3.
...Resistance, N1-N3...CMOS inverter.

Claims (4)

[Claims] 1. A plurality of memory arrays that are simultaneously activated in a predetermined test mode, and storage data that is read to a corresponding bit line from a plurality of memory cells coupled to a selected word line of the plurality of memory arrays. 1. A semiconductor memory device comprising: a test circuit that compares and verifies each bit line by bit line. 2. The test mode is performed on a word line basis, and the test circuit detects corresponding bits from a plurality of memory cells coupled to a selected word line of the plurality of memory arrays. When the stored data read out to the lines matches on all bit lines,
2. The semiconductor memory device according to claim 1, wherein the output signal is selectively enabled or disabled. 3. The test circuit is provided corresponding to two memory arrays forming a pair and is placed between these memory arrays, and the test circuit comprises:
a plurality of unit test circuits provided corresponding to each bit line of two memory arrays forming a pair and provided in parallel between a level judgment node and a first power supply voltage; and an error detection circuit that identifies errors in a plurality of read stored data by determining, and each of the unit test circuits is configured to detect errors between the level determination node and the first power supply voltage. a first MOSFET of a first conductivity type, which is provided in series in series and whose gate is coupled to a non-inverted signal line of a corresponding bit line of one of the paired memory arrays; a second MOSFE of a second conductivity type coupled to a non-inverted signal line of a corresponding bit line;
T, and a first conductivity type which is provided in series between the level determination node and the first power supply voltage, and whose gate is coupled to the inverted signal line of the corresponding bit line of one of the paired memory arrays. 2. The method according to claim 1, further comprising a third MOSFET and a fourth MOSFET of the second conductivity type, the gate of which is coupled to the inverted signal line of the corresponding bit line of the other paired memory array. Claim 2
semiconductor storage device. 4. The semiconductor memory device is a dynamic RAM, and the test mode is performed by writing arbitrary storage data for each bit line into a plurality of memory cells connected to the same word line. 4. The semiconductor memory device according to claim 1, 2 or 3, wherein the semiconductor memory device is a semiconductor memory device.