JPH04351792A - Nonvolatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To prevent erroneous write in and erroneous erasure of nonselection memory transistors. CONSTITUTION:A memory cell array 800 is configured by memory array configuration groups arranged in a matrix from and each memory array configuration group is selected by plural memory transistors QM1,1 to QM2,6 and first selection transistors QS1,1 to QS2,6 which are connected to the memory transistors in parallel. Each memory array configuration group is connected to bit lines through second selection transistors QC1 to QC4 and the second selection transistors are selected by selection lines C1 to C2. During a write in and a read out period, a memory transistor which is the same memory array configuration group is selected by first word lines X1 to X6 and the first selection transistors which make pairs with the selected memory transistors are turned off by second word lines Z1 to Z6. Since the first selection tracsistors, which are paried with the other nonselection memory transistors, are turned on, these first selection transistors act as trnasfer gates and prevent erroneous write in and erroneous erasure of nonselection memory transistors.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and more particularly to an electrically erasable programmable read-only memory that can electrically erase data stored in a memory transistor and write new data. The present invention relates to a device (hereinafter referred to as EEPROM).

0002

2. Description of the Related Art Various types of nonvolatile semiconductor memory devices have been researched and developed that do not lose written data even when the power is turned off. In particular, the development of EEPROMs has progressed rapidly in recent years, and various products have been put into practical use.

[0003] EEPROMs have various structures, and in recent years, one constructed by connecting memory transistors in series has been proposed (R. Shirota et al., Tec.
hnical digest of 1988
symposium on VLSI tec
hnology P33-P34).

FIG. 12 is an equivalent circuit diagram showing an example of a conventional nonvolatile semiconductor memory device. First, the conventional example shown in FIG. 12 will be explained. Sign Qsi,j (i=1~2,j
=1 to 4) are selection transistors, symbols QMi,j(i
=1-2, j=1-6) are memory transistors. Memory transistor QMi,j (i=1~2, j=1~
6) control gate electrode is connected to the word line Xi (i=1
~6). selection transistor Qsi,
j (i=1 to 2, j=1 to 4), the first selection transistor group (
Qs1,1, Qs1,3, Qs2,1, Qs2, in the figure
The gate electrodes of 3) are connected to the first Z1 and Z3, respectively, and the second selection transistor group (Qs1, 2, Qs14, Qs in the figure) is connected to the source line S.
The gate electrodes of Qs2, 2, Qs2, and 4) are connected to second selection lines Z2 and Z4, respectively.

[0005] Each of the first selection transistors Qs1, 2~
Qs2,3 and three memory transistors QM1,1~
QM1, 3, QM1, 4 ~ QM1, 6, QM2, 1 ~ Q
M2,3, QM2,3 to QM2,4 and each second selection transistor Qs1,2 to Qs2,4 form a set, and each set is hereinafter referred to as a memory array configuration group. Bit line Y1
, Y2 and the source line S, and the bit lines Y1, Y2 are connected to the drain electrodes of the first selection transistors Qs1,1 to Qs2,3 of the memory array configuration group.

FIG. 13 is a plan view of each memory array configuration group formed between the bit line Y1 (Y2) and the source line S in the conventional example, and FIG. 14 is a plan view along the line AA' in FIG. FIG.

In FIGS. 13 and 14, 21 is a semiconductor substrate, 22a is a first selection transistor Qs1,1 (Qs
1, 3 to Qs2, 3), and 22b is the second selection transistor Qs1, 2 (Qs1, 4 to Qs2,
4) source region; 22c is an impurity diffusion layer region connecting each transistor in series; 23a and 23b are first and second source regions;
4 is the gate insulating film of the selection transistor Qs1,1, Qs1,2, and 4 is the memory transistor QM1,1 (QM1,
2 to QM2, 6), 25 is the second gate insulating film of memory transistor QM1, 1 (QM1, 2 to QM2, 6), and 26 is memory transistor QM1, 1.
(QM1, 2 to QM2, 6) floating gate electrodes, 27 is a memory transistor QM1, 1 (QM1, 2 to QM2,
6) control gate electrodes, 28a, 28b are gate electrodes of selection transistors Qs1, 1, Qs1, 2, 29 is an interlayer insulating film, 30 is a contact hole, 31 is a bit line Y1 (
This is the metal wiring that constitutes Y2).

The structural feature of this nonvolatile semiconductor memory device is that the first gate insulating film 24 of the memory transistor QM1,1 is as thin as, for example, 90 angstroms, and the first gate insulating film 24 of the memory transistor QM1,1 is thin, for example, between the floating gate electrode 26 and the semiconductor substrate 21 and between the floating gate electrode 26.
and tunneling between the source and drain electrodes easily occurs. Therefore, this conventional example performs electrical writing and erasing using this operating principle (tunneling).

Next, the operation of this nonvolatile semiconductor is shown in FIG.
Predetermined memory array configuration groups Qs1,1, QM1,1 in
, QM1,2, QM1,3, Qs1,2 will be explained. Note that each transistor is an N-channel transistor. Table 1 shows the potentials of the bit line Y1, first and second selection lines Z1 and Z2, and word lines X1, X2, and X3 in each mode of data erase, data write, and data read in this case. The unit of all numerical values in the table is volt (V).

0010

[Table 1]

In the following explanation, erasing data refers to injecting electrons into the floating gate electrode, while writing data refers to extracting electrons from the floating gate electrode.

First, the mode for erasing data will be explained. First, the bit line Y1 and the source line S are set to ground potential, and the word lines X1, X2, and X3 are set to a positive high voltage, for example, 1
Set to 7V. Since the first and second selection lines were set to 5V, each memory transistor QM1,1, QM1,2,
The channel potential of QM1 and QM3 and the potential of the source and drain electrodes are fixed to 0V. At this time, due to the positive high voltage applied to the control gate electrode 27 of each memory transistor QM1, 1, QM1, 2, QM1, 3, the electric field in the first gate insulating film 24 becomes strong, and the F-N electron tunnels. When the phenomenon occurs, the semiconductor substrate 21 and the impurity diffusion layer 22c
from the floating gate electrode 2 via the first gate insulating film 24.
6, each memory transistor QM1,1
, QM1, 2, QM1, 3 increase. This state is a state in which data has been erased. In this erase mode, there is no selectivity of memory transistors, so data stored in all memory transistors is erased at the same time.

Next, data is transferred to memory transistor QM1.
, 1, QM1, 2, and QM1, 3 modes will be explained. Bit line Y1, first selection line Z1 and memory transistors QM1, 1, QM1, 2 to be written
, QM1, QM3, the word lines X1, X2, X3 of the memory transistors connected to the bit line Y1 side are set to a positive high voltage, for example, 20V. At the same time, memory transistors QM1, 1, QM1, 2, QM1 to be written
, 3 and the word lines X1, X of the memory transistors connected to the source line S side than the memory transistors.
2, X3 and the source line S are set to ground potential. At this time, the control gate electrode 27 of the memory transistor to be written is at ground potential, and the drain electrode of the memory transistor is at a positive high potential of 20V, so the first gate insulating film 24 of the memory transistor to be written is strong. When an electric field is applied, electrons are emitted from the floating gate electrode 26 of the memory transistor to be written toward the impurity diffusion layer 22c due to the FN electron tunneling phenomenon. At this time, the memory transistor to which a high voltage is applied to the control gate electrode 27 and the drain electrode functions only as a transfer transistor, but since the electric field of the first gate insulating film 24 of the memory transistor in this bias state is small, the F-N electron No tunnel phenomenon occurs.

Furthermore, in a memory transistor connected to the source line S rather than the memory transistor to be written to,
Although the potential of the control gate 27 becomes the ground potential, it does not become high because the drain electrode potential is blocked by the memory transistor to be written. As a result, the electric field in the first gate insulating film 24 becomes small and no FN electron tunneling phenomenon occurs. This accomplishes selective writing to the memory transistors.

When a plurality of memory transistors are to be written, writing is sequentially performed from the memory transistors on the source side S to the plurality of memory transistors connected to one selection transistor Qs1,1 using the above-described method. This is to protect written data due to electric field stress during writing to the memory transistor, that is, to prevent threshold voltage fluctuation.

Incidentally, when writing this data, the second selection line Z2 connected to the gate electrodes of the second selection transistors Qs1 and Qs2 must be held at 0V. This means that the control gate electrode potential of the memory transistor is 0V.
However, in the case of a memory transistor that has already been written, a channel current flows, so the purpose is to cut off this channel current.

Next, the case of reading data stored in the memory transistor will be explained. In this mode, the bit line Y1 is set to 1V, the first and second selection lines Z1,
Fix Z2 to 5V. Furthermore, only the word lines X1, X2, and X3 connected to the memory transistors to be read are set to the ground potential, and all other word lines are set to 5V. If the memory transistor selected at this time is in the erased state, no current flows from the bit line Y1 to the source line S because the threshold voltage is positive. On the other hand, when the selected memory transistor is in the write state, current flows from the bit line Y1 to the source line S because the threshold voltage is negative. All other unselected memory transistors act as transfer gates. In this mode of operation, the threshold value of each memory transistor must be controlled to a control gate voltage, for example, 5V or less.

Next, the four memory array configuration groups in FIG.
, 6, QM2, and 6, the bias states of the four memory array configuration groups in the write state will be explained. At this time, each bit line Y1, Y2, each word line X3, X6, the first
, the potentials of the second selection lines Z1 to Z4 are shown in Table 2.

[0019]

[Table 2]

The unit of the numerical values in Table 2 is volt (V).

Now, memory transistors QM1, QM3 and Q
Control gate electrodes 27 of M2, 3 are connected to the same word line X3, and control gate electrodes 27 of memory transistors QM1, 6 and QM2, 6 are also connected to the same word line X6. Therefore, memory transistors QM1, 3 and QM2, 3 and memory transistors QM1, 6 and QM2
, 6 is performed by controlling the potentials of the bit lines Y1 and Y2.

Now, consider a case where memory transistors QM1 and QM3 are used for writing, while memory transistors QM2 and QM3 are not used for writing. At this time, memory transistors QM1 and QM3 are in the write bias state described above, but
Since it is not desired to write to the memory transistors QM2 and QM3, the bit line Y2 is kept at an intermediate potential of 10V. As a result, the bias state of the memory transistors QM2 and QM3 is such that 0V is applied to the control gate electrode and 10V is applied to the drain electrode.

The bias state of the memory transistors QM1 and QM3 is 0V on the control gate electrode and 20V on the drain electrode.
is applied, while memory transistor QM2
, 3 are as low as 10V, the electric field applied to the first gate insulating film is smaller in the memory transistors QM2, QM3 than in the memory transistors QM1, QM3. Therefore, memory transistors QM2 and QM3 do not cause FN electron tunneling, and memory transistors QM2 and QM3 do not cause FN electron tunneling.
No erroneous writing occurs in 2 and 3.

Note that the memory transistors QM2,1 and QM
2 and 2 are in a bias state in which 20 V is applied to the control gate electrode and 10 V is applied to the drain electrode, respectively. Since this state is also smaller than the potential difference applied between the control gate electrode and the drain electrode in erase mode, the F-N electron tunneling phenomenon does not occur, and erasing of unselected memory transistors on non-written bit lines during writing is possible. It doesn't happen.

Memory transistors QM1, 6, QM2,
6, the word line X6 is biased to 0V, and the drain electrode and the gate electrode are connected to the first selection line Z
The first selection transistors Qs1, 3, Qs2, 3 fixed at 0V by
2, no electric field stress is applied and erroneous erasing and erroneous writing do not occur.

As is clear from the above description, the memory transistors QM1,1 to QM1, which share the word lines X1 to X6,
To prevent erroneous writing to QM2 and QM6, an intermediate potential such as 10V is required, for example. Note that if you try to control the bit line with only two voltage values, for example 0V and 20V, without using this intermediate potential, it is possible to prevent erroneous writes to the memory transistors that share the word line, but the non-written bits during writing It is not possible to prevent the progress of erroneous erasure of unselected memory transistors connected to the line. In other words,
This causes an unintentional increase in the threshold of unselected memory transistors connected to non-write bit lines. This phenomenon is particularly noticeable in memory transistors close to bit lines, and becomes a problem as the number of memory transistors connected in series increases, as the number of times of erasing during writing increases. For example, if the threshold value of the non-write transistor becomes higher than the voltage applied to the control gate electrode during reading, this problem will result in erroneous reading of data, resulting in a fatal defect.

From the above explanation, the conventional nonvolatile memory transistor (1) utilizes the FN electron tunneling phenomenon during both erasing and writing. (2) In addition to the memory transistor, two selection transistors are connected in series between the bit line and the source line. (3) To prevent unintentional erasure of non-selected transistors during writing, three voltages, high, medium, and low, are used for the bit line bias. It has the following characteristics.

[0028]

[Problems to be Solved by the Invention] However, as mentioned above, conventional nonvolatile memory devices require three types of bit line bias potentials for selective writing: an intermediate potential, high and low potentials, and three types of bit line bias potentials. Since the F-N electron tunneling is controlled by the potential difference, there is a drawback that the setting range of each voltage is narrow. In particular, it is difficult to control the voltage setting of the intermediate potential, since either high or low voltage settings can cause defects.

Furthermore, conventional nonvolatile memory devices have the problem of over-erasing, that is, the threshold voltage of the memory transistor rises above the control gate voltage during reading, and in order to prevent over-erasing, However, these methods require precise setting and control of the erase voltage, which also has the disadvantage of imposing restrictions on the method of manufacturing the memory transistor and lowering the manufacturing yield.

Furthermore, since the FN tunneling phenomenon is used for both writing and erasing into the memory cell, a high positive voltage is required to execute the write/erase mode. For this reason, there is a drawback that it is necessary to use high breakdown voltage transistors using high breakdown voltage junctions as the bit line control transistor and the word line control transistor.

Furthermore, since writing and erasing into the memory transistor utilizes only the F-N tunneling phenomenon, the first gate insulating film 24 must be an extremely thin silicon oxide film of, for example, 100 angstroms or less. However, it is difficult to control the thickness and quality of the insulating film, which also has the disadvantage of lowering manufacturing yield.

Furthermore, since writing to the memory cell can only be performed serially from the source line S side, it is necessary to erase the memory cell once before reprogramming. This means that functions such as word erasing and word writing cannot be realized, and reprogramming takes a long time.Even if it is used as a large-capacity nonvolatile memory, its uses are extremely limited. have.

The present invention has been made in view of the above problems, and does not require an intermediate potential in selective writing, can perform writing at a relatively low voltage, and does not cause the problems of overwriting and overerasing. , a nonvolatile semiconductor memory device suitable for high integration, which has a wide voltage margin for writing and erasing, allows the first gate insulating film to be made thick, and can realize word writing and word erasing functions. is intended to provide.

[0034]

[Means for Solving the Problems] The gist of the present invention is to connect a plurality of transistor pairs in series, each consisting of a memory transistor having a floating gate and a control gate, and a first selection transistor connected in parallel with the memory transistor. a memory array in which memory array configuration groups arranged in rows and columns; a first word line commonly connected to control gates of memory transistors each arranged at the same row direction position; A plurality of second word lines are provided corresponding to the plurality of columns of the memory array, and a plurality of second word lines are connected in common to the gates of the first selection transistors, which correspond to the respective lines and are arranged at the same row direction position. a plurality of second selection transistors connected between the plurality of bit lines and one end of the memory array configuration group;
a plurality of selection lines provided corresponding to the plurality of rows of the memory array and connected to the gates of second selection transistors of the memory array configuration groups each belonging to the same row; and a plurality of selection lines other than the plurality of memory array configuration groups It also has a source line connected to the end.

[0035]

[Operation of the invention] When writing to or reading from a memory cell transistor, the first selection transistor that forms a pair with the selected memory transistor is turned off, and all the first selection transistors that form a pair with non-selected memory transistors are turned on. , functions as a transfer gate.

[0036]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a plan view showing a first embodiment of a nonvolatile semiconductor memory device of the present invention, and FIGS. 2 and 3 are AA' and BB in FIG.
' FIG. Figures 4 to 7 are also Figure 2 to
These are cross-sectional views similar to those shown in FIG.
Sections are taken along DD', EE', and FF'.

In the figure, 1 is a P-type semiconductor substrate of, for example, 13 Ωcm, and 2a, 2b, and 2c are N-type semiconductor substrates such as AS, for example.
A first impurity diffusion layer 3 doped with a type impurity is, for example, a gate insulating film of a first selection MOS type transistor made of a silicon oxide film with a thickness of 300 angstroms, and 4 is a gate insulating film of a first selection MOS type transistor, for example, P (phosphorous) or the like. The gate electrode of a first selection MOS transistor with a thickness of 3000 angstroms is made of polycrystalline silicon containing impurities, and 5 is a second selection MOS transistor made of a silicon oxide film with a thickness of 300 angstroms. 6 is a gate electrode of a second selection MOS transistor with a thickness of 3000 angstroms made of polycrystalline silicon containing impurities such as P (phosphorous), and 7 is a gate insulating film made of, for example, chemical vapor deposition. Thickness 2500 mm formed by method
8a is an impurity diffusion layer of the first selection transistor with a thickness of 500 angstroms and is made of N-type polycrystalline silicon containing a high concentration of, for example, AS; 8b is an impurity diffusion layer of, for example, B This is a channel region of a first selection transistor having a thickness of 500 angstroms and made of P-type polycrystalline silicon containing boron (boron) or the like at a high concentration of 3×10 16 cm −3 .

9 is a first gate insulating film of a memory transistor made of a silicon oxide film with a thickness of 120 angstroms, and 10 is a memory transistor with a thickness of 2000 angstroms made of polycrystalline silicon containing impurities such as P (phosphorous). 11 is a second gate insulating film of a memory transistor made of a silicon oxide film with a thickness of 200 angstroms, and 12 is a floating gate electrode with a thickness of 3000 angstroms made of polycrystalline silicon containing impurities such as P (phosphorous). This is a control gate electrode for a memory transistor.

13 is a metal wiring interlayer film made of, for example, BPSG with a thickness of 1.0 μm, which insulates the metal wiring and each part; 14 is a contact hole formed in the interlayer film 13;
For example, metal wiring made of Al etc. with a thickness of 1.0 μm,
16 is a field insulating film made of, for example, a silicon oxide film with a thickness of 6000 angstroms, and 17 is, for example, an AS film.
etc. to a high concentration of 1020 cm-2 to a thickness of 5
This is polycrystalline silicon grown to a thickness of 1,000 angstroms and buried between memory transistors.

Now, the gate electrode 6 of the second selection MOS transistor is connected row by row in the cell array as shown in FIG. 1, and serves as a selection line.
In the cell array, the gate electrodes 4 of the OS type transistors are connected row by row, as also shown in FIG. 1, and serve as second word lines.

In the cell array, the control gate electrodes 12 are connected row by row to form first word lines, as shown in FIG. It is separated for each.

In this embodiment, in addition to a second selection MOS transistor provided on the semiconductor substrate 1 and a plurality of memory transistors connected in series to the second selection MOS transistor, A first selection MOS type transistor is connected in parallel with each of the memory transistors. Moreover, in order to prevent an increase in the planar cell occupation area, the first selection MOS transistor is stacked above the memory transistor, and is made of polycrystalline silicon to prevent voids between cells at the time of high integration. A film 17 is provided along the impurity diffusion layer 8a of the first selection MOS transistor so as to fill the gaps between the cells.

Therefore, in this embodiment, the first selection MOS transistor 100 includes a source/drain region (hereinafter referred to as 8a) consisting of an impurity diffusion layer 8a on an insulating film, a polycrystalline silicon film 17, and a channel. area 8b,
It consists of a gate insulating film 3 above the channel region 8b and a gate electrode 4 on the gate insulating film 3.
Drain region 8a and channel region 8b are insulated and separated for each column. MOS transistor 11 for second selection
A contact hole 14 is formed in the drain region 2a of a series transistor group consisting of memory transistors 0 and a plurality of memory transistors, and a metal wiring 15 serving as a bit line is connected to the drain region 2a. Further, the source electrodes of the series transistor groups are commonly connected in each group and constitute a source diffusion layer wiring 2b.

Next, the operation of this embodiment will be explained using the equivalent circuit diagram shown in FIG. Sign Qsi,j (i=1~2,j
=1 to 6) are the first selection transistors, and have the symbol Q
Mi,j (i=1-2, j=1-6) is a memory transistor. The memory transistor QMi,j and the first selection transistor Qsi,j each form a pair, and three of these pairs are connected in series, for example, QM1,1
,QM1,2,QM1,3 and Qs1,1,Qs1,2,
Qs1 and Qs3 form one memory array configuration group. Memory cell array 800 is obtained by arranging this memory array configuration group in a matrix. In the plan view of FIG. 1, the layout is such that the source diffusion layer 2a and the bit line contact 14 are shared by two memory array configuration groups.

The control gate electrode 12 of the memory transistor QMi,j is connected to the first word line Xi (i=1 to
6), and the first selection transistor Qs
The gate electrodes 4 of i and j are connected to the second word line Zi(
i=1 to 6).

The drain electrodes 2a of the memory array configuration groups connected in series are connected to bit lines Yi (i=1 to 2) for each column.
On the other hand, the source electrodes 2b are commonly connected to the source line S. Furthermore, the gate electrodes 6 of the second selection transistors Qci (i=1 to 4) are connected to each other row by row, and are controlled by selection lines (Ci (i=1 to 2)).

Next, referring to Table 3, typical memory transistors QM1, 1, QM1 in write mode
,2,QM1,3,QM2,1,QM1,5,QM2,
An example of the bias potential of each word line, each bit line, each selection line, and source line when 5 is selected is shown. Note that the units of all numerical values in Table 3 are volts (V).

[0048]

[Table 3]

In the description of this embodiment, writing refers to increasing the threshold voltage of the memory transistor by injecting electrons into the floating gate electrode 10. Writing in this example uses hot electron injection using a channel current. For example, when writing to the memory transistor QM1,1, 6V is applied to the drain electrode of the memory transistor QM1,1 from the bit line Y1 via the second selection transistor Qc1, and the first voltage is applied to the control gate electrode. 10V is supplied from the word line X1.

On the other hand, this memory transistor QM1,1
Since 0V is supplied from the second word line Z1 to the gate electrode of the first selection transistor Qs1,1, which is paired with and connected in parallel, it is turned off. Therefore, the only path for the current caused by the voltage supplied from the bit line Y1 to the drain electrode is the path passing through the memory transistors QM1,1.

On the other hand, this memory transistor QM1,1
The control gate electrodes of the other memory transistors QM1, 2, QM1, 3 of the memory array configuration group to which the memory array structure group belongs are all fixed to 0V by the first word lines X2, X3. In addition, a first selection transistor Q arranged in parallel with these
10V is supplied from the second word lines Z2, Z3 to the gate electrodes of s1, 2, Qs1, 3, and these first selection transistors Qs1, 2, Qs1, 3 are turned on.

Therefore, the selected memory transistor Q
The source electrode of M1,1 is connected to these selection transistors Qs
The bit line Y1 is connected to the source line S at ground potential through the bit line Y1, Qs1, Qs1, and Qs1, and a channel current flows from the bit line Y1 to the source line S. As a result, hot electrons are generated in the channel portion of the memory transistor QM1,1, and electrons are injected into the floating gate electrode.

However, other memory transistors QM1, 2, QM1 in the same selected memory cell configuration group
, 3 are not written because the voltage supplied to the control gate electrode is 0V and there is almost no potential difference between the source and drain electrodes.

Similarly, when writing to the memory transistors QM1 and QM2, 10V is supplied from the selection line C1 to the gate electrode of the second selection transistor Qc1, and 6V is supplied from the bit line Y1 to the drain electrode. Other memory transistors QM1, 1, QM1 in the same memory array configuration group
, 3 are connected to the first word lines X1, X3.
0V from the other first selection transistor Qs
A second word line Z is connected to the gate electrodes of Qs1, 1, Qs1, 3.
1, Z3 from the first word line to the control gate of the selected memory transistor QM1, 2.
0V and this selected memory transistor QM
The first selection transistor Qs paired with 1 and 2
0V is supplied to the gate electrodes 1 and 2 from the second word line Z2.

In this way, the first selection transistor Qs1, 2 paired with the selected memory transistor QM1, 2 blocks the path bypassing this memory transistor QM1, 2, and Since the selection transistors Qs1,1, Qs1,1 form a path that bypasses the unselected memory transistors QM1,1, QM1,3, a channel current flows between the source and drain only in the selected memory transistors QM1,2. flows. In this way, hot electrons are generated in the channel portion and electrons are injected into the floating gates of the selected memory transistors QM1 and QM2. At this time, the first selection transistor Qs1
, 1, Qs1, 3 act as transfer gates between the bit line Y1 and the source line S.

In order to prevent erroneous writing and erasing of other memory array configuration groups connected to the same bit line Y1 represented by memory transistors QM1 and QM5, the memory transistors QM1 and QM5 are connected to other memory array configuration groups. First word line X4
~X6, second word lines Z4 to Z6, and selection line C2 are all fixed at 0V. Therefore, the memory transistor Q
No channel current is generated through M1,4, QM1,5, QM1,6, and no erroneous writing occurs.

Selective writing of memory transistors connected to the same word line, eg, QM1,1 and QM2,1, is realized by the bit line voltage. That is,
When writing to memory transistor QM2,1, by setting bit line Y1 to 0V, memory transistor Q
If the potential difference between the source and drain of M1, 1 is set to 0V, writing will not be performed. Note that even if the bit line Y1 is left open, no channel current flows, so no erroneous writing occurs.

Next, the erase mode will be explained. Table 4
, Table 5 shows examples of the potentials of each bit line, each word line, and source line in the erased state. All units in the table are volts (V)
It is. Erasing here refers to emitting electrons from the floating gate electrode to reduce the threshold voltage of the memory transistor.

Table 4 shows the case of erasing from the source line, and Table 5 shows the case of erasing from the bit line.

[0060]

[Table 4]

[0061]

[Table 5]

Erasing in this embodiment utilizes FN electron tunneling. That is, when a high voltage such as 20V is applied to the source/drain region or either one, and a low voltage of 0V is applied to the control gate electrode, the first This method utilizes the property that the electric field in the gate insulating film becomes strong, FN tunneling occurs through the first gate insulating film, and electrons are emitted.

Therefore, erasing is possible from both the bit line side and the source line side. First, the case of erasing from the source side will be explained.

In the case of batch erasing, there is no selectivity of memory transistors, and all first word lines X1 to X6 are set to 0V.
First, all second word lines Z1 to Z6 are set to 20V, and all selection lines C1 and C2 are set to 0V. At this time, all memory transistors QMi,j (i=1 to 2, j=1 to 6)
Since the impurity diffusion layer potential on the source line side and, incidentally, on the drain side becomes a high potential, electrons are emitted from the floating gate electrode and erased.

When selecting and erasing a word line, only the selected first word line is set to 0V, and all other first word lines are set to 0V.
and all second word lines to 20V. In addition, the selection lines C1 and C2 are set to 0V, and the bit lines Y1 and Y
Separate each memory array configuration group from 2. Since a high voltage of 20V is applied to the source line, as a result, the electric field between the floating gate electrode and the source/drain electrode becomes small except for the selected word line, so the F-N electron tunneling phenomenon does not occur. Therefore, it is not deleted. In this way, only the memory transistors connected to the selected first word line are erased.

On the other hand, when erasing is performed from the bit line side, the impurity diffusion layer to which the voltage is applied is simply switched from the source region to the drain region, and the other operations are the same as those described above.

FIG. 9 shows changes in the threshold voltage of memory transistor QMi,j in these write/erase modes. When writing is performed, the threshold voltage of the floating electrode increases due to electrons injected into the floating gate electrode. From this, for example, 0V is applied to the control gate electrode.
Even if is applied, no channel current flows.

On the other hand, when erasing is performed, the threshold voltage decreases as electrons are emitted from the floating gate electrode. Thereby, for example, a channel current flows even if 0V is applied to the control gate electrode.

FIG. 10 shows changes in the threshold voltage of memory transistor QMi,j over time. Note that although only an electrical method of erasing is described here, it may also be erased all at once by irradiating ultraviolet rays, for example. Next, the read mode will be explained with reference to Table 6. All units in the table are volts (V).

[0070]

[Table 6]

The following description will be made assuming that the memory transistors QM2,1 are accessed. The first word line X1 is connected to the control gate electrode of the selected memory transistor QM2,1.
0V is applied from the second word line Z1 to the gate electrode of the first selection transistor Qs2,1 paired with the memory transistor QM2,1. The channel of the first selection transistor Qs2,1 is turned off, leaving only the channel portion of the memory transistor QM2,1 as a current path.

This selected memory transistor QM2
, 1 belong to the memory array configuration group, the gate electrodes of the other first selection transistors Qs2, 2, Qs2, 3 are all set to 5V and turned on, and the memory transistor QM selected from the bit line Y2 as a transfer gate is turned on.
A current path to the drain electrode 2,1 and a current path from the selected memory transistor QM2,1 to the source line S are formed.

As a result, if the selected memory transistor QM2,1 is in the write state and the threshold voltage is 0V or higher, the potential of the control gate electrode of the selected memory transistor QM2,1 is 0V. , the current path from the bit line Y2 to the source line S is cut off by the memory transistor QM2,1, and no current flows.

Oppositely selected memory transistor QM
If 2,1 is in the erased state and the threshold voltage is 0V or less,
A current flows from the bit line Y2 to the source line S via the memory transistor QM2,1.

In this way, the erase and write states of the selected memory transistor correspond to the "presence" and "absence" of current from the bit line, respectively, and the presence or absence of this current is determined by the state connected to the bit line. By detecting with a sense amplifier or the like, it is determined whether the read data is "0" or "1".

Here, the control gate electrode of the unselected memory transistor may be at 0V or 5V. This is because this memory transistor does not need to function as a transfer gate due to the existence of the paired first selection transistor.

Furthermore, in this embodiment, the threshold voltage of the unselected memory transistor during reading may have any value for the same reason. In this way, if the threshold voltage of the first selection transistor is lower than the voltage applied to the second word line, the first selection transistor acts as a transfer gate and the read function of the device is performed. .

On the other hand, the first word line, second word line, and selection line of other memory array configuration groups to which the selected memory transistor does not belong are all fixed to 0V. Therefore, current paths from the bit lines Y1 and Y2 through these other memory array configuration groups are cut off. Therefore, even if the threshold voltages of all memory transistors in all memory array configuration groups are 0V or less, the operation is not affected.

In addition to the above-described read mode, in this embodiment, it is also possible to read out memory transistors connected to the same first word line in parallel. For example, to read memory transistors QM1,1 and QM2,1 simultaneously, bit line Y1 and bit line Y2 may be connected to separate sense amplifiers (not shown) and data may be output according to their respective currents.

By the way, the selection line has the following advantages. First, the parasitic leakage current flowing through the unselected memory transistor during writing is absorbed by the second selection transistor Q.
Since it can be blocked by ci, efficient writing becomes possible. As a result, it is possible to set a wide variation range of the threshold voltage of the memory transistor QMi,j during writing and erasing.

Second, since the impurity diffusion layer connected to the bit line Yi can be only the drain diffusion layer of the second selection transistor Qci of each memory array configuration group, the bit line capacitance can be reduced. Can be done.

FIG. 11 shows a second embodiment of the invention. FIG. 11 is a cross-sectional view of a portion corresponding to that shown in FIG. The difference from the first embodiment is that the first selection M
The channel portion 8a of the OS type transistor is present above the gate electrode 4 of the first selection MOS type transistor.

With this configuration, the electric field due to the high voltage applied to the control gate 12 of the memory transistor is prevented by the gate electrode 4 of the first selection MOS type transistor, and the channel voltage of the first selection transistor is increased. It has the advantage of being stable.

Other functions and driving methods are the same as in the first embodiment. Further, the other configurations are the same, and the same reference numerals as those given to the corresponding parts in the first embodiment are given, and the explanation thereof will be omitted.

[0085]

As explained above, in the present invention, a memory transistor and a first selection transistor are connected in parallel to form one pair, and a plurality of these pairs are further connected in series to form a memory array configuration group. A second selection transistor is provided between the pair of memory transistor and first selection transistor and the bit line.

Further, a first selection transistor is provided in a stacked manner on top of the memory transistor, and the first selection transistor is provided on the polycrystalline silicon which connects the first selection transistor in series. Source of transistor for
A polycrystalline silicon film containing a high concentration of impurity of the same conductivity type as the source/drain region of the first selection transistor is provided on the drain region, and each first selection transistor and second selection transistor are connected to each other. I try to embed it in between. Such a configuration brings about the effects described below.

(1) There is no need to set an intermediate potential during selective writing, and it is sufficient to set two voltage values. Therefore, designing of peripheral circuits and control circuits is easy. (2) Does not cause problems of overwriting and overerasing. This means that there is no upper or lower limit to the variation of the threshold voltage of the memory transistor. Therefore, the difference in threshold voltage fluctuation of the memory transistor during writing and erasing can be made large. Therefore, the design of the peripheral circuits, especially the write system control circuit, is simple and easy. Furthermore, even if there is a difference in write characteristics due to fluctuation factors during the manufacturing of memory transistors, the tolerance range is wide, resulting in a high manufacturing yield. (3) Hot electron injection can be used for writing. Therefore, the electric field in the first gate insulating film of the unselected memory transistor during writing can be made smaller than during erasing. Therefore, during writing, erroneous writing to unselected memory transistors connected to the same word line can be easily prevented. In addition, the threshold voltage of the memory transistor after writing can be determined by setting the voltage of the control gate electrode to a low voltage such as 0V, so that the voltage of the control gate electrode during writing is low and the voltage of the first word line is low. There is no need to use a high breakdown voltage transistor having a high breakdown voltage junction in the decoder to be driven, and the design of the decoder becomes easier. (4) Writing does not need to be performed by F-N electron tunneling, and erasing can also be performed by avalanche breakdown or ultraviolet irradiation in addition to F-N electron tunneling. It is also possible to use a relatively thick silicon oxide film, such as 130 angstroms, for the gate insulating film. Therefore, control during manufacturing of the first gate insulating film of the memory transistor is easy and the manufacturing yield is high. (5) Since the drain voltage during writing is low and the electric field in the first gate insulating film is weak, erroneous erasure during writing of already written data is less likely to occur. Therefore, there is no restriction on the writing order among the series-connected memory transistor groups. Therefore, designing of peripheral circuits is easy. (6) Word erasing and word writing are possible. In other words, only information on a specific word line can be rewritten. Therefore, it is possible to update the stored data without erasing all bits or writing all bits. This can significantly shorten the programming time and is suitable for program storage of accumulated data at any time. (7) Since the first selection transistor paired with each memory transistor is stacked above each memory transistor, the cell occupation area is the same as that of the conventional memory transistor. Further, since no selection transistor is required on the source side of each transistor group, the array area when forming a cell array is reduced. (8) Since the source and drain regions of the first selection transistor provided on the thin polycrystalline silicon film are buried with the polycrystalline silicon film, the first selection transistor is This has the advantage of preventing voids from forming in the source/drain regions.

In addition, electrically, since the distance between the first selection transistors is reduced, the parasitic resistance of the source and drain of the first selection transistors is also reduced.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing a first embodiment of the present invention.

FIG. 2 is a sectional view taken along line A-A' in FIG. 1;

FIG. 3 is a sectional view taken along line B-B' in FIG. 1;

FIG. 4 is a sectional view taken along line C-C' in FIG. 1;

FIG. 5 is a cross-sectional view taken along line D-D' in FIG. 1;

FIG. 6 is a sectional view taken along E-E' in FIG. 1;

FIG. 7 is a sectional view taken along line F-F' in FIG. 1;

FIG. 8 is an equivalent circuit diagram of the first embodiment of the present invention.

FIG. 9 is a graph showing voltage-current characteristics of the memory transistor according to the first embodiment of the present invention.

FIG. 10 is a graph showing programming characteristics of the memory transistor according to the first embodiment of the present invention.

FIG. 11 is a sectional view showing a second embodiment of the present invention.

FIG. 12 is an equivalent circuit diagram of a conventional nonvolatile semiconductor memory device.

FIG. 13 is a plan view of a conventional example.

FIG. 14 is a cross-sectional view of a conventional nonvolatile semiconductor memory device.

[Explanation of symbols]

QMi,j Memory transistor Qsi,j First selection transistor Qci Second selection transistor 1, 21 Semiconductor substrate 2a, 2b, 2c, 22a, 22b, 22c First impurity diffusion layer 3, 23a First selection Gate insulating film 4, 28a of MOS type transistor for first selection 6, 28b Gate electrode 5, 23b of MOS type transistor for second selection MOS type for second selection Gate insulating films 7 and 29 of the transistors Interlayer insulating films 8a and 8c Impurity diffusion layer 8b of the first selection MOS transistor Channel regions 9 and 24 of the first selection MOS transistor First gate of the memory MOS transistor Insulating films 10, 26 Floating gate electrodes 11, 25 Second gate insulating film 12, 27 of MOS transistor for memory Control gate electrode 13 Metal wiring interlayer film 14, 30 Contact hole 15, 31 Metal wiring 16 Field insulating film 17 Polycrystalline silicon membrane

Claims (3)

[Claims] 1. A memory array configuration group in which a plurality of transistor pairs each including a memory transistor having a floating gate and a control gate and a first selection transistor connected in parallel with the memory transistor are connected in series is arranged in a matrix. the arranged memory arrays, first word lines commonly connected to the control gates of the memory transistors arranged at the same row direction position, and the plurality of first word lines each corresponding to the plurality of first word lines, each of which is identical to the first word line. A plurality of second selection transistors commonly connected to the gates of the first selection transistors arranged in the row direction.
a plurality of bit lines provided corresponding to the plurality of columns of the memory array, and a plurality of second word lines connected between the plurality of bit lines and one end of the memory array configuration group.
a selection transistor, a plurality of selection lines connected to the gates of second selection transistors of the memory array configuration group, each of which is provided corresponding to a plurality of rows of the memory array and each belongs to the same row; A nonvolatile semiconductor memory device comprising a source line connected to the other end of a memory array configuration group. 2. Each of the memory transistors includes an impurity region formed in a semiconductor substrate, a first gate insulating film covering a surface of the semiconductor substrate, and the floating gate stacked on the first gate insulating film. The first selection transistor has a second gate insulating film provided on the floating gate and a control gate on the second gate insulating film, and the first selection transistor is provided in a semiconductor layer on an interlayer insulating film covering the control gate. 2. The nonvolatile semiconductor memory device according to claim 1, further comprising a channel region provided, a third gate insulating film on the channel region, and a gate electrode on the third gate insulating film. 3. Each of the memory transistors includes an impurity region formed in a semiconductor substrate, a first gate insulating film covering a surface of the semiconductor substrate, and the floating gate stacked on the first gate insulating film. The first selection transistor has a second gate insulating film provided on the floating gate and a control gate on the second gate insulating film, and the first selection transistor has a gate electrode on an interlayer insulating film covering the control gate. 2. The nonvolatile semiconductor memory device according to claim 1, further comprising: a third gate insulating film on the gate electrode; and a channel region provided in a semiconductor layer on the third gate insulating film.