JPH0435092B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a sync detector circuit that detects sync data supplied from the outside as a pulse train at regular intervals, and is particularly suitable for application to magnetic disk devices, etc. This paper relates to a sink/detector circuit.

[Prior art]

In general, in the case of MFM (double density) recording method, each sync field of each track on a magnetic disk contains 12 bytes of hexadecimal sync field "00".
Data has been written, and the sync data serially read out from each sync field becomes a pulse train at equal intervals. This sync data is mainly used for synchronizing the VFO (variable frequency oscillator) data separator circuit using the PLL (phase locked loop) circuit provided in the magnetic disk drive. ·data·
A sync detector circuit is provided to notify the separator circuit of the arrival of sync data.

[Problem that the invention seeks to solve]

By the way, the sink/detector circuit provided in a conventional magnetic disk device consists of a retriggerable monostable multivibrator configured with an IC circuit, an external capacitor that determines the output pulse width of this multivibrator, and an external capacitor that determines the output pulse width of this multivibrator. It consisted of resistance. In this case, the sync data is configured to be supplied to the trigger input terminal of the multivibrator, and after the multivibrator is triggered by the first pulse of the sync data, the sync data that arrives at regular intervals The values of the capacitors and resistors were determined so that they would be sequentially retriggered by the pulse train, and the arrival of sync data was detected based on whether the output of the multivibrator remained active for a predetermined period of time.
However, if the time constant determined by the values of the capacitor and resistor changes due to fluctuations in ambient temperature or changes over time, the above-mentioned sink data may not be detected reliably. There was a problem with lack of reliability.

In view of the above-mentioned circumstances, it is an object of the present invention to provide a highly reliable sink/detector circuit that is not affected by fluctuations in ambient temperature or changes over time.

[Means for solving problems]

The present invention provides a sync detector circuit for detecting whether serial data supplied from the outside is sync data consisting of a pulse train having a predetermined period and a predetermined number of pulses or more. clock pulse generating means for generating a reference clock pulse of 1, and outputting an active signal when each pulse of the serial data is supplied corresponding to each period in which the reference clock pulse is at the "H"level; a first logic circuit; a second logic circuit that outputs an active signal when each pulse of the serial data is supplied corresponding to each period in which the reference clock pulse is at the "L"level; said first or second
a counting means for counting the number of pulses of the reference clock pulse within a period during which an active signal is supplied from the logic circuit; and a determining means for determining whether the counting result of the counting means has reached a predetermined number. It is characterized by

[Effect]

During a period in which the pulse period of the serial data supplied from the outside matches the pulse period of the sync data, an active signal is supplied from the first logic circuit or the second logic circuit to the counting means, and this active signal The counting means counts the number of reference clock pulses during the period in which the reference clock pulse is supplied, thereby corresponding to the number of pulses in the serial data in the period in which the pulse period of the serial data matches the pulse period of the sync data. The value is counted. Then, when the number of pulses counted by the counting means reaches a predetermined number of pulses, this is determined by the determining means, and at this point, it is determined that the serial data supplied from the outside is sync data. Detected.

〔Example〕

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention applied to a soft selector type magnetic disk device.

In the figure, 1 is a clock pulse generation circuit that generates a clock pulse φ _{1 and} a clock pulse φ ₂ having the opposite phase to this clock pulse φ 1. In this embodiment, the clock pulse generation circuit 1 is also used when writing data to a magnetic disk. It is used as such. Therefore, the clock pulses φ ₁ , φ ₂
The period of is the same as the pulse period of the sync data written in the sync field of the magnetic disk. Clock pulses φ ₁ and φ ₂ generated by this clock pulse generating circuit 1 are respectively supplied to input terminals D of D-type flip-flops (hereinafter abbreviated as DFF) 2 and 3. Read data RD read from the magnetic disk is supplied to each clock terminal CK of DFF2 and DFF3. Also, the output of DFF2 is connected to the reset terminal R of DFF3.
The output of DFF3 is supplied to the reset terminal R of DFF2, and the output of DFF3 is supplied to the reset terminal R of DFF2.
Each Q output is supplied to one input terminal of an AND gate 5 and an edge detection circuit 6 via an OR gate 4. The edge detection circuit 6 detects the rising edge of the Q output of DFF2 or DFF3, and supplies a clear signal to the clear input terminal CLR of the asynchronous counter 7 at that point. The clock pulse _φ1 is supplied from the clock pulse generation circuit 1 to the other input terminal of the AND gate 5, and when the Q output of DFF2 or DFF3 becomes "H" level and the AND gate 5 becomes open, the clock pulse φ1 is supplied to the other input terminal of the AND gate 5. φ ₁ is supplied to the counter 7 via the AND gate 5. Counter 7 receives clock pulse φ ₁ supplied via AND gate 5.
The count value is supplied to the comparator 8. The comparator 8 compares the count value supplied from the counter 7 with a predetermined value set in advance, and outputs a match signal S when they match. In addition, 9 in the figure is DFF2 and 3
This is a pull-up resistor that supplies an "H" level signal to each set terminal S of.

Next, the operation of the sync detector circuit configured as described above will be explained with reference to FIG. Second
The diagram shows the track format of a magnetic disk,
The data patterns written in the Gap, Sync field, and AM (address mark) on the track, the read data RD using the MFM recording method shown corresponding to the data pattern, and the book. 3 is a timing chart showing the relationship between the waveforms of each part of the sync detector circuit of the embodiment. As shown in the figure, in the MFM recording method, a hexadecimal number "4E" is recorded in the gap, and a missing number is recorded at the beginning of the address mark.
Hexadecimal “A1” including the clock (indicated by M in the diagram)
is recorded. Also, in the figure, the symbol C written along the pulse train of read data RD
indicates a clock pulse, and symbol D indicates a data pulse.

First, in the initial state, the Q outputs of DFF2 and DFF3 are both at "L" level,
Further, the AND gate 5 is in a closed state, and furthermore, the count value of the counter 7 is cleared.
In this state, as shown in Figure 2, DFF2
The same DFF is output every period when the clock pulse _φ1 supplied to the input terminal D of
When each clock pulse C of the read data RD read from the sync field sequentially arrives at the clock terminal CK of DFF2, the Q output of DFF2 becomes "H" level continuously. In this case, DFF2
During the period when the output of DFF3 is at the "H" level, a "L" level signal is supplied from the output terminal of DFF2 to the reset terminal R of DFF3, so the operation of DFF3 is regulated and the Q output of DFF3 is is fixed at "L" level. and,
During the period when the Q output of DFF2 is at the "H" level, the "H" level Q output of this DFF2 is supplied to one input terminal of the AND gate 5 via the OR gate 4; The clock pulse φ ₁ supplied to the other input terminal of the counter 7 is sequentially supplied to the counter 7 . Then,
A counter 7 counts the number of clock pulses φ ₁ supplied via an AND gate 5 and sequentially supplies the count value to a comparator 8 .
Then, when the count value reaches a predetermined value, the comparator 8 outputs a coincidence signal S. Note that this coincidence signal S is used as a signal for controlling the synchronous operation of the VFO data separator circuit of the magnetic disk device.

Next, when the data pulse D of the first bit of the address mark is supplied to the clock terminal CK of DFF2, at this point, the "L" level clock pulse φ ₁ is supplied to the input terminal D of DFF2. The Q output of DFF2 becomes “L” level,
As a result, the AND gate 5 is closed and the clock pulse φ ₁ is no longer supplied to the counter 7.
Further, at the time when the Q output of the DFF 2 becomes "L" level, this falling edge is detected by the edge detection circuit 6, and the edge detection circuit 6 supplies a clear signal to the clear terminal CLR of the counter 7. As a result, the counter value of counter 7 is cleared.

The above operation is performed by transmitting the read data RD read from the sink field to the clock terminal CK of the DFF2 every period when the clock pulse _φ1 supplied to the input terminal D of the DFF2 is at the "H" level. This is the operation when each clock pulse C arrives sequentially, but when each clock pulse C of read data RD arrives sequentially with a half-cycle shift from clock pulse _φ1 , DFF3 performs the operation of DFF2 described above. It works exactly the same. Further, the counter 7 performs a counting operation even when read data RD other than the sync field is supplied to each clock terminal CK of DFF2 and DFF3. However, the read data RD read from a location other than the sync field does not form a pulse train of a predetermined number of equally spaced pulses like each clock pulse C of the sync field. It will be cleared before reaching a preset predetermined value. Therefore, by setting the predetermined value to an appropriate value, it is possible to prevent an equally spaced pulse train read from a location other than the sync field from being mistakenly detected as sync data.

According to the embodiment described above, unlike the conventional sink/detector circuit using a retriggerable monostable multivibrator, a CR time constant circuit consisting of a capacitor and a resistor is not used, and the circuit is configured only by a logic circuit. Therefore, it is not affected by changes in ambient temperature or changes over time, and the clock pulse generation circuit 1 used when writing data to a magnetic disk can also be used as a clock pulse generation means. , can be constructed easily and inexpensively.

〔Effect of the invention〕

As explained above, according to the present invention, there is provided a clock pulse generating means that generates a reference clock pulse having the same period as the sync data, and a clock pulse generating means that generates a reference clock pulse having the same period as the sync data, and a clock pulse generating means that generates a reference clock pulse having the same period as the sync data, and a clock pulse generating means that generates a reference clock pulse having the same period as the sync data, and a clock pulse generating means that generates a reference clock pulse having the same period as the sync data. The first outputs an active signal when each pulse of serial data is supplied externally.
logic circuit and the reference clock pulse is “L”.
a second logic circuit that outputs an active signal when each pulse of the serial data is supplied corresponding to each period of the serial data;
or a counting means for counting the number of the reference clock pulses within a period during which the active signal is supplied from the second logic circuit, and a determining means for determining whether the counting result of the counting means has reached a predetermined number. Since the
Compared to a conventional sink/detector circuit with a CR time constant circuit, it has the advantage of being unaffected by ambient temperature fluctuations and aging, resulting in stable operation and improved reliability. can get.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a timing chart for explaining the operation of the embodiment. 1...Clock pulse generation circuit, 2, 3...D
Type flip-flop, 4...or gate, 5...
AND gate, 6... edge detection circuit, 7... asynchronous counter, 8... comparator.

Claims (1)

[Claims] 1. In a sync detector circuit that detects whether serial data supplied from the outside is sync data consisting of a pulse train having a predetermined period and a predetermined number of pulses or more, a reference having the same period as the predetermined period is used. a clock pulse generating means for generating a clock pulse; and a first clock pulse generating means for outputting an active signal when each pulse of the serial data is supplied corresponding to each period in which the reference clock pulse is at the "H" level. a second logic circuit that outputs an active signal when each pulse of the serial data is supplied corresponding to each period in which the reference clock pulse is at the "L"level; counting means for counting the number of pulses of the reference clock pulse within a period during which the active signal is supplied from the first or second logic circuit; and a determination for determining whether the counting result of the counting means has reached a predetermined number. A sink/detector circuit comprising means.