JPH04348078A - Mos semiconductor device - Google Patents

Abstract

PURPOSE:To provide a MOS semiconductor device having a structure in which a MOS element can be integrated at high density by forming an SOI (silicon on insulator) structure. CONSTITUTION:An insulating film 2 is formed on a semiconductor substrate 1; a conductive layer 3 is formed on the insulating film 2, and it is used as a gate electrode. The surface and the side face of the conductive layer 3 as well as the insulating film 2 are covered with a dielectric film 4; in addition, a semiconductor layer 5 is formed on the dielectric film 4. The semiconductor layer 5 comprises the following: a first part 8 formed on the surface of the conductive layer 3; a second part 7 formed on the side face of the conductive layer 3; and a third part 9 formed in a part where the insulating film 2 is covered directly with the dielectric film 4. The first part 8 and the third part 9 constitute a source (or a drain), and the second part 7 constitutes a channel.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS type semiconductor device that can be integrated at high density.

0002

2. Description of the Related Art FIG. 8 is a schematic cross-sectional view of a planar MOS semiconductor device, which is one of the prior art. Traditional MO
In the S-type semiconductor device, as shown in FIG. 8, a dielectric film (silicon oxide film or CVD nitride film) 22 and a gate electrode 23 are provided on a semiconductor silicon substrate 21, and a source electrode 24 and a drain electrode 25 are formed using this as a mask. A planar type with a formed structure was common. In this structure, the effective channel length 26, which governs the electrical characteristics of the MOS semiconductor device, is determined by the finished dimensions of the gate electrode 23.

Furthermore, when a plurality of such MOS type semiconductor devices are formed, an element isolation field oxide film 28 is required to prevent electrical interaction between elements, and a set of these elements is required. is formed in the semiconductor silicon substrate 21 or well. Note that a high concentration layer 27 for preventing inversion is provided below the field oxide film 28.

In order to achieve high integration, a vertical MOS type semiconductor device formed in a trench on a silicon substrate has been proposed (Reference A COMPOSED TRE).
NCH TRANSISTOR (CTT)CELL
FOR 16/64MB dRAMS, VLSI S
ympo. '89, pp. 65-66). The basic structure of this type of semiconductor device is the same as that shown in FIG. 8, as a MOS type semiconductor device in which a source electrode and a drain electrode are formed in a semiconductor silicon substrate and are operated by a gate electrode above the source electrode and drain electrode. When a plurality of MOS type semiconductor devices are formed, a field oxide film structure for element isolation is also required as in the case of the planar type.

[0005]

[Problems to be Solved by the Invention] Conventionally, there has been a problem that the effective channel length 26, which governs the electrical characteristics of a MOS semiconductor device, is determined by the finished dimensions of the gate electrode and is greatly influenced by the precision of microfabrication. there were.

In addition, it is difficult to achieve high integration with planar MOS semiconductor devices, and to solve this problem, trench MOS semiconductor devices have been proposed in which the gate electrode, source electrode, and drain electrode are formed on the inner wall of the trench. The company had no choice but to adopt a complicated structure. Further, when a plurality of these elements are present, a field oxide film must be additionally formed to prevent electrical interaction between the elements. Furthermore, in a MOS type semiconductor device having a plurality of MOS transistors formed in the same semiconductor silicon substrate 21 or the same well, the base potential of each MOS transistor must be the same, and the There is a problem in that the base potentials cannot be selected independently, and there is little freedom in controlling electrical characteristics.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a MOS type semiconductor device in which MOS elements can be integrated at high density.

[0008]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a MOS type semiconductor device with a first insulating layer,
a first conductive layer formed on the first insulating layer and having an upper surface isolated from the first insulating layer and a side surface connecting the upper surface and the first insulating layer; a second insulating layer covering the upper and side surfaces of the layer and the first insulating layer; a first portion containing an impurity of a conductivity type different from that of the first portion, a second portion formed on a side surface of the first conductive layer and connected to the first portion and containing an impurity of a conductivity type different from that of the first portion; and a third portion that is formed where the second insulating layer directly covers the first insulating layer, continues to the second portion, and contains the same type of impurity as the first portion. and a semiconductor layer having the structure.

[0009]

[Operation] With the above structure, the present invention operates as follows. The MOS type semiconductor device of the present invention is an SOI (Sil
Since the device adopts an icon on insulator structure, elements can be easily separated. In other words, the semiconductor layer (polysilicon) that is finally formed can be separated into silicon islands using conventional microfabrication technology, and therefore the heat treatment required during the formation of the field oxide film, which was required in the conventional example for element isolation, can be eliminated. No longer needed. Therefore, there is no need to consider the problem of narrow channels caused by bird's beaks when forming a field oxide film. Further, since the MOS type semiconductor device of the present invention employs a vertical structure in which each element is arranged perpendicularly to the substrate, high density and high integration are possible. In addition, the semiconductor layer located on the side surface of the first gate electrode is
Since it is used as a channel of an OS type semiconductor device, the effective channel length is determined by the thickness of the first gate electrode. For this reason, compared to the electrical characteristics of conventional MOS semiconductor devices, which were controlled by the fine processing technology of the gate electrode, the MOS semiconductor device of the present invention allows for even more precise control of the characteristics. This structure is particularly effective for devices in which the dimensions of each element in the planar direction are minute, on the order of submicrons.

Further, a second dielectric layer is formed on the base electrode, a second gate electrode is formed on the second dielectric layer,
By controlling the potential, the potential of the base electrode can be controlled field-effectively.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic cross-sectional view of a semiconductor device in which a MOS field effect transistor is formed, which is an embodiment of the present invention. The base structure of the MOS type semiconductor device shown in FIG. 1 is such that an insulating film (first insulating layer) 2 is formed on a semiconductor silicon base (semiconductor base) 1. In this case, the insulating film 2
As for the thermal oxide film (SiO2
) or a vapor-grown oxide film (SiO2) is suitable, and its thickness is arbitrary from 0.1 .mu.m to several .mu.m. In order to reduce the wiring capacitance of the device formed on the insulating film 2 and increase the speed of the device, the thicker the insulating film 2 is, the more advantageous it is, and the lower the dielectric constant of the material, the lower the dielectric constant. The more preferable. However, since it is preferable to use a material that has thermal characteristics similar to each material of the MOS type semiconductor device formed thereon, a silicon oxide film is optimal.

When processing elements on the insulating film 2, if the thickness of the insulating film 2 is increased to have the same strength as the substrate 1, the semiconductor silicon substrate 1 is not required. Furthermore, it is also possible to adopt a multilayer element structure in which other electrical elements (for example, semiconductor devices, resistors, capacitors) are present under the insulating film 2, and these may be connected vertically.

As shown in FIG. 1, a first gate electrode (first conductive layer) 3 is provided on the above insulating film 2, and a first dielectric film (second conductive layer) is provided to cover the first gate electrode 3. An insulating layer) 4 and a semiconductor silicon layer (semiconductor layer) 5 are formed.

The first gate electrode 3 is made of Cr, Mo, W, Cu.
, Al, etc. are most preferred, and mixtures of these metal materials, high concentration N-type polysilicon, or high melting point metal silicides are also possible. It must be noted that when multiple layers of different metals are used, the work function changes in the vertical direction. The processed line width of the first gate electrode 3 may be submicron, and variations in processing do not affect the electrical characteristics of the present MOS type semiconductor device. First gate electrode 3
The film thickness is a dominant factor in determining the effective channel length 6 of the present MOS type semiconductor device, and this film thickness may be selected to be approximately 0.5 to 2 μm. If it is too thick, the layer formed in the subsequent processing step will be affected by a step difference, and if it is too thin, the present MOS semiconductor device will be affected by a short channel effect.

The first dielectric film 4 is suitably a silicon nitride film or a silicon oxide film grown in a vapor phase, and has a film thickness of 10 to several tens of nanometers.
Choose m.

The semiconductor silicon layer 5 has a thickness of 20 to 300 nm.
A polysilicon or epitaxial silicon thin film (by laser recrystallization or lateral epitaxial growth) with a thickness of . In the semiconductor silicon layer 5, a portion (first portion) 8 located on the upper surface of the first gate electrode 3 is a source (
The semiconductor silicon layer (second portion) 7, which constitutes the (or drain) electrode and is located on the side surface of the first gate electrode 3, is
type (or N type) impurity is thin (5×1015 to 1×
1017 cm-3) and constitutes the channel of the present MOS type semiconductor device.

Furthermore, a semiconductor silicon layer (third portion) 9 laminated on the insulating film 2 with the first dielectric film 4 interposed therebetween, that is, a portion of the semiconductor silicon layer 5 other than the portion facing the first gate electrode 3 is provided. The located portion constitutes the drain (or source) electrode. Both the first portion 8 and the third portion 9 are N-type (or P-type) heavily doped layers. To form the N-type (or P-type) impurity layer, a technique is used in which a sidewall mask is formed on the side surface of the first gate electrode outside the semiconductor silicon layer 5 by inclined ion implantation.

Although the above-mentioned extraction of each electrode is not shown in FIG. 1, it can be easily accomplished using conventional microfabrication techniques. Further, when it is necessary to separate each element, such as when a plurality of MOS type semiconductor devices are formed on the same insulating film, an isolation band 10 is provided. As a result, two MOS type semiconductor regions 33 and 35 are formed in FIG.

FIG. 2 is a plan view of the MOS type semiconductor device shown in FIG. 1, and FIGS. 3 and 4 are variations thereof. Figures 2 to 4
1, the same components as in FIG. 1 are given the same numbers. As shown in FIG. 2, the semiconductor elements 33 and 35 are separated by a separation band 10, and have a structure that looks like an island floating on a sea of insulating film 2. 3 and 4 show an embodiment for electrically connecting the semiconductor elements 33 and 35 shown in FIG. 2. In FIG. FIG. 3 shows each semiconductor element 33, 3.
This is an example in which the first gate electrodes 3 of No. 5 are electrically connected by a conductor 30. The conductor 30 is made of the same components as the first gate electrode 3, and is formed simultaneously with the first gate electrode 3 in the same process. FIG. 4 shows an example in which the third portions 9 constituting the drains (or sources) of both semiconductor elements 33 and 35 are extended to each other to form a connection region 90 and electrically connected. This connection region 90 is made of the same component as the drain (or source) 9, and is formed simultaneously with the drain (or source) 9 in the same process. In each figure, the base electrode 7 of the semiconductor element 33 is configured to be P type (or N type), the drain (or source) electrodes 8 and 9 are configured to be N type (or P type), and the semiconductor element 35 is configured in the opposite manner. A complementary MOS type semiconductor device can be obtained by configuring the polarity of , that is, the base electrode 7 is N type (or P type) and the drain (or source) electrodes 8 and 9 are P type (or N type). . Further, a first dielectric film 4 is interposed between the drain (or source) electrode 9 and the insulating film 2 due to the manufacturing process. This is not necessarily necessary in the relationship between 9 and the insulating film 2. Here, by overlapping the first dielectric film 4 with the insulating film 2,
The insulating layer is made thicker.

Next, a second embodiment of the present invention will be explained with reference to FIG. FIG. 5 shows a second embodiment of the present invention.
1 is a schematic cross-sectional view of an S-type semiconductor device. Its basic structure is the same as the MOS type semiconductor device shown in FIG. In the second embodiment, as shown in FIG. 5, a second dielectric film (third insulating layer) 11 and a second gate electrode (second conductive layer) 12 are further formed outside the channel 7. It has a structure. Second
The materials and film thicknesses of the dielectric film 11 and the second gate electrode 12 are the same as the first one.
This may be considered to be the same as the first dielectric film 4 and first gate electrode 3 in the embodiment. In this embodiment, by providing the second gate electrode 12, the potential of the channel 7 is controlled by the potential of the second gate electrode 12 in a field effect manner.

Next, a method for manufacturing the semiconductor device shown in FIG. 1 will be explained with reference to FIGS. 6 and 7. First, as shown in FIG. 6A, a SiO2 insulating film 2 is formed on a Si substrate 1 by heat treatment or chemical vapor deposition.
position (CVD) to a thickness of 0.1 μm. Next, LPCVD (low
pressure chemical vapor
thickness 0.5~2μ by deposition method
A polysilicon film of m is formed, and phosphorus P is thermally diffused to form an N-type polysilicon layer. This polysilicon layer is formed into a predetermined pattern by photolithographic etching to form the first gate electrode 3 as shown in FIG. 6(B).

Next, as shown in FIG. 6C, a layer of silicon nitride (Si3 N4) (first dielectric film 4) is formed to cover the first gate electrode 3 and the exposed portions of the insulating film 2. ) is formed to a thickness of 10 to several tens of nanometers by the LPCVD method.

Next, as shown in FIG. 6(D), a polysilicon or epitaxial silicon thin film 5 is grown to a thickness of 20 to 300 nm on the first dielectric film 4, and a P-type or N-type impurity is added to the film. ×1015~1×1017cm-
A semiconductor silicon layer 5 is formed by doping (ion implantation) to a concentration of 3. In this case, an inclined implantation method is used so that the implantation is performed into the semiconductor silicon layer 5 located on the side surface of the first gate electrode 3.

Next, as shown in FIG. 7A, SiO2 or Si3 is deposited on the semiconductor silicon layer 5 by the CVD method.
The N4 film 12 is formed to have a thickness of 200 to 500 nm, and the film 12 is subjected to RIE (reactive ion etc.).
As shown in FIG. 7B, only the portion 12d corresponding to the side surface of the electrode 3 is left and the other portions 12a, 12b, and 12c are removed by directional etching using the Hing method.

Using the film portion 12d as a mask, the semiconductor silicon layer 5 is doped with impurities of a different type (
A source (or drain) electrode 8 and an impurity adjacent to the gate electrode 3 are implanted at a high concentration using an inclined ion implantation method to form a source (or drain) electrode 8 in a portion located on the upper surface of the gate electrode 3, as shown in FIG. 7(C). A drain (or source) electrode 9 is formed in a portion located above the insulating film 2. A portion of the semiconductor silicon layer 5 corresponding to the side surface of the gate electrode 3 is not implanted with high concentration impurities and is used as the channel 7.

Note that a complementary MOS type semiconductor device can be manufactured by carrying out the above steps in the following manner. That is, FIG. 6(D) from the formation of the semiconductor silicon layer 5 to the formation of the source and drain electrodes.
In the steps from to FIG. 7C, first, the position of the semiconductor element 35 is masked, and the semiconductor element 33 is
P type (or N type) by performing the steps from D) to Figure 7(C)
drain (or source) electrodes 8, 9 and N type (or P
A base electrode 7 of the type (type) is formed. Then, the semiconductor element 33 side is masked, and the semiconductor element 35 is masked as shown in FIG.
) to FIG. 7C are performed to form N-type (or P-type) drain (or source) electrodes 8 and 9 and P-type (or N-type) base electrode 7.

[0027]

As described above, according to the present invention, it is possible to realize a MOS type semiconductor device with a simple structure and excellent controllability of electrical characteristics. In addition, since the structure allows for high density and high integration, and allows for easy isolation between elements, it can be expected to be used as a technology at the level of future 256 megabit DRAMs.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the structure of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a plan view of the semiconductor device shown in FIG. 1.

FIG. 3 is a modification of FIG. 2;

FIG. 4 is a modification of FIG. 2;

FIG. 5 is a cross-sectional view showing the structure of a semiconductor device showing a second embodiment of the present invention.

FIG. 6 is an explanatory diagram showing steps of the method for manufacturing the semiconductor device shown in FIG. 1;

7 is an explanatory diagram showing steps of the method for manufacturing the semiconductor device shown in FIG. 1. FIG.

FIG. 8 is a cross-sectional view showing an example of the structure of a conventional semiconductor device.

[Explanation of symbols]

1 Semiconductor substrate 2 Insulating film (first insulating layer) 3 First gate electrode (first conductive layer) 4
First dielectric film (second insulating layer) 5 Semiconductor silicon layer (semiconductor layer) 7 Channel (second part) 8 Source (or drain) electrode (first part) 9 Drain (or source) electrode (first part) 3) 11 Second dielectric film (third insulating layer) 12
Second gate electrode (second conductive layer) 30 Conductor (connection means) 33, 35 Semiconductor element 90 Connection region (connection means)

Claims (27)

[Claims] 1. A first insulating layer, a top surface formed on the first insulating layer and isolated from the first insulating layer, and a side surface connecting the top surface and the first insulating layer. a first conductive layer; a second insulating layer covering the top surface and side surfaces of the first conductive layer and the first insulating layer; A first portion formed on the top surface of the conductive layer and containing impurities of one conductivity type; and a first portion formed on the side surface of the first conductive layer and connected to the first portion. a second portion containing impurities of a different conductivity type, and a second insulating layer formed where the second insulating layer directly covers the first insulating layer;
a semiconductor layer having a third part that is continuous with the part and contains an impurity of the same type as the first part.
S-type semiconductor device. 2. The MOS type semiconductor device according to claim 1, further comprising a semiconductor substrate on which the first insulating layer is formed. 3. The MOS type semiconductor device according to claim 1, wherein the first conductive layer includes a semiconductor material containing a high concentration of impurities. 4. The MOS type semiconductor device according to claim 1, wherein the first conductive layer contains one or more metals selected from molybdenum, tungsten, chromium, copper, and tungsten. 5. The MOS type semiconductor device according to claim 1, wherein the first conductive layer contains metal silicide. 6. The MOS type semiconductor device according to claim 1, wherein the second insulating layer includes a silicon nitride film, a silicon oxide film, or a composite film thereof. 7. The MOS type semiconductor device according to claim 1, wherein the semiconductor layer has a P layer in a first portion, an N layer in a second portion, and a P layer in a third portion. 8. The MOS type semiconductor device according to claim 1, wherein the semiconductor layer has an N layer in a first part, a P layer in a second part, and an N layer in a third part. 9. The first portion of the semiconductor layer, the second portion of the semiconductor layer;
a third insulating layer covering the third insulating layer, and a second conductive layer mainly forming on the third insulating layer covering the second part of the semiconductor layer. MOS according to claim 1, further comprising:
type semiconductor device. 10. A first insulating layer, a plurality of layers selectively formed on the first insulating layer, each having an upper surface separated from the first insulating layer, and the upper surface and the first insulating layer. a first conductive layer having a side surface connecting the first conductive layer; a second insulating layer covering the upper surface and side surfaces of each of the first conductive layers and the periphery of the first insulating layer connected to the side surfaces; a first portion that covers a second insulating layer, is formed separately for each of the first conductive layers on the first insulating layer, and contains impurities of one conductivity type; a second portion that is formed on a side surface of the first conductive layer, is connected to the first portion, and contains an impurity of a conductivity type different from that of the first portion, and the second insulating layer is connected to the first portion. a MOS type semiconductor device, comprising: a third portion formed directly covering an insulating layer of the semiconductor layer, the third portion being continuous with the second portion and containing the same type of impurity as the first portion; 11. The MOS type semiconductor device according to claim 10, further comprising a semiconductor substrate on which the first insulating layer is formed. 12. Claim 1, wherein the first conductive layer includes a semiconductor material containing a high concentration of impurities.
MOS type semiconductor device according to 0. 13. The MOS type semiconductor device according to claim 10, wherein the first conductive layer contains one or more metals selected from molybdenum, tungsten, chromium, copper, and aluminum. 14. The MOS type semiconductor device according to claim 10, wherein the first conductive layer contains metal silicide. 15. The MOS type semiconductor device according to claim 10, wherein the second insulating layer includes a silicon nitride film, a silicon oxide film, or a composite film thereof. 16. The semiconductor layer has a first portion including a P layer;
11. The MOS type semiconductor device according to claim 10, wherein the second portion has an N layer and the third portion has a P layer. 17. The first portion of the semiconductor layer is an N layer;
11. The MOS type semiconductor device according to claim 10, wherein the second portion has a P layer and the third portion has an N layer. 18. A third insulating layer covering the first portion, second portion, and third portion of the semiconductor layer, and a second insulating layer of the semiconductor layer on the third insulating layer. 11. The M according to claim 10, further comprising a second conductive layer mainly formed in a portion covering the portion of the M.
OS type semiconductor device. 19. In the semiconductor layer, the first portion is N
a first semiconductor region exhibiting conductivity of a type, a second part of which is P type, and a third part of which is N type; the first part is of P type, the second part is of N type, and a third part; and a second semiconductor region exhibiting P-type conductivity.
MOS type semiconductor device as described. 20. The MO according to claim 10, further comprising connecting means for electrically connecting any conductive layer selected from the first conductive layers.
S-type semiconductor device. 21. A first insulating layer, a top surface formed on the first insulating layer and isolated from the first insulating layer, and a side surface connecting the top surface and the first insulating layer. a conductive layer; a second insulating layer covering the top and side surfaces of the conductive layer and the first insulating layer; a first portion containing an impurity of a conductivity type; a second portion formed on a side surface of the conductive layer and connected to the first portion and containing an impurity of a conductivity type different from that of the first portion; , and is formed on an insulating layer formed by the first insulating layer or by overlapping the first insulating layer and the second insulating layer and does not cover the conductive layer. a third part that is connected to the second part and contains the same type of impurity as the first part;
S-type semiconductor device. 22. A first insulating layer, a top surface formed on the first insulating layer and isolated from the first insulating layer, and a side surface connecting the top surface and the first insulating layer. a conductive layer; a second insulating layer covering the top and side surfaces of the conductive layer and the first insulating layer; a first portion containing impurities of a conductive type at a high concentration; A second portion containing a lower concentration than the first portion is formed where the second insulating layer directly covers the first insulating layer, and is continuous with the second portion and has a second portion containing the second insulating layer at a lower concentration than the first portion. A MOS semiconductor device comprising: a third portion containing an impurity of the same conductivity type as the impurity contained in the portion at a higher concentration than the second portion. 23. The MOS type semiconductor device according to claim 22, further comprising a semiconductor substrate on which the first insulating layer is formed. 24. The MOS type semiconductor device according to claim 22, wherein the conductive layer includes a semiconductor material containing a high concentration of impurities. 25. Claim 2, wherein the second insulating layer includes a silicon nitride film or a silicon oxide film.
MOS type semiconductor device according to 2. 26. The MOS type semiconductor device according to claim 22, wherein the first portion and the second portion of the semiconductor layer have P-type characteristics. 27. The MOS type semiconductor device according to claim 22, wherein the first portion and the second portion of the semiconductor layer have N-type characteristics.