JPH0434794A - Memory control circuit - Google Patents

Abstract

PURPOSE:To maximize the execution cycle of storage holding operation and to reduce energy consumption by providing a refresh means performing refresh operation in a prescribed cycle by the group of a memory cell and a means designating the refresh cycle of the memory cell group according to the shortest storage holding time. CONSTITUTION:The memory control circuit is provided with a numerical registration means 300 outputting the maximum mask numerical signal corresponding to an entire storage holding operation (refresh operation) address 20 by 1:1, a storage holding operation request permission means 200 corresponding to the entire storage holding operation address 20 by 1:1, and a gate means 400 permitting the transmission of the decord result of a storage holding operation request signal 10, and constructed to change the cycle performing the storage holding operation. To most of the memory cells with the storage holding capacity of more than m-times that of conventional regulation, the cycle of the storage holding operation is selectively turned to be m-times that of the prescribed regulation to omit the unnecessary storage holding operation. Thus, the energy consumption for the storage holding operation can be reduced on average since the number of the storage holding operation can be reduced as the whole.

Description

TECHNICAL FIELD The present invention relates to a memory control circuit, and more particularly to a memory control circuit that performs a memory retention operation (refresh operation) on a memory.

Conventional technology Generally, DRAM (Dynamic RAM)
etc., it is necessary to perform a memory retention operation in order to retain the memory contents. The configuration of the main parts of a conventional memory control circuit that performs the memory retention operation is shown in the block diagram of FIG.

In the figure, a memory retention operation request signal (Ref refresh
When Request) 10 is input to the decoding means 100, the memory retention operation address signal (Rerresh
Address) 20 (1 to n) corresponds to one of the memory cell groups 1 to n, and an address-by-address memory retention operation request signal, for example, 11B, is generated and the memory cell group 1 including the memory cell 111 is A memory retention operation is performed.

In this case, the memory retention operation is performed at regular intervals for each memory retention operation address. In other words, the execution period of the memory retention operation is fixed in accordance with the memory retention capacity of the worst memory cell so that all the memory cells of the memory can retain the memory. In other words, the implementation period was set in advance according to the memory retention time of the memory cell with the shortest memory retention time among all the memory cells.

However, most memory cells have a memory retention capacity that sufficiently exceeds the memory retention operation period defined above. Therefore, unnecessary memory retention operations are performed even for most of these memory cells having sufficient memory retention capacity, resulting in the disadvantage of consuming excess power.

OBJECTS OF THE INVENTION The present invention has been made to solve the above-mentioned conventional drawbacks, and its purpose is to provide a memory control circuit that can eliminate unnecessary power consumption.

Structure of the Invention A memory control circuit according to the present invention includes a refresh means for refreshing a memory including a plurality of memory cell groups each consisting of a plurality of memory cells at a predetermined period for each memory cell group; Refresh cycle designation for each memory cell group, specifying a refresh cycle for the memory cell group according to the memory retention time of the memory cell with the shortest memory retention time among the memory cells in the memory cell group. It is characterized by having a means.

Example Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of main parts of an embodiment of a memory control circuit according to the present invention, and parts equivalent to those in FIG. 3 are designated by the same reference numerals.

In the figure, a memory control circuit according to an embodiment of the present invention includes a numerical value registration means 800 that outputs a maximum mask numerical signal in one-to-one correspondence to all memory retention operation addresses, and It has memory retention operation request permission means 200 corresponding to pair 1, and gate means 400 for permitting transmission of the decoding result of the memory retention operation request signal 10, and is configured to be able to change the cycle of performing the memory retention operation. ing.

For each memory retention operation address, the numerical registering means 300 stores information such that all memory cells in the memory cell group targeted for the memory retention operation can retain memory even if the memory retention operation cycle is m (rr, > 1) times the specified number. Set the maximum mask value signal for possible memory retention operation addresses.

Then, the memory retention operation request permission means 200 inputs the decoding result of the memory retention operation request signal 10 and the maximum mask value signal for each memory retention operation address, and each time the decoding result of the memory retention operation request signal 10 is input, An operation is performed to increment the count value corresponding to the memory retention operation address. When the counted value reaches the input value of the maximum mask numerical signal corresponding to the memory retention operation address, a memory retention operation permission signal is set and output. At the same time, it operates to reset the count value when the next memory retention operation request is input.

The gate means 400 inputs the decoding result of the memory retention operation request signal and the memory retention operation enable signal for each memory retention operation address, and when the memory retention operation permission signal is set, the decoding result of the memory retention operation request signal and the memory retention operation permission signal are input for each memory retention operation address. Transmission of a memory retention operation request signal to a memory retention operation address is permitted.

As a result, for a memory retention operation address that targets a memory cell group having a memory retention capacity m times greater than the prescribed value, the memory retention operation is performed with the refresh period m times the prescribed value.

It is assumed that the value of m is set in advance according to the memory cell with the worst memory retention capacity (that is, the shortest memory retention time) among the memory cells in each memory cell group 1 to 1.

In this configuration, by inputting the memory retention operation request signal 10 to the decoding means 100, memory cell groups 1 to n are input in response to n memory retention operation address signals 20.
A memory retention operation request signal (for example, 11a) for each address is generated for any one of the memory retention operation address signals 20 of the memory retention operation request permission means 200 and the gate means 400, that is, memory cell groups 1 to 1.
It is sent to the bit position corresponding to any one of n.

On the other hand, the numerical registering means 300 stores in advance each memory retention operation address signal 20, that is, for each memory cell group 1 to n that is the target of the memory retention operation, all memory cells in the memory cell group or m times the prescribed number of memory cells. If the memory can be retained even during the retention operation cycle, the maximum mask value (m-1) is set for the memory retention operation address signal 20, that is, the bit position corresponding to the memory cell groups 1 to n. The output of this numerical value registration means 300 is the maximum mask numerical signal (for example, 3
1a), it is sent to a bit position corresponding to the memory retention operation address signal 20 to the memory retention operation request permission means 200, that is, corresponding to any one of the memory cell groups 1 to n.

The memory retention operation request permission means 200 increments the count value each time a memory retention operation request signal for each bit and address (for example, 11a) is input, and when the count value is greater than or equal to the input value of the maximum mask numerical signal (for example, 31a). When the memory retention operation enable signal (for example, 21a) is set, the memory retention operation address signal 20 of the gate means 400, that is, the memory retention operation enable signal 21a, that is, the memory retention operation enable signal 21a, which corresponds to one of the memory cell groups 1 to n, is set.
Output to the soto position. Furthermore, the count value is reset in response to the input of the next address-by-address storage holding operation request signal (for example, 11a).

The gate means 400 is set with a memory retention operation address signal 20, that is, a memory retention operation enable signal (for example, 21a) inputted for each bit corresponding to one of the memory cell groups 1 to n. If there is a memory retention operation request signal for each address (for example, 11a)
Permit transmission.

In this way, the memory retention operation for each address is performed with the memory retention operation cycle m times the regulation for memory retention operation addresses that target a memory cell group having a memory retention capacity of m or more than the regulation. request signal (e.g. 11
b) to one of the memory cell groups 1 to n corresponding to the memory retention operation address signal 20 (1 to n), for example, when the memory retention operation address signal 20 is "1", the memory cell group 1 The memory retention operation is performed by outputting the data to

Next, the internal configuration of the memory retention operation request permission means 200 shown in FIG. 1 will be explained using FIG. 2.

FIG. 2 is a block diagram showing the configuration of the memory retention operation request permission means 200 of the memory control circuit shown in FIG. 1. In the figure, as an example of each bit, the memory retention address signal 20 is "1", that is, the memory retention operation request permission means 201 for one bit corresponding to the memory cell group 1 is shown.

In the figure, the counting means 221 receives the memory holding operation request signal 1.
1a, the count value is incremented and a count value signal 22a is output to the comparison means 211.

The comparison means 211 receives the count value signal 22g and the maximum mask value signal 31a, and when the value of the count value signal 22a matches the input value of the maximum mask value signal 31a, the storage operation permission signal 21a is output. is set and output. Further, the memory retention operation permission signal 21a is transmitted to the counting means 22.
It is also output to the reset terminal of No.1. Therefore, after the value of the count value signal 22a reaches the input value of the maximum mask value signal 31a, the count value of the counting means 221 is reset.

If the memory control circuit with the above configuration is used to perform a memory retention operation for a memory that requires a memory retention operation, it will not be necessary for most memory cells that have a memory retention capacity of m or more than the conventional regulation. By selectively increasing the memory retention operation cycle by m times the above prescribed value so as to omit the memory retention operation, the overall number of memory retention operations can be reduced.
On average, current consumption for memory retention operation can be reduced,
This makes it possible to suppress excess power consumption.

Note that if the value held in the numerical value registration means is configured to be able to be rewritten from the outside, the refresh cycle can be changed more flexibly.

As described in detail, according to the present invention, it is possible to maximize the execution cycle of the memory retention operation and reduce power consumption.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a memory control circuit according to an embodiment of the present invention, FIG. 2 is a block diagram showing the internal configuration of a memory retention operation request permission means, and FIG. 3 is a block diagram showing the configuration of a conventional memory control circuit. FIG. Explanation of symbols of main parts 100...Decoding means 200...Memory retention operation request permission means 300.
... Numerical registration means 400 ... Gate means

Claims (1)

[Claims] (1) Refreshing means for refreshing a memory including a plurality of memory cell groups each consisting of a plurality of memory cells at a predetermined period for each of these memory cell groups; , refresh cycle designating means for respectively designating the refresh cycle for the memory cell group according to the memory retention time of the memory cell whose memory retention time is the shortest among the memory cells in the memory group. memory control circuit.