JPH04163786A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce power consumption for memory holding operation by selectively increasing a memory holding operation period by fixed times in order to omit unnecessary memory holding operation. CONSTITUTION:A gate means 400 inhibits the transmission of a memory holding operation demand signal (such as D11a) at every address in response to memory holding operation address signals D20 (addresses = 1-n) respectively-that is, when both a memory holding operation demand count-value signal (such as D21a) input at every bit corresponding to either of the memory cell groups 1-n and a mask signal (such as D31a) are set. A memory holding operation demand signal at every address (such as D11b), in which memory holding operation periods are executed by (m) times of a normal regarding memory holding operation addresses using memory cell groups having memory holding capacity of (m) times or more of the normal one as objects, is output to the memory cell group 1 in either of the corresponding memory cell groups 1-n-for example, when the address value of the memory holding operation address signal D20 is '1', and memory holding operation is carried out. Accordingly, memory holding currents are reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device that requires a memory retention operation.

[Conventional technology]

The main parts of an example of a memory retention circuit configuration of a semiconductor memory device that requires a conventional memory retention operation are shown in the block diagram of FIG. In FIG. 3, the memory retention operation request signal DIO is converted into a memory retention operation address signal D20 by the decoding means 100.
(address=1 to n), a memory holding operation request signal for each address, for example, D 11 a, is generated for one of the memory cell groups 1 to 0, and the memory cell 111
A memory retention operation is performed on the memory cell group 1 including.

The above-described memory retention operation is performed at regular intervals for each memory retention operation address. In other words, the memory retention operation cycle is fixed according to the memory retention capacity of the worst memory cell so that all memory cells of the semiconductor memory device can retain memory.

[Problem to be solved by the invention]

However, most memory cells have a memory retention capability that is well in excess of the prescribed memory retention operation period mentioned above. Therefore, unnecessary memory retention operations are performed on most of these memory cells that have sufficient memory retention capacity.
Current is being consumed more than necessary.

[Means to solve the problem]

The semiconductor memory device of the present invention includes a plurality of memory cell groups, each of which requires a memory retention operation at an arbitrary cycle equal to or longer than a prescribed memory retention operation cycle, and to which a corresponding memory retention operation address is assigned; For each memory retention operation address, it is determined whether all the memory cells in the corresponding memory cell group are capable of retaining memory even in a memory retention operation cycle that is a predetermined number of times the prescribed memory retention operation cycle. mask information storage means for setting in advance mask information to indicate the memory retention operation address, and outputting a corresponding mask signal based on the mask information when the memory retention operation address is input; a memory retention operation request counting means that repeatedly counts the number of retention operation requests in units of the predetermined number and outputs a memory retention operation request count signal excluding a period until the counted value is added by "1" from the initial value; ; for each of the memory retention operation addresses, the output of the mask information storage means and the output of the memory retention operation request counting means are input, and both the mask signal and the memory retention operation request count signal are input; and gate means for inhibiting a memory retention operation request to the memory cell group corresponding to the memory retention operation address when the memory retention operation address is stored.

Further, in the above configuration, the memory retention operation request counting means may be configured to arbitrarily set the predetermined number, which is a unit for counting the number of memory retention operation requests, for each of the memory retention operation addresses. .

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the main parts of a memory retention operation circuit configuration in an embodiment of the semiconductor memory device of the present invention. In FIG. 1, a memory retention operation request signal DIO is converted into a memory retention operation address signal D2 by a decoding means 100.
0 (address=1 to n), memory cell group 1-n
A storage holding operation request signal for each address (for example, DLla) is generated for one of the storage holding operation request signals and outputted to corresponding bit positions of the storage holding operation request counting means 200 and gate means 400, respectively. This memory retention operation request counting means 200 increments a count value for each bit each time a memory retention operation request signal for each address (for example, Dlla) is input, and when the count value exceeds a prespecified value m. When this occurs, it is reset, and a memory retention operation request count signal (for example, D21a) is generated and output to the corresponding bit position of the gate means 400 except for the period after being reset until the next increment.

On the other hand, in the read-only mask information storage means 300,
In advance, for each memory retention operation address signal D20 (address=1 to n), that is, for each memory cell group 1 to n that is the target of the memory retention operation, all the memory cells 111 of the memory cell group are specified. Mask information indicating whether memory can be retained even with a memory retention operation cycle m times m is set, and a mask signal (( For example, it is output as D31 a) to the corresponding bit position of the gate means 400.

The gate means 400 receives a memory retention operation request meter input for each bit corresponding to the memory retention operation address signal D20 (address=1 to n), that is, corresponding to any one of the memory cell groups 1 to n. When both the numerical signal (for example, D21 a) and the mask signal (for example, D31 a) are set, transmission of the memory retention operation request signal for each address (for example, Dlla) is prohibited, and the prescribed m borrowing is performed. For memory retention operation addresses that target memory cell groups with the above memory retention capacity, a memory retention operation request signal (for example, Dllb) for each address that is executed by multiplying the memory retention operation cycle by m times the specified value is supported. Any one of the memory cell groups 1 to n, for example,
The address value of the memory retention operation address signal D20 is “1”
In this case, the signal is output to the memory cell group 1 to perform the memory retention operation.

Note that the value of m may be any value that can be specified for each of the memory cell groups 1 to n within a range that guarantees the memory retention operation.

Further, when the value of m is "2", the memory retention operation request counting means 200 is constituted by a T flip-flop that inverts the content of the bit held every time a memory retention operation request signal for each address (for example, Dlla) is input. You can also.

FIG. 2 is a circuit diagram showing the configuration of gate means 400 for inhibiting a memory retention operation request in the memory retention operation circuit configuration of FIG. 1, and shows gate means 401 for one bit corresponding to memory cell group 1. . In FIG. 2, the NAND gate 4i1 to which the memory retention operation request count signal D21a and the mask signal D31a are input generates the memory retention operation permission signal D41a and outputs it to the AND gate 421. AND gate 421 to which the address-by-address storage retention operation request signal Dlla and the storage retention operation permission signal D41a are input.
generates a memory holding one operation request signal D11b for each address and outputs it to the memory cell group 1. That is, NAND gate 4
11, when the memory retention operation request count signal D21a and the mask signal D31a are set, the memory retention operation request signal Dlla for each address is output to the AND gate 42.
The memory retention operation permission signal D41a is reset to prohibit transmission through the memory retention operation permission signal D41a.
By resetting 41a, the AND gate 421 prohibits the address-by-address storage holding operation request signal Dilb from being output to the memory cell group 1.

〔Effect of the invention〕

As explained above, the present invention eliminates unnecessary memory retention operations for most memory cells whose memory retention capacity is more than a predetermined number of times the conventional regulation in semiconductor memory devices that require memory retention operations. By selectively increasing the memory retention operation cycle by a predetermined number of times the above-mentioned regulation, the overall number of memory retention operations can be reduced to close to 1/predetermined number, so on average, the number of memory retention operations can be reduced by a predetermined number. This has the effect of reducing the current consumption to nearly 1/predetermined number.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the main parts of the memory retention operation circuit configuration in an embodiment of the semiconductor memory device of the present invention, and FIG.
The figure is a circuit diagram showing an example of the configuration of the gate means for inhibiting a memory retention operation request in the memory retention operation circuit configuration of FIG. 1, and FIG. 3 shows the main parts of an example of the memory retention operation circuit configuration of a conventional semiconductor memory device. FIG. 1 to n...Storage cell group, 100...Decoding means,
111...Storage cell, 200...Memory retention operation request counting means, 300...Mask information, 400.401.
...Gate means, 411...NAND gate, 421
...AND gate.

Claims (1)

[Scope of Claims] 1. A plurality of memory cell groups, each of which includes memory cells that require a memory retention operation at an arbitrary cycle equal to or longer than a prescribed memory retention operation cycle, and each of which is assigned a corresponding memory retention operation address; For each memory retention operation address, it is determined whether all the memory cells in the corresponding memory cell group are capable of retaining memory even in a memory retention operation cycle that is a predetermined number of times the prescribed memory retention operation cycle. mask information storage means for setting in advance mask information to indicate the memory retention operation address, and outputting a corresponding mask signal based on the mask information when the memory retention operation address is input; The number of times the holding operation is requested is repeatedly counted in units of the predetermined number, and the counted value is “1” from the initial value.
``memory retention operation request counting means that outputs a memory retention operation request count signal excluding the period up to addition; the output of the request counting means, and when the mask signal and the memory retention operation request count signal are both input, a memory retention operation request is sent to the memory cell group corresponding to the memory retention operation address. 2. A semiconductor memory device characterized in that the memory retention operation request counting means has a unit for counting the number of times a memory retention operation is requested for each of the memory retention operation addresses. 2. The semiconductor memory device according to claim 1, wherein the number can be set arbitrarily.