JPH04346249A - Chip carrier - Google Patents
Chip carrierInfo
- Publication number
- JPH04346249A JPH04346249A JP3147800A JP14780091A JPH04346249A JP H04346249 A JPH04346249 A JP H04346249A JP 3147800 A JP3147800 A JP 3147800A JP 14780091 A JP14780091 A JP 14780091A JP H04346249 A JPH04346249 A JP H04346249A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- cap
- spacer
- substrate
- chip carrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 125000006850 spacer group Chemical group 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000006073 displacement reaction Methods 0.000 abstract 1
- 239000000853 adhesive Substances 0.000 description 5
- 230000001070 adhesive effect Effects 0.000 description 5
- 230000017525 heat dissipation Effects 0.000 description 4
- 229920002379 silicone rubber Polymers 0.000 description 3
- 239000004945 silicone rubber Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229920001971 elastomer Polymers 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15182—Fan-in arrangement of the internal vias
- H01L2924/15184—Fan-in arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Cooling Or The Like Of Electrical Apparatus (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】0001
【技術分野】本発明はチップキャリアに関し、特に電子
装置等に使用される配線基板上にＩＣチップを実装する
ために用いるチップキャリアに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip carrier, and more particularly to a chip carrier used for mounting an IC chip on a wiring board used in an electronic device or the like.
【０００２】0002
【従来技術】従来、この種のチップキャリアはＩＣチッ
プと、このＩＣチップの片面が、内面に接着されるキャ
ップと、このキャップが接着され、かつＩＣチップが電
気的に接続された基板とを含んで構成されていた。そし
て、ＩＣチップの他面と基板との間にはスペーサが設け
られ、そのスペーサとしては、無垢のゴムを用いていた
。2. Description of the Prior Art Conventionally, this type of chip carrier consists of an IC chip, a cap to which one side of the IC chip is adhered to the inner surface, and a substrate to which the cap is adhered and to which the IC chip is electrically connected. It was composed of: A spacer is provided between the other surface of the IC chip and the substrate, and the spacer is made of solid rubber.
【０００３】しかし、上述した従来のチップキャリアで
は、ゴムの硬さが硬いため、放熱板として作用するキャ
ップやＩＣチップの高さ寸法の公差によりＩＣチップを
キャップへ押える力がばらつき、ＩＣチップとキャップ
との間の接着剤の厚さがばらついて、それにより放熱特
性がばらつくという欠点がある。However, in the above-mentioned conventional chip carrier, since the rubber is hard, the force that presses the IC chip against the cap varies due to tolerances in the height dimensions of the cap and IC chip, which act as heat sinks, and the IC chip and There is a drawback that the thickness of the adhesive between the cap and the cap varies, resulting in variations in heat dissipation characteristics.
【０００４】0004
【発明の目的】本発明は上述した従来の欠点を解決する
ためになされたものであり、その目的は放熱特性の信頼
性の高いチップキャリアを提供することである。OBJECTS OF THE INVENTION The present invention has been made to solve the above-mentioned conventional drawbacks, and its purpose is to provide a chip carrier with highly reliable heat dissipation characteristics.
【０００５】[0005]
【発明の構成】本発明によるチップキャリアは、ＩＣチ
ップと、このＩＣチップの一主面が、内面に接着される
キャップと、このキャップが接着されかつ前記ＩＣチッ
プが電気的に接続された基板と、この基板と前記ＩＣチ
ップの他主面との間に設けられたスペーサとを有するチ
ップキャリアであって、前記スペーサは中空可撓性部材
からなることを特徴とする。A chip carrier according to the present invention comprises an IC chip, a cap to which one main surface of the IC chip is adhered to the inner surface, and a substrate to which the cap is adhered and the IC chip is electrically connected. and a spacer provided between the substrate and the other main surface of the IC chip, wherein the spacer is made of a hollow flexible member.
【０００６】[0006]
【実施例】次に、本発明について図面を参照して説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.
【０００７】図１は本発明によるチップキャリアの一実
施例の構成を示す縦断面図である。FIG. 1 is a longitudinal sectional view showing the structure of an embodiment of a chip carrier according to the present invention.
【０００８】図において、基板１は上面に複数のパッド
２、下面に複数の入出力用バンプ３を有し、各パッド２
と各バンプ３とは内部配線４により接続されている。基
板１のＩＣチップ５と対向する部分には、例えば窒素を
シリコーンゴムで覆う中空球形構造のスペーサ６が接着
剤１０等により複数個並べて固定される。In the figure, a substrate 1 has a plurality of pads 2 on the upper surface and a plurality of input/output bumps 3 on the lower surface, and each pad 2
and each bump 3 are connected by internal wiring 4. On a portion of the substrate 1 facing the IC chip 5, a plurality of spacers 6 having a hollow spherical structure, for example, in which nitrogen is covered with silicone rubber, are arranged and fixed with an adhesive 10 or the like.
【０００９】複数のリード７を有するＩＣチップ５はリ
ード７を所定の形状に成形された後、基板１上に実装さ
れる。そして、リード７とパッド２とは金属熱圧着法等
によりフェイスダウン接続される。The IC chip 5 having a plurality of leads 7 is mounted on the substrate 1 after the leads 7 are formed into a predetermined shape. Then, the lead 7 and the pad 2 are connected face-down by metal thermocompression bonding or the like.
【００１０】また、キャップ８の内面にはＩＣチップ５
が接着剤９で接着される。このとき、各スペーサ６は内
部に中空６１を有するシリコーンゴム６２であるため、
スペーサ６の変位に対する力が、中空６１を有していな
い場合に比べて小さい。よって接着剤９は、ＩＣチップ
５やキャップ８の高さ方向のばらつきがスペーサ６で吸
収されるため均一に押え付けられる。したがって、ＩＣ
チップ５とキャップ８との接着が均一化され、良好な放
熱特性が得られる。ここで、スペーサ６を複数個並べる
のは、スペーサ６が球形であるため、１個であると、そ
の上に乗せるＩＣチップ５がスペーサ６の位置ずれによ
って傾き、キャップ８への接着のための押え付け力が不
均一となり熱抵抗が悪くなったり、リード７をパッド２
から剥したりするおそれがあるためである。また、キャ
ップ８は基板１とも接合されて、ＩＣチップ５を封止す
る。[0010] Furthermore, an IC chip 5 is mounted on the inner surface of the cap 8.
are adhered with adhesive 9. At this time, since each spacer 6 is made of silicone rubber 62 having a hollow 61 inside,
The force required to displace the spacer 6 is smaller than when the spacer 6 does not have the hollow 61. Therefore, the adhesive 9 can be pressed down uniformly because variations in the height direction of the IC chip 5 and the cap 8 are absorbed by the spacer 6. Therefore, I.C.
The adhesion between the chip 5 and the cap 8 is made uniform, and good heat dissipation characteristics are obtained. Here, the reason for arranging a plurality of spacers 6 is that the spacer 6 is spherical, so if there is only one spacer 6, the IC chip 5 to be placed on top of it will be tilted due to the positional shift of the spacer 6, and it will be difficult to adhere to the cap 8. The pressing force may be uneven, resulting in poor thermal resistance, or the lead 7 may be
This is because there is a risk of it peeling off. Further, the cap 8 is also bonded to the substrate 1 to seal the IC chip 5.
【００１１】なお、スペーサは、シリコーンゴムに限ら
ず、各種の可撓性部材を用いて中空構造とすれば良い。[0011] The spacer is not limited to silicone rubber, and may be made of various flexible members to form a hollow structure.
【００１２】0012
【発明の効果】以上説明したように本発明は、ＩＣチッ
プとキャップとの接着が均一にできるので放熱特性にお
いて信頼性の高いチップキャリアが得られるという効果
がある。As explained above, the present invention has the effect that since the IC chip and the cap can be bonded uniformly, a chip carrier with high reliability in heat dissipation characteristics can be obtained.
【図１】本発明の実施例によるチップキャリアの構成を
示す縦断面図である。FIG. 1 is a longitudinal sectional view showing the structure of a chip carrier according to an embodiment of the present invention.
１ 基板 ２ パッド ５ ＩＣチップ ６ スペーサ ７ リード ８ キャップ ９，１０ 接着剤 1 Board 2 Pad 5 IC chip 6 Spacer 7 Lead 8 Cap 9,10 Adhesive
Claims (1)
面が、内面に接着されるキャップと、このキャップが接
着されかつ前記ＩＣチップが電気的に接続された基板と
、この基板と前記ＩＣチップの他主面との間に設けられ
たスペーサとを有するチップキャリアであって、前記ス
ペーサは中空可撓性部材からなることを特徴とするチッ
プキャリア。1. An IC chip, a cap to which one main surface of the IC chip is adhered to an inner surface, a substrate to which the cap is adhered and the IC chip is electrically connected, and the substrate and the IC chip. 1. A chip carrier comprising a spacer provided between the chip and the other main surface of the chip, the spacer being made of a hollow flexible member.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3147800A JPH04346249A (en) | 1991-05-23 | 1991-05-23 | Chip carrier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3147800A JPH04346249A (en) | 1991-05-23 | 1991-05-23 | Chip carrier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04346249A true JPH04346249A (en) | 1992-12-02 |
Family
ID=15438503
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3147800A Pending JPH04346249A (en) | 1991-05-23 | 1991-05-23 | Chip carrier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04346249A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6271058B1 (en) | 1998-01-06 | 2001-08-07 | Nec Corporation | Method of manufacturing semiconductor device in which semiconductor chip is mounted facedown on board |
| JP2014029977A (en) * | 2012-07-05 | 2014-02-13 | Fujikura Ltd | Heat dissipation structure of electronic device |
-
1991
- 1991-05-23 JP JP3147800A patent/JPH04346249A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6271058B1 (en) | 1998-01-06 | 2001-08-07 | Nec Corporation | Method of manufacturing semiconductor device in which semiconductor chip is mounted facedown on board |
| JP2014029977A (en) * | 2012-07-05 | 2014-02-13 | Fujikura Ltd | Heat dissipation structure of electronic device |
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