JPH0434573U - - Google Patents
Info
- Publication number
- JPH0434573U JPH0434573U JP7731490U JP7731490U JPH0434573U JP H0434573 U JPH0434573 U JP H0434573U JP 7731490 U JP7731490 U JP 7731490U JP 7731490 U JP7731490 U JP 7731490U JP H0434573 U JPH0434573 U JP H0434573U
- Authority
- JP
- Japan
- Prior art keywords
- delay
- capacitor
- valve
- elements
- delay circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 3
- 238000007599 discharging Methods 0.000 description 1
Description
第１図はこの考案の実施例の回路図、第２図は
同じく実施例のＦＥＴ素子の電流特性曲線を表わ
したグラフ、第３図は同じく実施例のコンデンサ
の電荷の変化を表わしたグラフ、第４図は同じく
実施例のコンデンサの充放電々流の変化を表わし
たグラフ、第５図はこの考案の他の実施例の回路
図、第６図は従来の遅延バルブの回路図である。
１……電磁バルブ、２……遅延回路、３……遅
延バルブ、４……コンデンサ、５，６……ＦＥＴ
素子、９ａ，９ｂ……制御回路。
FIG. 1 is a circuit diagram of an embodiment of this invention, FIG. 2 is a graph showing the current characteristic curve of the FET element of the same embodiment, and FIG. 3 is a graph showing changes in the charge of the capacitor of the same embodiment. FIG. 4 is a graph showing changes in charging and discharging currents of a capacitor according to the same embodiment, FIG. 5 is a circuit diagram of another embodiment of this invention, and FIG. 6 is a circuit diagram of a conventional delay valve. 1... Solenoid valve, 2... Delay circuit, 3... Delay valve, 4... Capacitor, 5, 6... FET
Element, 9a, 9b...control circuit.
Claims (1)
ブにおいて、前記遅延回路がコンデンサと、該コ
ンデンサと直列に接続された２個のＦＥＴ素子で
構成され、２個のＦＥＴ素子が双方向に接続され
ていることを特徴とした遅延バルブ。 ２ ２個のＦＥＴ素子は、ゲートがソースと接続
してある請求項１記載の遅延バルブ。[Claims for Utility Model Registration] 1. In a delay valve composed of an electromagnetic valve and a delay circuit, the delay circuit is composed of a capacitor and two FET elements connected in series with the capacitor; A delay valve characterized by elements being bidirectionally connected. 2. The delay valve according to claim 1, wherein the gates of the two FET elements are connected to the sources.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7731490U JPH0434573U (en) | 1990-07-20 | 1990-07-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7731490U JPH0434573U (en) | 1990-07-20 | 1990-07-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0434573U true JPH0434573U (en) | 1992-03-23 |
Family
ID=31619589
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7731490U Pending JPH0434573U (en) | 1990-07-20 | 1990-07-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0434573U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6111839A (en) * | 1984-06-26 | 1986-01-20 | Ricoh Co Ltd | Power-on initializing circuit |
| JPH0256875B2 (en) * | 1982-11-26 | 1990-12-03 | Fuji Denki Sogo Kenkyusho Kk |
-
1990
- 1990-07-20 JP JP7731490U patent/JPH0434573U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0256875B2 (en) * | 1982-11-26 | 1990-12-03 | Fuji Denki Sogo Kenkyusho Kk | |
| JPS6111839A (en) * | 1984-06-26 | 1986-01-20 | Ricoh Co Ltd | Power-on initializing circuit |