JPH04344945A - Data processor - Google Patents

Abstract

PURPOSE:To confirm the operation of a whole device by finding out the fault of a specified component in a processor to operate at a specified instruction so as to execute efficiently analysis and evasion. CONSTITUTION:This processor consisting of plural components is provided with an error-free instruction designating register 1 to designate the specified instruction so that the detection of an error is not executed during the execution of the instruction, an instruction register 3 for holding the instruction being executed at present and a comparing means 5 to compare the contents of the error-free instruction designating register 1 and the instruction code part of the instruction register 3 with each other. Then, for a period in which the contents of the error-free instruction designating register 1 and the instruction code part of the instruction register 3 coincide with each other, the device is controlled so as not to detect the error occurring in the components in the processor.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a data processing device consisting of a plurality of components, and in particular, the present invention relates to a data processing device that is made up of a plurality of components, and in particular, to prevent failures in the device by controlling so that errors occurring in each component are not detected during the execution of a specific instruction. The present invention relates to a data processing device that facilitates discovery and correction.

0002

2. Description of the Related Art FIG. 4 is a block diagram showing an error detection control circuit in a conventional data processing device. In the figure, 7 is an error-free latch for operating the data processing device in an error-free state, and 8 is an error Error free mode signal, which is the output signal from free latch 7, 11
is the parity of data "10" to "13", 12 is an error detection circuit, 13 is an error detection signal output from the error detection circuit 12, and 15 is an error indicating that an error has occurred in a component of the data processing device. The signal 16 is an inverter.

Next, the operation will be explained. At the initial stage of testing a data processing device, it is necessary to operate the device without detecting errors occurring within the device. In that case, by setting the error free latch 7,
Make error free mode signal 8 significant.

In this state, even if the parity 11 of the output data "10" to "13" of the components in the data processing device is not a correct value and the error detection signal 13 becomes significant, the error free mode signal 8 is significant, so the error signal 15 does not become significant and no error is detected. Therefore, when the error-free mode signal 8 is made significant, even if an error such as a parity error occurs, the operation of each component in the data processing device can be checked.

[0005]

[Problem to be Solved by the Invention] Since the error detection control circuit in the conventional data processing device was configured as described above, it was not possible to precisely control the error-free state, and the device was always kept in the error-free state. Therefore, there was a problem in that it was not possible to efficiently discover and analyze failures using specific instructions.

[0006] This invention has been made to solve the above-mentioned problems, and in addition to providing a signal to maintain an error-free state at all times, it also provides a signal to maintain an error-free state only while a specific instruction is being executed. It is an object of the present invention to provide a data processing device that can perform fine-grained error-free state control corresponding to instructions and efficiently discover and analyze failures caused by specific instructions.

[0007]

[Means for Solving the Problems] A data processing device according to the present invention provides an error-free instruction that specifies a specific instruction so that error detection is not performed during instruction execution in a data processing device consisting of a plurality of components. a designation register, an instruction register for holding an instruction currently being executed, and comparison means for comparing the contents of the error-free instruction designation register and an instruction code portion of the instruction register; Control is performed so that errors occurring in the components within the data processing device are not detected during a period when the contents match the instruction code portion of the instruction register.

[0008] Furthermore, the data processing device according to the present invention includes:
A plurality of error-free instruction specification registers are provided for specifying instructions for which error detection is not executed, and during execution of a plurality of instructions specified by the plurality of error-free instruction specification registers,
This is to control so that errors are not detected.

[0009]

[Operation] The data processing device according to the present invention can be kept in an error-free state when executing a specific instruction, thereby avoiding failure of components operated by the specific instruction.
It becomes possible to check the operation of the device. Furthermore, since the location of the failure is clarified by the specific command, the failure can be discovered and corrected in a short period of time.

Furthermore, since a plurality of instructions that operate in an error-free state can be specified, more fine-grained error control is possible.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a data processing apparatus according to the present invention. In the figure, 1 is an error-free instruction specification register for specifying an instruction to operate in an error-free state, 2 is a data bus, 3 is an instruction register (IR) that takes in the instructions transferred by data bus 2, and 4 is an instruction start signal, 5 is a comparison circuit that compares the contents of error-free instruction specification register 1 and the instruction code part of instruction register 3, and 6 is a specific instruction that becomes significant when the instruction codes of error-free instruction specification register 1 and instruction register 3 are equal. It is an error free signal.

Further, 7 is an error-free latch for always operating the data processing device in an error-free state, 8 is an error-free mode signal which is an output from the error-free latch 7, 9 is an OR gate, and 10 is an error-free state. Error-free signal indicating that 11 is data “10
” to “13” parity, 12 is error detection circuit, 13
14 is a NOR gate, 15 is an error signal, 16 is an inverter, 17 is an AND gate, and 18 is a clock T0.

Next, the operation will be explained. FIG. 2 is a timing chart showing the operation of the data processing device shown in FIG. The device in Fig. 1 has two-phase clocks T0, T
1. However, the clock T1 is not particularly used.

First, the instruction start signal 4 is significant and the data on the data bus 2 is taken into the instruction register 3 at the timing of the clock T018. The data taken into the instruction register 3 is the instruction to be executed. The instruction code stored in the error-free instruction designation register 1 and the instruction code portion of the instruction register 3 are input to the comparison circuit 5 in advance, and if the instruction codes in both registers match, the instruction code from the comparison circuit 5 is input. The output specific instruction error free signal 6 becomes significant during one instruction period.

During the period in which the specific instruction error-free signal 6 or the error-free mode signal 8 set in the error-free latch 7 is significant, the error-free signal 10 becomes significant. Even if the parity 11 of data "10" to "13" is invalid and the error detection signal 13 is significant, the error signal 15 will not be significant during the period when the error free signal 10 is significant, and the error will not be detected. Not done.

Next, an embodiment of the second invention shown in FIG. 3 will be described. In the figure, numerals 21, 22, and 23 are error-free instruction designation registers added to designate a plurality of instructions, and any number of these can be added.

Next, the operation will be explained. The inputs to the comparison circuit 5 are the error-free instruction specification register A21 and the instruction register 3, as well as the error-free instruction specification register B22 and the error-free instruction specification register C2.
It is 3. The values of these multiple error-free instruction designation registers and the instruction code portion of the instruction register 3 are input to the comparison circuit 5, and if the instruction code of the instruction register 3 matches any one of the values of the multiple error-free instruction designation registers, it is specified. The instruction error free signal 6 becomes significant and no error is detected.

In the present invention, an error-free state is set by comparing the contents of the error-free instruction designation register 1 and the instruction code being executed. However, by changing the input to the comparison circuit 5, an error can be detected when other conditions are met. It is also possible to set a free state. For example, it is possible to achieve an error-free state when a specified range of addresses is being executed or during a specified machine cycle period.

[0019]

[Effects of the Invention] As described above, according to the present invention, it is possible to achieve an error-free state only during the execution of a specific instruction, and it is possible to avoid failures in specific components within a data processing device that operate according to a specific instruction. It is possible to check the operation of the entire device.

Furthermore, more detailed error-free control can be performed, and failure locations can be found, analyzed, and corrected efficiently in a short period of time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of a data processing device according to the present invention.

FIG. 2 is a timing chart showing the operation of the data processing device shown in FIG. 1;

FIG. 3 is a block diagram showing the configuration of an embodiment of a second data processing device according to the present invention.

FIG. 4 is a block diagram showing the configuration of a conventional data processing device.

[Explanation of symbols]

1 Error-free instruction specification register 3 Instruction register 5 Comparison circuit 7 Error free latch 12 Error detection circuit

Claims (2)

[Claims] Claim 1: In a data processing device consisting of a plurality of components, an error-free instruction specification register for specifying a specific instruction so that error detection is not performed during instruction execution, and for holding an instruction currently being executed. an instruction register, and comparison means for comparing the contents of the error-free instruction designation register and the instruction code portion of the instruction register, and the contents of the error-free instruction designation register and the instruction code portion of the instruction register match. A data processing apparatus characterized in that control is performed so that an error occurring in a component within the data processing apparatus is not detected during a period during which the data processing apparatus is in use. 2. A plurality of error-free instruction specification registers for specifying instructions for which the error detection is not executed,
2. The data processing apparatus according to claim 1, wherein control is performed so that no errors are detected during execution of the plurality of instructions specified by the plurality of error-free instruction specification registers.