JPH04344784A - Scanning speed converter for television signal - Google Patents

Abstract

PURPOSE:To form a television signal synchronously with a marker signal by applying scanning speed conversion to the television signal without specific provision of an input terminal for external synchronization. CONSTITUTION:A marker signal generated at a period of a standard television signal inserted to a television signal having a scanning speed being an odd number (N) of multiple of the speed of the standard television signal is detected by a marker signal detection circuit 16, time axis expansion processing is applied based on the marker signal and the television signal having a scanning speed equal to the scanning speed of the standard television signal is read from field memories 5, 6.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention is a television signal scanning speed converter that converts the scanning speed of a television signal having an odd number (N) times the scanning speed of a standard television signal to 1/N and outputs the same. Regarding.

0002

[Prior Art] Television signals of the standard television system have a prescribed scanning period for one screen.
In the case of the C system, the field frequency is 60 Hz, so an NTSC television camera cannot capture dynamic objects that change faster than 1/60 second. Therefore, as disclosed in, for example, Japanese Patent Laid-Open No. 59-17292, a television camera with a scanning speed N times that of the standard television system is used to capture an image, and the output signal of the image is sent to a video tape recorder. A high-speed development recording device that performs channel recording has been provided.

[0003] In order to monitor the imaging output from the N-times scanning television camera used in such a high-speed development and recording device using an image monitor, a special N-times scanning image monitor may be used, or a It is necessary to use a scanning speed conversion device that converts the scanning speed of the imaging output to the scanning speed of the standard television system.

0004

[Problems to be Solved by the Invention] By the way, television cameras perform imaging operations synchronized with a reference television signal for external synchronization. A television signal of N times speed scanning is generated based on Such a scanning speed conversion device that converts the scanning speed of the imaging output from an N times scanning television camera to the scanning speed of the standard television system requires a reference television signal of 1 times speed scanning. A reference television signal is required, and the input terminal for the N-times scanning high-speed television signal and the input terminal for the 1-times scanning reference television signal must be installed in parallel, which increases the number of external connection terminals. There is a problem.

[0005] The present invention has been made in view of the above circumstances, and provides an input terminal for a high-speed television signal for N-times scanning and an input terminal for a reference television signal for external synchronization in parallel. An object of the present invention is to provide a television signal scanning speed converting device capable of converting the scanning speed of an image pickup output from an N-times scanning television camera to the scanning speed of a standard television system without causing any problems.

[0006]

[Means for Solving the Problems] In order to solve the above-mentioned problems, the television signal scanning speed conversion device according to the present invention provides a television signal having a scanning speed that is an odd number (N) times that of a standard television signal. A marker signal generated at the cycle of the standard television signal inserted in the N is detected, a memory control signal is generated based on the detected marker signal, and writing and reading are controlled by this memory control signal. This invention is characterized in that a television signal having a scanning speed equal to the scanning speed of the standard television signal is generated by a memory that extends the time axis of the television signal having twice the scanning speed. The marker signal has a white level of 100%, for example, and is inserted at a position corresponding to the vertical retrace interval of the standard television signal.

[0007]

[Operation] In the television signal scanning speed conversion device according to the present invention, the scanning speed is generated at the period of the standard television signal inserted into the television signal having a scanning speed that is an odd number (N) times that of the standard television signal. A time axis expansion process is performed on the marker signal to generate a television signal having a scanning speed equal to the scanning speed of the standard television signal.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a television signal scanning speed conversion apparatus according to the present invention will be described below with reference to the drawings. A television signal scanning speed conversion device according to the present invention is configured as shown in FIG. 1, for example.

The television signal scanning speed conversion device shown in FIG. 1 converts a triple-speed scanning television signal obtained as an image output from a triple-speed scanning television camera into a standard television system scanning speed. in,
The triple-speed scanning television signal VIDEOIN is supplied to the signal input terminal 1.

[0010] The above triple speed scanning television signal VID
As shown in Fig. 2, EOIN includes a marker signal (SCAN ID) that sets a specific line within the vertical blanking period to 100% white level once every three fields.
is inserted. The above marker signal (SCAN ID
) are inserted, for example, in a 525-line system such as the NTSC system, as shown in FIG. As shown in FIG. 4, there are 8 lines in the odd field and 321 lines in the even field.

[0011] In this scanning speed conversion device, the first
The triple-speed scanning television signal VIDEOIN supplied to the signal input terminal 1 of
/D) is supplied to the converter 4 and digitized by the A/D converter 3. Triple speed scanning television signal data D digitized by the A/D converter 3
ATA is written into the field memory 5 for odd fields and the field memory 6 for even fields, which are controlled by the memory controller 4 to write and read data.

Further, the triple speed scanning television signal VIDEOIN supplied to the first signal input terminal 1 is as follows:
The signal is supplied to the synchronization separation circuit 8, and the synchronization separation circuit 8 extracts a synchronization signal SYNC×3 for triple-speed scanning. The triple-speed scanning synchronization signal SYNC×3 extracted by the synchronization separation circuit 8 is supplied to a half-H killer circuit 9, a vertical synchronization detection circuit 10, and a phase comparator 11.

The half-H killer circuit 9 removes the equivalent pulse of the vertical synchronization portion of the triple-speed scanning synchronization signal SYNC×3 to form a 3H pulse with a duty ratio of approximately 50%. 3H obtained from this half H killer circuit 9
The pulse is supplied to a 6H pulse generation circuit 12 and a V counter 13, and is also supplied to a comparison control signal generation circuit 15 via a delay circuit 14.

The 6H pulse generation circuit 12 is configured to generate the 3H pulse.
A 6H pulse with a duty ratio of approximately 50% is formed based on the phase of the pulse. The 6H pulse obtained by the 6H pulse generation circuit 12 is supplied to the memory controller 5, vertical synchronization detection circuit 10, V counter 13, and also to the marker detection circuit 16.

The vertical synchronization detection circuit 10 detects the triple speed scanning synchronization signal S at the falling edge of the 6H pulse.
By latching YNC×3, vertical synchronization is detected and a vertical synchronization signal VSYNC is output. The vertical synchronization signal VSYNC obtained by the vertical synchronization detection circuit 10 is supplied to the V counter 13.

The V counter 13 is a counter that uses the 6H pulse as a clock, and uses the vertical synchronization signal VSYN as a clock.
A reset is applied at the C phase, and one round is made at 525 or 625. In this V counter 13, the vertical synchronization signal VS
By latching the above 3H pulse at the falling edge of YNC, the triple speed scanning television signal VIDE
The odd field and even field of OIN are detected to form field identification pulse WO/E. In addition, this V counter 13 selects the count value of the 6H pulse and selects the pulse I which indicates the insertion line of the marker signal ID.
Form a D LINE. The above field identification pulse W O/E and marker insertion line pulse ID LI
NE is supplied to the memory controller 4 and marker detection circuit 16.

In the marker detection circuit 16, the A/D
The most significant bit (MSB) of the triple-speed scanning television signal data DATA digitized by the converter 3
The marker insertion line of the odd field is detected from the field identification pulse WO/E and the marker insertion line pulse IDLINE. The above marker signal is 100
% white level, so the above data DAT
The most significant bit (MSB) of A becomes logic "H". Marker detection pulse ID O by this marker detection circuit 16
DD is supplied to the memory controller 4 and comparison control signal generation circuit 15.

Further, the 3H pulse obtained from the half-H killer circuit 9 is processed by the delay circuit 14 so that the falling edge portion of HSYNC of the triple-speed scanning synchronization signal SYNC×3 is included in logic "H". The clock pulse PKCK is delayed until the clock pulse PKCK is supplied to the comparison control signal generation circuit 15.

The comparison control signal generation circuit 15 frequency-divides the clock pulse PKCK by 1/3, and generates a phase signal once every three lines with respect to the falling edge of the HSYNC of the triple-speed scanning synchronization signal SYNC×3. Comparison control signal PD
Form EN. Note that this comparison control signal generation circuit 15
The 1/3 frequency division operation is reset once every six fields by the marker detection pulse ID ODD from the marker detection circuit 16, and the phase is uniquely fixed.

The phase comparator 11 is supplied with a signal RH obtained by dividing the oscillation output of a voltage controlled oscillator (VCO) 17 by frequency dividers 18 and 19.
A phase-locked loop (PLL) is configured to compare the phase of H and the triple-speed scanning synchronization signal SYNCx3 supplied from the synchronization separation circuit 8, and control the oscillation phase of the VCO 17 using the phase comparison output. It consists of

[0021] In the PLL having such a configuration, the phase comparison is performed using the synchronization signal SYNC x 3 of the triple-speed scanning described above, and one of the three lines.
It is possible to uniquely determine the phase of the signal RH, that is, the H phase of the scanning speed conversion output.

The VCO 17 oscillates at a frequency of 3×M×fH, where M is the number of scanning lines in one frame of the television signal subjected to scanning speed conversion, and a horizontal scanning frequency fH. 18 divides the frequency of the oscillation output of the VCO 17 by 1/3, and the frequency divider 19 divides the frequency of the oscillation output of the VCO 17 by 1/3.
The frequency-divided output of is further divided into 1/M. Above VCO17
The oscillation output of is phase-locked to the synchronization signal SYNC×3 of the triple speed scanning by the operation of the PLL. The oscillation output of this VCO 17 with a frequency of 3×M×fH is used as the write clock WCK (M×3H).
The signal is supplied to the A/D converter 3, the memory controller 3, and each field memory 5, 6. Further, the divided output of the frequency divider 18 that divides the write clock pulse WCK (M×3H) by 1/3 is used as the read clock RCK (M×H) by the memory controller 3 and each field memory 5, 6. Here, the number M of scanning lines in one frame is 52 in the case of the NTSC system.
In the case of the PAL system, the number is 625.

[0023] Then, the memory controller 4 has W
CK (M x 3H), RCK (M x H), RH, ID
Based on ODD, ID LINE, W O/E, etc., as shown in FIG.
Various control pulses (WE-O, WE-
E, WZ-O, WZ-E) and various control pulses for read control (RE-O, RE-E, RZ-O, RZ-E)
R O/E) is formed to control each of the field memories 6 and 7.

Various control pulses (W
E-O, WE-E, WZ-O, WZ-E), the write enable pulse (WE-O, WE-E) is the logic “H
”, and the write enable pulse (WE-O) is the reference television signal REF. The logic becomes "H" during the period corresponding to the odd fields O0, O3, O6, . -E) is the reference television signal REF. VI
The even field E of the triple-speed scanning television signal VIDEO exists on the starting edge side of each odd field O of DEO.
1, E4, E7...
”. Further, among the various control pulses (WE-O, WE-E, WZ-O, WZ-E) for write control, the write zero pulse (WZ-O, WZ-E) is the same as the write enable pulse (WE-E). -O, WE-E) indicates the beginning of the write address of each data written.

[0025] Furthermore, various control pulses for the readout control (RE-O, RE-E, RZ-O, RZ-E, R
O/E), read enable pulse (RE-O,
RE-E) is used to read data during the logic "H" period, and the read enable pulse (RE-O) is the reference television signal REF. The read enable pulse (RE-E) becomes logic "H" during a period corresponding to each odd field O of VIDEO, and the read enable pulse (RE-E) is set to the reference television signal REF. It becomes logic "H" during the period corresponding to each even field E of VIDEO. Furthermore, various control pulses (RE-O, RE-E, RZ-
O, RZ-E, R O/E), the read zero pulse (RZ-O, RZ-E) is the start of the read address of each data read by the read enable pulse (RE-O, RE-E). It shows. In addition, various control pulses (RE-O, RE-E,
Among the clock signals (RZ-O, RZ-E, R O/E), the read clock (R O/E) specifies the odd and even fields on the read side and is used as a control signal for the changeover switch 20. .

The field memory 5 for the odd field receives the control pulse (WE) for the write control.
-O, WZ-O) and the control pulses for read control (RE-O, RZ-O) to control data writing and reading, thereby controlling the reference television signal REF. Triple speed scanning television signal VIDEO present at the end of each even field E of VIDEO
The data of the odd fields O0, O3, O6... are written, and the data of the odd fields O0, O3, O6... are written.
O6 ... data is the above reference television signal RE
F. The odd field data CONV. which is time-axis expanded and read out during the period of each odd field O of VIDEO and whose scanning speed has been converted is read out. It is supplied as OUTODD to the D/A converter 21 via the changeover switch 20.

The field memory 6 for the even field also receives the control pulse (WE-) for the write control.
E, WZ-E) and the control pulse for the readout control (
RE-E, RZ-E) performs data write control and data read control, thereby controlling the reference television signal REF. Triple-speed scanning television signal VIDE present at the start end of each odd field O of VIDEO
Data of even fields E1, E4, E7, etc. of O is written, and these even fields E1, E4
, E7... is the reference television signal R
E.F. The even field data CONV. which is time-axis expanded and read out during the period of each even field E of VIDEO and whose scanning speed has been converted is converted into even field data CONV. It is supplied as OUTEVEN to the D/A converter 21 via the changeover switch 20.

The D/A converter 21 receives scanning speed converted odd field data CONV. which is sequentially supplied via the changeover switch 20. OUTODD and even field data CONV. OUTEVEN is converted into an analog signal, and a television signal VIDEOOUT whose scanning speed has been converted is output from an output terminal 23 via a low-pass filter 22 for interpolation.

The scanning speed-converted television signal VIDEOOUT obtained at the output terminal 23 is based on the data of two consecutive fields O0, E1, O3, E4, etc. of the triple-speed scanning television signal VIDEO on the time axis. Since it is an expanded image, the odd field data and even field data constituting each frame are temporally continuous, and the outline of the moving image will not become step-like.

[0030]

Effects of the Invention In the television signal scanning speed conversion device according to the present invention, the period of the standard television signal inserted into the television signal having a scanning speed that is an odd number (N) times that of the standard television signal. Since a television signal having a scanning speed equal to the above N times the scanning speed is generated based on the generated marker signal, scanning speed conversion can be performed without providing an input terminal for a reference television signal for external synchronization. A television signal synchronized with the marker signal can be generated. Therefore, since the number of external connections can be reduced by one, wiring connections can be simplified.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of the configuration of a television signal scanning speed conversion device according to the present invention.

FIG. 2 is a timing chart showing the operation of the scanning speed converter shown in FIG. 1;

FIG. 3 is a timing chart showing the operation of an NTSC scanning speed converter.

FIG. 4 is a timing chart showing the operation of a PAL scanning speed converter.

[Explanation of symbols]

1...Signal input terminal 2, 22...Low pass filter 3...A/D converter 4...Memory controller 5, 6...Field memory 8...Synchronization separation circuit 9...Half H killer circuit 10... Vertical synchronization detection circuit 11... Phase comparator 12...6H pulse generation circuit 13...V counter 14...Delay circuit 15... Comparison control circuit 16...Marker signal detection circuit 17...VCO 18, 19... Frequency divider 20...Switch switch 21...D/A converter

Claims (4)

[Claims] 1. Detecting a marker signal generated at the cycle of the standard television signal inserted into a television signal having a scanning speed that is an odd number (N) times that of the standard television signal, and detecting the detected marker signal. generates a memory control signal based on the memory control signal, and the writing and reading are controlled by the memory control signal to extend the time axis of the television signal having a scanning rate N times equal to the scanning rate of the standard television signal. A scanning speed conversion device for a television signal, which generates a television signal having a scanning speed. 2. The apparatus for converting the scanning speed of a television signal according to claim 1, wherein the marker signal has a white level of 100%. 3. The apparatus for converting the scanning speed of a television signal according to claim 1, wherein the marker signal is inserted at a position corresponding to a vertical blanking period of the standard television signal. 4. The television signal scanning speed converter according to claim 1, wherein said N is three.