JPH04344420A - Rotation detector - Google Patents

Abstract

PURPOSE:To facilitate back-up with a battery for a long time by minimizing the whole current consumption. CONSTITUTION:A rotation detector takes out a rotational signal by detecting a change in current flowing through two resistance changing elements 11, 12. A timing generating means 18 for intermittently supplying current to the two resistance changing elements is provided so that the change in the current is detected only during a period of intermittent current flow.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a rotation detector used in encoders and the like, which extracts rotation signals by detecting changes in current flowing through two variable resistance elements.

0002

2. Description of the Related Art Conventionally, rotation detectors detect the rotation of a rotating body and are used in encoders and the like.

For example, in recent years, the number of encoders per unit of equipment used in robots and production lines has reached a considerable number. These encoders used to recover when starting up after a power outage, but due to reasons such as the increase in the number of encoders per unit of equipment and the shift to absolute encoders, it has become difficult to recover quickly. Ta. For this reason, the mainstream method has become to back up the encoder with a battery to simplify the restoration work. To back up the encoder with a battery,
It is necessary to sufficiently reduce the current consumption of the encoder.

[0004] Conventionally, an encoder is constructed using a rotating body that is driven to rotate and has magnetic signals recorded thereon, and a rotation detector as shown in FIG. 3 that detects the magnetic signals recorded on this rotating body. There is something that has been done. This rotation detector is composed of variable resistance elements 1 and 2, which are magnetoresistive elements that detect magnetic signals recorded on a rotating body, bipolar transistors 3 and 4, and resistors 5 and 6. , 2 are connected as emitter resistors of bipolar transistors 3 and 4, and a comparator 7 that compares the output voltages of this constant current circuit.

The bias current flowing through the variable resistance elements 1 and 2 is determined by the voltage Vref applied to the bases of the bipolar transistors 3 and 4, and the variable resistance elements 1 and 2 detect magnetic signals recorded on the rotating body. The resistance value changes depending on this magnetic signal. These resistance change elements 1 and 2
The voltage change due to the resistance value change is exponentially amplified by the bipolar transistors 3 and 4 to become a collector current, which is converted into a voltage change by the voltage drop across the resistors 5 and 6, and the difference between these voltage changes is converted into a pulse by the comparator 7. It is converted into signal V0.

[0006]

[Problem to be Solved by the Invention] The above-mentioned rotation detector utilizes a diode characteristic in which fluctuations in the voltage between the base and emitter of the bipolar transistors 3 and 4 are amplified exponentially to the collector current, so the resistance change Element 1,
2 requires a certain amount of large current to flow through it. Further, due to their characteristics, the bipolar transistors 3 and 4 require current to flow between the base and the collector and between the base and the emitter in response to leakage current. For this reason, it is necessary to flow a considerably large current through the resistance change elements 1 and 2, which makes it difficult to back up with a battery and has the disadvantage that the resistance change elements 1 and 2 generate heat and deteriorate their characteristics.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a rotation detector which can improve the above-mentioned drawbacks, can reduce the overall current consumption to an extremely small amount, and can be backed up by a battery for a long time.

[0008]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a rotation detector which extracts a rotation signal by detecting a change in current flowing through two variable resistance elements. The device has timing generation means for causing an intermittent current to flow through the resistance change element, and is configured to detect changes in the current only during the period in which the intermittent current flows.

[0009]

[Operation] The timing generating means causes intermittent current to flow through the two resistance change elements, and a rotation signal is extracted by detecting changes in the current flowing through the two resistance change elements only during the period in which the intermittent current flows. .

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of the present invention. The rotation detector of this embodiment and the recording body (not shown) constitute an encoder, and the recording body is constituted by a rotating disk on which, for example, a sine wave-like magnetic signal is recorded along the rotational direction on the outer circumference. Rotationally driven. Resistance change elements 11 and 12, which are magnetoresistive elements, are arranged opposite to the rotating disk at a predetermined interval, detect magnetic signals recorded on the rotating disk, and change resistance according to the magnetic signals. The value changes. When the rotating disk is rotating, the resistance values of the variable resistance elements 11 and 12 change in a sinusoidal manner according to the sine wave-like magnetic signal recorded on the rotating disk. are arranged at predetermined intervals in the rotational direction of the rotating disk so that the resistance value changes are in opposite phases to each other. P channel M
The OS field effect transistors 13 and 14 constitute a first current mirror circuit, and their sources are connected to a positive DC power supply. The drain of the field effect transistor 13 is connected to the drain of an N-channel MOS type field effect transistor 15, and the gates of the field effect transistors 13 and 14 are connected to the drain of the field effect transistor 15. The field effect transistor 15 is an MO whose gate is a P channel.
It is connected to the drain of the S type field effect transistor 16 and the drain of the N channel MOS type field effect transistor 17, and the source of the field effect transistor 15 is grounded via the variable resistance element 11. The source of field effect transistor 16 is connected to the drain of field effect transistor 15, and the source of field effect transistor 17 is grounded. The gates of the field effect transistors 16 and 17 are connected to the output terminal of the timing generation circuit 18 which outputs the clock Ψ.

Similarly, P-channel MOS field effect transistors 19 and 20 constitute a second current mirror circuit, and their sources are connected to a positive DC power supply. The source of the field effect transistor 20 is connected to the drain of an N-channel MOS type field effect transistor 21, and the gates of the field effect transistors 19 and 20 are connected to the drain of the field effect transistor 21. The field effect transistor 21 has a gate connected to the drain of the P-channel MOS field effect transistor 22 and the drain of the N-channel MOS field effect transistor 23, and the source of the field effect transistor 21 is grounded via the variable resistance element 12. Ru. The source of field effect transistor 22 is connected to the drain of field effect transistor 21, and the source of field effect transistor 23 is grounded. The gates of the field effect transistors 22 and 23 are connected to the timing generation circuit 18.
is connected to an output terminal that outputs the clock Ψ.

Further, N-channel MOS field effect transistors 24 and 25 constitute a third current mirror circuit, and their sources are grounded. Field effect transistor 24
, 25 are connected to the drains of field effect transistors 14 and 19, respectively.
The gates of transistors 4 and 25 are connected to the drain of field effect transistor 19. The connection point between the drain of the field effect transistor 14 and the drain of the field effect transistor 24 is connected to the gate of the latch circuit 26, and the clock input terminal of the latch circuit 26 is an output terminal for outputting the clock φ of the timing generation circuit 18. is connected, and a rotation signal is output from the output terminal OUT of the latch circuit 26.

In this embodiment, the drive ability β of the MOS field effect transistor is determined by the ratio W/L of the process constant, channel width W, and channel length L. The process constants of all P-channel MOS field effect transistors and all N-channel MOS field effect transistors are the same unless special processing such as ion implantation is performed. Therefore, two M of the same type
The ratio of the drive ability β of the OS type field effect transistor is W
/L is determined. Generally, since L is constant, the β ratio is easily determined by W. In the above current mirror circuit,
The gate voltages Vgs of the two field effect transistors are the same, and the current ratio of the two field effect transistors is equal to the β ratio. The characteristics of the MOS field effect transistor in the saturation region can be expressed as Id=β(Vgs−Vth)2 (1), where Id is the drain current of the MOS field effect transistor.

In the saturated conduction state, the P-channel MOS field effect transistor 13 has a source-gate voltage Vgs.
1 is determined by the current Id1, and if the drive ability of the P-channel MOS field effect transistor 13 is β1, then Vgs1=Vth/(Id1/β1)2...
(2) becomes. On the other hand, the gate voltage of the P-channel MOS field effect transistor 14 is
3, the current Id2 flowing through the field effect transistor 14 is equal to the gate voltage of the field effect transistor 14.
Substituting equation (1) into equation (2) with the drive capacity of β2 as β2, Id2=(β2/β1)Id1...(3)
becomes. β ratio (β2
/β1) is the W ratio (W2/W1), so Id2=(
W2/W1) Id1 (4). W2:W
If 1=1:n, then the drain current of the field effect transistor 14 is n times the drain current of the field effect transistor 13. For example, W of the field effect transistor 13
is 2 μm, and W of the field effect transistor 14 is 100 μm.
m, the drain current of the field effect transistor 14 is 50 times the drain current of the field effect transistor 13.
Double.

When the field effect transistor 15 is in a conductive state, the drain current of the field effect transistor 13 flows through the field effect transistor 15 and the variable resistance element 11 and depends on the resistance value of the variable resistance element 11. Therefore, the current of the variable resistance element 11 i1 is amplified by a current mirror circuit consisting of field effect transistors 13 and 14. Further, the ratio of the channel width W3 of the field effect transistor 19 and the channel width W4 of the field effect transistor 20 is 1:1, and the ratio of the drive ability β3 of the field effect transistor 19 to the drive ability β4 of the field effect transistor 20 is 1:1. :1, and the drain current of the field effect transistor 19 and the drain current of the field effect transistor 20 are equal. When the field effect transistor 21 is in a conductive state, the drain current of the field effect transistor 20 flows through the field effect transistor 21 and the variable resistance element 12 and depends on the resistance value of the variable resistance element 12. Therefore, the current i2 of the variable resistance element 12 is caused by the electric field. It is outputted via a current mirror circuit consisting of effect transistors 19 and 20.

If the ratio of the channel width W5 of the field effect transistor 24 to the channel width W6 of the field effect transistor 25 is n:1 (for example, 25:1), then the drive capability β5 of the field effect transistor 24 and the channel width W6 of the field effect transistor 25 are The ratio of the current i4 to the drive capability β6 is n:1 (for example, 25:1), and the current i4 of the field effect transistor 24 is n times the current i3 of the field effect transistor 25. In the conductive state of the field effect transistors 15 and 21,
The current i1 of the variable resistance element 11 is the current i1 of the field effect transistor 1.
Amplified by a current mirror circuit consisting of 3 and 14,
The current i2 of the variable resistance element 12 is the current i2 of the field effect transistor 1.
The signal is amplified by a current mirror circuit including field effect transistors 24 and 25 via a current mirror circuit including field effect transistors 9 and 20.

Current i1 flowing through the magnetoresistive elements 11 and 12
, i2 is caused by the field effect transistors 14, 2
4, and the gate state of the latch circuit 26 is determined by this unbalanced state and the charge state of the gate capacitor of the latch circuit 26. The latch circuit 26 latches the gate state in synchronization with the clock φ from the timing generation circuit 18.

The field effect transistor 15 receives the clock Ψ from the timing generation circuit 18 from the field effect transistor 16.
, 17, it is controlled to be in a conductive state or a cut-off state. Similarly,
The field effect transistor 21 is controlled to be in a conductive state or a cutoff state by receiving input from the clock Ψ timing generation circuit 18 via a level shifter made up of field effect transistors 22 and 23. All amplifier circuits other than these level shifters are current amplification circuits using current mirror circuits, so when the field effect transistors 15 and 21 are cut off, the currents i1 and i2 become approximately 0 [A], and the overall power of this circuit is reduced. The current also becomes approximately 0 [A]. In reality, the current does not completely become 0 [A] due to the leakage current of the field effect transistor, but the leakage current of the field effect transistor is generally extremely small, 1 [nA] or less. The clocks φ and φ that control the activation time of the entire circuit are generated by the timing generation circuit 18 according to a certain time rule.

Next, the operation of this embodiment will be explained using the waveforms shown in FIG. First, the magnetoresistive elements 11 and 12 detect sinusoidal magnetic signals recorded on the rotating disk, and as the rotating disk rotates, the resistance values change in a sinusoidal manner with opposite phases to each other. This change in the resistance value of the magnetoresistive elements 11 and 12 is directly reflected in the currents i1 and i2, and the drain currents of the field effect transistors 13 and 20 change minutely. , 25. As shown in FIG. 2, the clocks φ and ψ generated by the timing generation circuit 18 vary from 0 [V] (hereinafter referred to as LO) to the power supply voltage Vdd (
It is assumed that the signal is a digital signal having an amplitude up to HI (hereinafter referred to as HI). Furthermore, it is assumed that the clock Ψ is a negative logic clock and a notch-shaped pulse. Clock φ is a positive logic clock, and the fall of clock φ occurs after a predetermined setup time has elapsed from the fall of clock Ψ, and the rise of clock Ψ occurs after a predetermined hold time has elapsed from the fall of clock φ. It shall be later. These setup times and hold times depend on various parameters of the circuit (especially the β ratio of the field effect transistors 14 and 24, and the gate capacitor of the latch circuit 26), and can be determined at the time of circuit design.

Now, if the clock Ψ becomes LO, the field effect transistors 17 and 23 are cut off (hereinafter referred to as off), and the field effect transistors 16 and 2 are turned off.
2 enters a saturated conduction state (hereinafter referred to as on), and field effect transistors 15 and 21 turn on. At this time, the field effect transistors 15 and 21 are applied with bias voltages depending on the resistance values of the variable resistance elements 11 and 12, respectively, and become conductive. As mentioned above, current i1 is amplified by field effect transistors 13 and 14, and current i2 is amplified by field effect transistors 20 and 19 and field effect transistors 25 and 24. These field effect transistors 13, 14, field effect transistors 20, 1
9. The field effect transistors 25 and 24 each constitute a current mirror circuit, and the difference between the current i1 and the current i2 is finally reflected in the field effect transistors 14 and 24.

If i1>i2, the supply current of field effect transistor 14 exceeds the sink current of field effect transistor 24. The excess current is transferred to the latch circuit 26.
The gate capacitor of the latch circuit 26 is charged, and the gate voltage V0 of the latch circuit 26 is increased. This state is the state at times A, C, . . . in FIG. When V0 rises sufficiently and exceeds the logic threshold level of the latch circuit 26, the clock φ is turned off and the latch circuit 26 becomes HI.
Latch.

On the other hand, if i1<i2, the supply current of the field effect transistor 14 is insufficient with respect to the sink current of the field effect transistor 24, and this shortage is compensated by the charge of the gate capacitor of the latch circuit 26, and V0 descends. This state is the state at time B in FIG. When V0 falls sufficiently to be below the logic threshold level of latch circuit 26, clock φ is turned off and latch circuit 26 latches LO.

Now, when the clock Ψ becomes HI, the field effect transistors 17 and 23 are turned on, the field effect transistors 16 and 22 are turned off, and the field effect transistors 15 and 21 are turned off. At this time, the gate voltages V1 and V2 of the field effect transistors 15 and 21 become 0 [V], the field effect transistors 15 and 21 are turned off, and i1 and i2 become 0 [A]. However, in reality, leakage current flows through the field effect transistors 15 and 21;
This is an extremely small amount of 1 [nA] or less. i1
, i2 becomes 0 [A], the current of the entire circuit also becomes almost 0 [
A]. This is actually several tens [nA] to several hundred [nA].
nA]. At this time, the source current i4 of the field effect transistor 24 also becomes 0 [A], and V0 becomes an undefined value from a digital signal perspective, and it is necessary to prevent this from being output to the outside. The latch circuit 26 is provided to realize this, and is designed to continue to hold the valid rotation signal when the clock ψ is LO while the clock ψ is HI, and from the output terminal OUT as shown in FIG. A pulse-like rotation signal as shown in is output.

The responsiveness of this circuit to the clock Ψ is faster than the power on/off of a light emitting diode or operational amplifier, although it depends on the setup time setting, so the pulse width of the clock Ψ is set to 10 [μS], for example. It can be done. The period of the clock Ψ can be determined based on the responsiveness to the rotation of the rotating body required of the system. If R rotations per second are required for the rotation of the rotating body, one clock Ψ is required for at least one half revolution of the rotating body, so the period T of the clock Ψ can be determined by the following equation. T=1/(2R) For example, when the rotation of the rotating body is 3000 [rpm], T=10 [mS].

Now, the period of clock Ψ is T, and clock Ψ
If the pulse width of is t, the current consumption of the entire circuit when the clock Ψ is LO is I, and the leakage current of the entire circuit when the clock Ψ is HI is i, then the average current consumption I' is as follows. . I'={tI+(T-t)i}/T≈(t/T)I However, i≪I. For example, T=10 [mS], t=10 [μS], I=2
[mA], I'≈2 [μA]. Therefore, if this circuit is backed up by a battery with a capacity of 200 [mAH], it will continue to operate for approximately 11 years and 5 months.

According to this embodiment, the variable resistance elements 11,
Even if the current of 12 is very small, it can be easily controlled as necessary by β2/β1 and β6/β5 using a current mirror circuit consisting of field effect transistors 13 and 14 and a current mirror circuit consisting of field effect transistors 24 and 25. The currents i1 and i of the resistance change elements 11 and 12 can be amplified to
2 can be easily lowered to such an extent that the variable resistance elements 11 and 12 do not generate heat. Also, this circuit is a MOS
Since it is constructed using type field effect transistors, it is suitable for semiconductor integrated circuits, and operates like a CMOS, so current consumption can be reduced. In particular, it has good compatibility with CMOS digital circuits, and can be easily connected to subsequent stages.
It is also possible to make it into a chip. Resistance change element 11,1
2 is manufactured by applying semiconductor process technology, the relative characteristics of the pair of variable resistance elements 11 and 12 are relatively good,
This is a characteristic suitable for semiconductor integrated circuits. Therefore, by using a semiconductor integrated circuit incorporating such variable resistance elements 11, 12, MOS field effect transistors, etc., it is possible to create a circuit without adjustment.

By the way, in the above embodiment, if the field effect transistors 15 and 21 are left on without being turned on/off, the idle current i4 flowing through the field effect transistor 24 will be the value after amplification of i1 or i2. Since the current is equally large, the current consumption of the entire circuit remains large at all times, and long-term battery backup is impossible. However, timing generation circuit 1
The field effect transistor 15,
21 is turned on and off to cause an intermittent current to flow through the resistance change elements 11 and 12, changes in the current are detected only during the current flowing period, and a rotation signal is extracted. Therefore, the current consumption of the entire circuit can be reduced to an extremely small current. This enables long-term battery backup.

[0028] In the above embodiment, the P channel MO
S type field effect transistor 13, 14, 16, 19, 2
0 and 22 may be N-channel MOS field effect transistors, and N-channel MOS field effect transistors 15, 17, 21, 23, 24, and 25 may be P-channel MOS field effect transistors. Furthermore, the above-mentioned MOS field effect transistor is an MIS (Metal Insulator) other than a MOS field effect transistor.
er Silicon) type field effect transistors may also be used. This MIS type field effect transistor is a MOS
type field effect transistor. Further, as the resistance change elements 11 and 12, elements may be used that detect physical changes such as optical changes other than the magnetic changes due to the rotation of the rotating body, and change the resistance value according to the physical changes. ,
Alternatively, it may be possible to detect a physical change amount other than the signal recorded on the rotating body. Furthermore, the present invention may be applied to a circuit that samples optical pulses using CdS elements as the variable resistance elements 11 and 12.

[0029]

As described above, according to the present invention, in a rotation detector which extracts a rotation signal by detecting a change in the current flowing through two variable resistance elements, the two variable resistance elements are connected intermittently to each other. The present invention has a timing generating means for causing a current to flow, and is configured to detect changes in the current only during the period in which the current flows intermittently, so that the overall current consumption can be reduced to an extremely small current. Enables long-term battery backup.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

FIG. 2 is a timing chart showing the operation timing of the same embodiment.

FIG. 3 is a circuit diagram showing a conventional rotation detector.

[Explanation of symbols]

11, 12 Resistance change elements 13 to 17, 19 to 25 MOS field effect transistor 18 Timing generation circuit 26 Latch circuit

Claims (1)

[Claims] Claims: 1. A rotation detector which extracts a rotation signal by detecting changes in current flowing through two variable resistance elements, comprising timing generation means for causing an intermittent current to flow through the two variable resistance elements. and a rotation detector configured to detect changes in the current only during periods in which the current flows intermittently.