JPH0434383A - Integrated circuit having testing circuit - Google Patents

Abstract

PURPOSE:To measure the characteristics of a function block estimated in a planning stage by mounting a selector selecting either one of an output signal from a functional aspect and the input signal supplied from the outside to output the same. CONSTITUTION:When the change-over signal of a delay time measuring mode supplied from an input pin 3 is set to a low level, the output signals outputted from terminals 2a, 2b become the almost same logic as the output signal outputted at the time of the original operation of a mega-macroscopic cell 1. Therefore, the states of the terminals 2a, 2b at the time of the original opera tion of the cell 1 are outputted to output pins 11a, 11b. When the change-over signal of the delay time measuring mode supplied from the pin 3 is set to a high level, the output signals outputted from the terminals 2a, 2b become the almost same logic as the input signal for measuring a delay time supplied from an input pin 6. Therefore, the input signal for measuring the delay time is outputted to the pins 11a, 11b in the same logic so as to contain a predetermined delay time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit having a plurality of functional blocks and a test circuit for the functional blocks, and particularly to an integrated circuit having a test circuit suitable as a standard cell type integrated circuit. Concerning integrated circuits.

[Conventional technology] Conventionally, standard cell type integrated circuits (LSI)
It is constructed by interconnecting one or more mega macrocells whose mask layout is designed as a relatively large standard functional block and one or more user macrocells which are constructed by combining a plurality of standard basic cells. .

In this way, in a standard cell type integrated circuit configured by wiring a mega macrocell and a user macrocell, all terminals of each macrocell can be connected to external terminals (hereinafter referred to as pins) of the LSI depending on the mode setting. Assign and connect to test each macrocell individually through this pin. Let's use this test method as a macro separation test.

FIG. 4 is a block diagram showing a conventional integrated circuit. Input signals input from input pins 34a and 34b are sent to mega macrocell 32 via manual buffers 35a and 35b, respectively.
input terminal IN1. Input to IN2. The output signals output from the output terminals 0UT1 and 0UT2 of the mega macro cell 32 are respectively output from the input terminal IN1 of the user macro cell 33.
．． Input to IN2. The output signals output from the output terminals 0UTI and 0UT2 of the user macrocell 33 are outputted from the output pins 37a and 37a through the output buffers 36a and 38b, respectively.
37b.

FIG. 5 is a block diagram showing an integrated circuit provided with a test circuit for macro separation. In this case, in order to simplify the explanation, only the test circuit for macro-separating the mega-macro cell 32 is shown, and the same parts as in FIG. .

In FIG. 5, a user macro cell 43 indicated by a broken line is a user macro cell 33 and a test circuit (selector) 42a, 4
2b. The output signals output from the output terminals 0UT1.0UT2 of the mega macro cell 32 are input to the input terminals INI and IN2 of the user macro cell 33, respectively, and are input to the S terminals of the test circuits 42a and 42b. Output terminal 0UT1 of user macrocell 33
The output signals output from 0UT2 are input to the S terminals of test circuits 42a and 42b, respectively. These test circuits 42a, 42b are configured to switch the S input to O when not in the separation mode.
The S input is output from the O terminal when in separation mode.

In an integrated circuit having a test circuit configured as described above, when not in the separation mode, the test circuits 42a, 4
Since the input selection of 2b is on the S terminal side, Figures 4 and 5
The circuits in the figure are logically approximately equivalent. On the other hand, in the separation mode, since the input selection of the test circuits 42a and 42b is on the S terminal side, the output terminals 0UT1.
The output signal of 0UT2 is output to the output pin 37a via test circuits 42a, 42b and output buffers 38a, 36b, respectively.
, 37b.

Therefore, all the input/output terminals INI of the mega macrocell 32
, IN2, 0UTI, 0UT2 are input/output pins 34a,
34b, 37a, and 37b. In such a separate mode, megamacro cells 32 can be tested individually.

[Problems to be Solved by the Invention] However, in the integrated circuit having the conventional test circuit described above, the output terminal 0UT of the mega macrocell 32
I,0UT2 is output pin 37a.

Although it is logically coupled to 37b, mega macrocell 3
It is not possible to observe the timing of signal changes at the output terminals 0UTI and 0UT2 of 2, that is, the delay characteristics. Specifically, the output terminals 0UTI, 0 of the mega macrocell 32
After the signal changes in UT2, output pins 37a, 3
7b, the intervening wiring, test circuits 42a, 42b and output buffers 38a, 3E! A delay time occurs due to the signal propagation of b. Therefore, in the integrated circuit having the above-mentioned test circuit, there is a problem that it is not possible to test whether the mega-macro cell 32 incorporated in the circuit satisfies the characteristics expected at the design stage.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide an integrated circuit having a test circuit capable of measuring expected characteristics of functional blocks at the design stage.

[Means for Solving the Problems] An integrated circuit incorporating a test circuit according to the present invention includes a plurality of functional blocks connected in series between an input terminal and an output terminal, and a selection of these functional blocks. and a test circuit individually connected between the input terminal and the output terminal, wherein the functional block receives either one of its functional output signal or an externally supplied input signal. It is characterized by having a selector for selecting and outputting.

[Operations] In the present invention, when measuring the characteristics of a functional block in an integrated circuit, the functional blocks are individually connected between an input terminal and an output terminal via a test circuit, and By controlling the selected selector, the functional block outputs its functional output signal. Then, the functional blocks are individually tested using the input terminals and output terminals. In this case, the delay characteristics of the functional block measured by this test include delay time due to signal propagation in the test circuit, wiring, etc. interposed between the output end of the functional block and the output terminal. Therefore, by controlling the selector, an input signal supplied from the outside is outputted from the functional block, and the delay time of this signal is measured. Although this delay time includes the delay time due to the test circuit etc. mentioned above and the delay time due to the selector and its wiring, the latter is extremely small (can be ignored) compared to the former. as,
By measuring the delay times of both signals selected by the selector, the delay characteristics at the output end of the functional block can be calculated. This allows the characteristics of the functional block expected at the design stage to be measured.

[Embodiments] Next, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an integrated circuit having a test circuit according to a first embodiment of the present invention.

The mega macrocell 1 constituting the functional block inputs an input signal to a predetermined input terminal (not shown) and outputs its functional output signal from output terminals 2a and 2b. Further, the delay time measurement mode switching signal supplied from the input bin 3 is inputted to the input terminal 5 of the mega macrocell 1 via the input buffer 4.

On the other hand, the input signal for delay time measurement supplied from the input bin θ is directly input to the input terminal 7 of the mega macrocell 1. Then, the mega macrocell 1 transmits either the functional output signal or the delay time measurement input signal to the output terminal 2 in accordance with the delay time measurement mode switching signal.
It is designed to output to a + 2 b. The output signal of this mega macro cell 1 is input to a user macro cell 8 forming a functional block. The output signal of the user macrocell 8 is output to output bins 11a and 11b via output buffers 10a and 10b. Further, the input signal of the user macrocell 8 is outputted via the test circuit 9a+9b instead of the internal circuit of the user macrocell 8, depending on the mode setting, as in the conventional circuit. That is, when performing a separate test on mega-macro cell 1, mega-macro cell 1
Output terminal 2 a! The output signal outputted from 2b is outputted from output bins 11a and 11b with the same logic through test circuits 9a and 9b.

FIG. 2 is a circuit diagram showing an extracted functional block (mega macro cell 1) of an integrated circuit having the above-mentioned test circuit.

The mega-macro cell 1 is designed as a standard layout block, and a mega-macro cell 21 having a predetermined function is arranged therein. The mega macro cell 21 inputs an input signal to a predetermined input terminal (not shown), and outputs the functional output signal to output terminals 0UTI and 0UT.
Output from 2. 4 person AND10R game) 22a, 2
2b inputs the output signal of the mega macrocell 21 and the delay time measurement mode switching signal inputted from the input terminal 5 via the inverter 23, and also inputs the input signal for delay time measurement inputted from the input terminal 7. and the delay time measurement mode switching signal input from input terminal 5,
Depending on the switching signal, either the output signal of the mega macro cell 21 or the input signal for measuring the delay time is outputted from the output terminals 2 a +2b. That is, when the input terminal 5 is at a low level, the output terminals 2a + 2b have substantially the same polarity as the output terminals 0UT1.0UT2 of the mega macrocell 21. On the other hand, when input terminal 5 is at high level,
The input signal for measuring the delay time input from the input terminal 7 is outputted to the output terminals 2a and 2b, including the delay time between these terminals.

Next, in the integrated circuit having the test circuit described above,
The operation when the test circuits 9a and 9b are used to separate the mega-macro cell 1 and test the mega-macro cell 1 individually will be described.

First, when the delay time measurement mode switching signal supplied from the input bin 3 is set to low level, the output signals output from the output terminals 2a and 2b are approximately the same as the output signals output during the original operation of the mega macrocell 1. It becomes the same ring. Therefore, the output bin 11a.

11b, the state of the output terminals 2 a r 2 b when the mega macro cell 1 is performing its original operation is output. However, at this time, the signals observed at the output pins 11a and 11b are the signals observed at the output terminal 2a.

After the output signal of 2b changes, the test circuit 9a, 9b1 output buffer 10a v 1 interposed in the signal propagation path
0 b and wiring delay time (this delay time is T.T
i1ST) will change after the lapse of time. That is, assuming that the delay time from the input pin (not shown) of the integrated circuit to the output terminal 2a + 2b is TD2, the delay time TD11 observed at the output pins 11a and 11b is expressed by the following equation (1). .

TDI□ = T D2+ T otgs
... (1) Next, when the delay time measurement mode switching signal supplied from the input bin 3 is set to high level, the output signal output from the output terminals 2 a r 2 b is as follows.
This is approximately the same as the input signal for delay time measurement supplied from the input bin 8. Therefore, the input signal for delay time measurement is outputted to the output pins 11a and 11b in its original logic including a predetermined delay time. The propagation of the input signal for delay time measurement input to this input bin 6 is transmitted to the output bin 11.
The delay time 're-' until it is observed at a, 11b
tx is expressed by the following formula (2).

T e−,s = T MMAC+ T 0TEST
(2) However, THH4° is the signal propagation delay time from the input pin 6 to the output bin 2 a +2b.

In this way, the delay time T8-11 and TDI□ can be measured by setting the input signal for delay time measurement supplied from the input bin 6 to high or low level.

Note that the delay time TM□. is expressed by the following formula (3).

T, □. =TθIN+T2□...(3) However,
Taxs is the wiring delay time from the input bin 6 to the input of the 4-man power AND10R gates 22a and 22b in the mega macro cell 1, and T2□ is the 4-man power AND10R gate 22
This is the delay time from the inputs of a and 22b to the output terminals 2a and 2b. Also, from the above formulas (2) and (3), T8-1
□ is expressed by the following formula (4).

To−■= TotEsr +TIIIN + T22
- (4) Furthermore, from the above equations (1) and (4), the following (5
) formula is obtained.

T, □-Te-11 "TO2T-08-T2□ ... (5) Here, the delay time T GIN is the delay time only for wiring, and the input bin 6 is connected to a device with extremely high drive ability (for example, ,
Since the signal is supplied by an LSI tester), the delay time T8 is usually negligible compared to the delay time TO2, which includes gate delay times of several stages. Therefore, the above equation (5) can be expressed by the following equation (6).

TDl, -Tll-II"FTD2 T22 -
(6) If the relationship between the delay time TD2 and the delay time T2□ is expressed by the following equation (7), the above equation (8) is expressed by the following equation (8).

T D2> T 2□ ...(7) TD
Nagasaki TDII -T's-t□ ...(8) Therefore, under the condition that the above formula (7) holds true, that is, 4-man power AND
In the case where the gate delay time T2□ of the 10R gates 22a and 22b can be ignored compared to the delay time TD2 of the mega macrocell 1, the connection between the input bin (not shown) of the integrated circuit and the output pins 11a and llb. delay time TD between
I□, and input pin 6 and input pin output pin 1! a, 11
By measuring the delay time T6-□1 between
Delay time T of mega macrocell 1 at output terminals 2a and 2b. 2 can be calculated from the above equation (8). This makes it possible to measure the characteristics of the mega-macro cell 1 expected at the design stage.

FIG. 3 is a circuit diagram showing extracted functional blocks of an integrated circuit having a test circuit according to a second embodiment of the present invention. In FIG. 3, the same parts as those in FIG. 2 are given the same reference numerals, and detailed explanations of those parts will be omitted.

A mega macro cell 21 having a predetermined function is arranged inside the mega macro cell 1a.

This mega macro cell 21 inputs an input signal to a predetermined input terminal (not shown), and outputs the output signal to an output terminal 0UT.
1.0 Output from UT2. The output signal of the mega macro cell 21 is outputted from output terminals 2a and 2b via transfer gates 24a and 24b. The input signal for delay time measurement input from the input terminal 7 is a transfer gate)2
It is outputted from output terminals 2a and 2b via 5a and 25b.

The delay time measurement mode switching signal input from the input terminal 5 is transferred to the transfer gate 24 via the inverter 23.
It is input to the gates of transfer gates 25a and 24b, and directly to the gates of transfer gates 25a and 25b. transfer game) 24a, 24b, 25a, 25
b conducts the signal when its gate input is at a low level, and cuts off the signal when its gate input is at a low level. Therefore, when the delay time measurement mode switching signal input from the input terminal 5 is at a low level, the gates 24a and 24b are conductive, and the gates 25a and 2
5b is cut off, the output terminals 2a and 2b have the same logic as the output terminals 0UT1.0UT2 of the mega macrocell 21. On the other hand, when the delay time measurement mode switching signal input from the input terminal 5 is at the 71 level, the output terminals 2a and 2
An input signal for measuring delay time inputted from the input terminal 7 is outputted to b.

In this embodiment, since the selector for selecting the output signal of the mega-macro cell 21 and the input signal for delay time measurement is constituted by a transfer gate, the number of elements constituting this selector is compared to that in the first embodiment. can be reduced. Furthermore, when inputting an input signal for delay time measurement from the input pin 8 to the input terminal 7 in the same manner as in the first embodiment, the conditional expression shown in the above equation (7) is as follows (
9) It is expressed by the formula.

T D2>725 (9) However, T25 is the delay time from the input of the transfer gates 25a, 25b to the output terminals 2a, 2b.

Therefore, similarly to the first embodiment, the delay times T5-st and Tn under the condition that the above equation (9) holds true.
By measuring +□, the delay time TD2 of the mega macrocell 1a at the output terminals 2a and 2b can be determined from the above equation (8). In addition, in the case of a selector constituted by a transfer gate in this way, the delay time T25 is
This can be expressed as the time during which the input signal for delay time measurement supplied from a drive device with high drive ability directly passes through the transfer gates 25a and 25b when they are conductive, and is generally a smaller value than the delay time T2□. Take. Therefore, according to this embodiment, the characteristics of the mega-macro cell 1a expected at the design stage can be measured with higher accuracy than in the first embodiment.

Effects of the Invention As explained above, according to the present invention, the functional block is equipped with a selector that selects and outputs either the functional output signal or the input signal supplied from the outside. Delay time due to signal propagation in a test circuit can be measured. Therefore, the delay characteristics at the output end of the functional block can be calculated, and the expected characteristics of the functional block at the design stage can be measured. Thereby, the present invention has the effect of being able to improve the test accuracy of integrated circuits.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an integrated circuit that performs a test circuit according to the first embodiment of the present invention, FIG. 2 is a circuit diagram showing extracted functional blocks of the integrated circuit, and FIG. FIG. 4 is a block diagram showing a conventional integrated circuit, and FIG. 5 is a block diagram showing an integrated circuit having a conventional test circuit. It is a diagram. L la, 21; Mega Macro Cell, 2 a + 2
b; Output terminal, 3.8+ 34a+ 34b; Input pin, 4.35a, 35b; Input buffer, 5, 7; Input terminal, 8, 43; User macro cell, 9a, 9b, 42
a, 42b; test circuit, 10a, 10b+ 36a,
36b; output buffer, lla, 11b, 37a, 37
b; Output pin, 22a, 22b; ANDOR gate, 2
3; Inverter, 24a, 24b, 25a, 25b;
) Transfer gate diagram t 24o, 24b, 25a, 25b. Mecha 7 black beggar F ransuf 7'7-h Fig.

Claims (1)

[Claims] (1) A plurality of functional blocks connected in series between an input terminal and an output terminal, and a test circuit that selects these functional blocks and connects them individually between the input terminal and the output terminal. An integrated circuit having a test circuit, wherein the functional block has a selector that selects and outputs either one of its functional output signal and an externally supplied input signal. .