JPH04343518A - Input circuit - Google Patents

Abstract

PURPOSE:To improve the breakdown strength of an input circuit to a signal inputted from the external and to expand the selection width of external devices to be connected to a signal input terminal. CONSTITUTION:This input circuit is provided with an NMOS transistor(TR) N2 for receiving an external signal S by a source electrode and transmitting the signal S from a drain electrode to an input buffer 3. The maximum potential level of a signal inputted from the gate electrodes of a PMOS TR P1 and an NMOS TR N1 in the buffer 3 are limited to a high level power supply voltage VDD or less by fixing gate potential to the voltage VDD. When a pull-up PMOS TR P2 is connected between the drain electrode of the TR N2 and a high level power supply terminal 6, a through current in the buffer 3 is reduced even when the potential level of the signal S is close to the logical threshold of the buffer 3, and logic can more correctly judged.

Description

[Detailed description of the invention]

0001

[Industrial Field of Application] The present invention relates to an input circuit, and in particular to an M input circuit.
The present invention relates to an input circuit configured using OS field effect transistors.

0002

2. Description of the Related Art A conventional input circuit will be explained with reference to FIG. FIG. 2 is a circuit diagram schematically showing an example of a conventional input circuit installed on a semiconductor integrated circuit chip (hereinafter referred to as a chip). This is what I drew. FIG. 2(b) is a drawing of FIG. 2(a) at the transistor level.

Referring to FIG. 2(a), this input circuit consists of an input buffer 3 composed of a two-input NAND circuit 1 and an inverter 2 connected in series to the NAND circuit 1. One input terminal of the two-input NAND circuit 1 is connected to the signal input terminal 4, to which a signal S is input from outside the chip 5. Further, an input permission signal C is inputted to the other input terminal of the NAND circuit 1 from another circuit inside the chip 5. The output from the inverter 3 is input to other logic circuits inside the chip 5.

This input circuit outputs a signal from the inverter 2 that is in phase with the external signal S input to the signal input terminal 4 when the input enable signal C to the NAND circuit 1 is at a high level. On the other hand, when the input permission signal C is at a low level, the output of the inverter 2 is always at a low level regardless of the input signal from the outside, so the signal S is cut off.

[0005] Now, consider which part of the transistors constituting the input buffer 3 the signal S to the signal input terminal 4 is input to. FIG. 2(b) shows a case where FIG. 2(a) is constructed using CMOS transistors, as an example. Referring to FIG. 2(b), an external signal S input to the signal input terminal 4 is a P-channel MOS field effect transistor (hereinafter referred to as PM
(denoted as OS transistor) P1 and N-channel M
It is directly input to the gate electrode of an OS field effect transistor (hereinafter referred to as an NMOS transistor) N1.

As described above, the conventional input circuit is configured such that the signal S from the outside is directly input to the gate electrode of the CMOS transistor constituting the NAND circuit 1. The circuit configuration of the NAND circuit 1 is not limited to the CMOS transistor configuration, but there are various circuit configurations such as those configured only with NMOS transistors or those configured only with PMOS transistors. A signal S is directly input to the gate electrode of the MOS transistor.

[0007]

[Problems to be Solved by the Invention] However, in recent years, with the remarkable progress in semiconductor device manufacturing technology, devices formed on integrated circuit chips have become more and more popular as a means of making chips smaller, lowering power consumption, and increasing speed. It has become extremely miniaturized as a single means. Also in MOS transistors,
Along with the miniaturization of gate length and gate width, the thickness of the gate oxide film has also been reduced to about 20 to 30 nm, and M
The gate breakdown voltage of OS transistors tends to decrease. As a result, in the case of a circuit configuration such as a conventional input circuit in which an input signal from the outside is directly input to the gate electrode of a MOS transistor, dielectric breakdown of the gate oxide film of the MOS transistor may occur depending on the level of the input signal. The problem is that this occurs.

In particular, an integrated circuit using a power supply system with a higher potential than that of the input circuit or a device such as a sensor is connected to the outside of the input circuit, so that a high potential signal is input to the signal input terminal 4. Considering such a case, a drop in the gate breakdown voltage of a MOS transistor is fatal, and although a sufficient breakdown voltage was obtained using a conventional input circuit, the new manufacturing process causes destruction of the gate oxide film. , there is a very high possibility that a chip using this input circuit will become unusable.

The present invention has been made in view of the above-mentioned problems, and it is an object of the present invention to provide an input circuit that can be used even with input signals of a higher level than in conventional input circuits.

0010

Means for Solving the Problems The input circuit of the present invention includes an N-channel MOS field effect transistor whose source electrode is connected to a signal input terminal and whose gate electrode is connected to a high-level power supply terminal; It is characterized by having an input buffer that receives the potential of the drain electrode of the effect transistor.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a preferred embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing an input circuit according to an embodiment of the present invention at a CMOS transistor level.

Referring to FIG. 1, this embodiment is different from the conventional input circuit shown in FIG. , a pull-up PMOS transistor P2 provided between the drain electrode of the NMOS transistor N2 and the high-level power supply terminal 6.
Another feature is that an inverter 7 is provided for controlling the conduction state of this PMOS transistor P2 using an input permission signal C. The NMOS transistor N2 has a high breakdown voltage structure that increases the PN junction breakdown voltage between the source electrode and the P-type substrate or P-well, and has been put into practical use in the past.

In this embodiment, the NMOS transistor N2 is always in an on state because its gate potential is fixed to the high power supply voltage VDD. Therefore, the external signal S input to the signal input terminal 3 is input to the source electrode of the NMOS transistor N2, output from the drain electrode, and input to the input buffer 3. In this case, the NMOS transistor N2 is Since the gate potential is fixed to the high power supply voltage VDD, a voltage higher than this voltage is not output to the drain electrode. Therefore, PMOS transistors P1 and N of input buffer 3
The gate oxide film of MOS transistor N1 is not destroyed.

Next, the operation of the pull-up PMOS transistor P2 will be described. This MOS transistor is used to reduce the through current in the input buffer 3 compared to the case where only the NMOS transistor N2 is provided, and to enable more accurate logic determination.

Now, the potential level VS of the signal S and NMO
The relationship between the output level of the S transistor N2 (potential level of the drain electrode) VD is as follows, where VT is the threshold voltage of the NMOS transistor N2, and α is the back gate characteristic. There is. That is, the input buffer 3 receives a signal having a potential level (VD) lower than the potential level (VS) of the external signal S.

Now, if we consider the case where a signal with a potential level close to the logic threshold of the input buffer 3 is input as the external signal S, as can be seen from the above relational expression, the input buffer It may become difficult to judge the logic in input buffer 3, resulting in malfunction, or a large through current may flow through the CMOS transistor of input buffer 3. Considering the above, the potential level of the external signal S (
VS), the potential level (VD) of the signal input to the input buffer 3, and the high-level power supply voltage (VDD) preferably satisfy the following relationship at the same time. ■VS <VDD, VD =VS■VS >VD
In the case of D, VD = VDD Therefore, a pull-up PMOS transistor P2 is connected between the output terminal (drain electrode) of the NMOS transistor N2 and the high-level power supply terminal 6.
Connect. Then, the input permission signal C is inverted by the inverter 7 and input to the gate electrode of this transistor. In this way, the PMOS transistor P2
is when the input permission signal C is high level (i.e., the signal S
is turned on (when input is permitted).

Here, if the on-resistance of the NMOS transistor N2 is RN and the on-resistance of the PMOS transistor P2 is RP, then when VS>VDD, VD=VDD as described above. On the other hand, when VS <VDD, VD = {RN / (RP +RN)}・VDD
+{RP / (RP +RN)}・VS, so if RP is set to a value sufficiently larger than RN, VD ≒ VS, and the above-mentioned ■
The conditions of and ■ can be met.

By receiving the output potential of the NMOS transistor N2 corrected in this way at the input buffer 3, the logic of the signal S input to the signal input terminal 4 can be determined more accurately than when only the NMOS transistor N2 is used. can do. Furthermore, the through current in the input buffer 3 can be reduced.

[0019]

[Effects of the Invention] As explained above, according to the present invention, an NMOS transistor is provided which receives an external signal at the source electrode and transmits it from the drain electrode to the input buffer, and the gate potential is fixed at a high power supply voltage. , since the highest potential of the signal input to the gate electrode of the MOS transistor of the input buffer is limited to the high power supply voltage,
The withstand voltage against externally input signals can be improved without increasing the thickness of the gate oxide film of the MOS transistor of the input buffer, and the range of options for external devices connected to the signal input terminal can be expanded. .

Furthermore, the present invention provides a pull-up PMOS transistor between the output terminal (drain electrode) of the NMOS transistor and the high-level power supply terminal, so that the potential level of the external signal is equal to the logic threshold of the input buffer. Even if the level is close to this value, it has the effect of reducing the through current in the input buffer and making it possible to more accurately determine logic.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an input circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of an example of a conventional input circuit.

[Explanation of symbols]

1 NAND circuit 2,7 Inverter 3 Input buffer 4 Signal input terminal 5 Integrated circuit chip 6 High level power supply terminal

Claims (2)

[Claims] 1. An N-channel MOS field effect transistor whose source electrode is connected to a signal input terminal and whose gate electrode is connected to a high-level power supply terminal;
1. An input circuit comprising: an input buffer that receives a potential of a drain electrode of an OS field effect transistor. 2. An N-channel MOS field effect transistor whose source electrode is connected to a signal input terminal and whose gate electrode is connected to a high-level power supply terminal;
An input circuit comprising: a pull-up transistor connected between a drain electrode of an OS field effect transistor and the high-level power supply terminal; and an input buffer receiving the potential of the drain electrode.