JPH04343272A - Solid-state image pickup device - Google Patents

Solid-state image pickup device

Info

Publication number
JPH04343272A
JPH04343272A JP3115165A JP11516591A JPH04343272A JP H04343272 A JPH04343272 A JP H04343272A JP 3115165 A JP3115165 A JP 3115165A JP 11516591 A JP11516591 A JP 11516591A JP H04343272 A JPH04343272 A JP H04343272A
Authority
JP
Japan
Prior art keywords
metal wiring
transfer
wiring layer
solid
imaging device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3115165A
Other languages
Japanese (ja)
Inventor
Kozo Orihara
弘三 織原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3115165A priority Critical patent/JPH04343272A/en
Publication of JPH04343272A publication Critical patent/JPH04343272A/en
Pending legal-status Critical Current

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  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

PURPOSE:To enable a solid-state image pickup device to operate at a high speed by a method wherein a drive pulse is applied to the transfer electrode of a vertical register through the intermediary of a metal wiring for every two horizontal pixels. CONSTITUTION:The first transfer electrodes 103-105 formed of the first polycrystalline silicon film to which the same drive pulse is applied are connected in common through the intermediary of a contact section 109 with the first metal wiring layers 111-115 arranged along the transfer channel 102 of a vertical register. On the other hand, the second transfer electrodes 106-108 of the second polycrystalline silicon film are connected to the second metal wiring layers 116-119 arranged vertical to the first metal wiring layers through the intermediary of a contact section 110 provided to the gap of the first metal wiring layers. By this setup, as the same pulse is applied for every two pixels in the horizontal direction, a high speed operation is limited by the resistance of transfer electrodes for two pixels, and as a result, a solid-state image sensing device of his design can operate at a high speed.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は固体撮像装置に関し、特
にインターライン転送型あるいはフレームインターライ
ン転送型CCD撮像装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device, and more particularly to an interline transfer type or frame interline transfer type CCD imaging device.

【0002】0002

【従来の技術】図3は、従来技術によるインターライン
転送型CCD撮像装置における垂直レジスタの転送電極
構成の一例を示す平面図である。光電変換素子301の
部分を切り欠いた櫛型の形状をした1層目の多結シリコ
ン膜からなる第1の転送電極303と2層目の多結晶シ
リコン膜からなる第2の転送電極306が交互に配置さ
れている。駆動パルスは通常転送電極303〜308の
両端部から印加される。転送電極の材料として一般に用
ちいられている多結晶シリコン膜はシート抵抗値が数1
0Ωと高抵抗であり、例えばHDTV対応の1インチ光
学系に適応した200万画素CCDイメージセンサでは
1本の転送電極の端部から中心部までの抵抗値は100
kΩ程度になる。一方、基板との間の静電容量は10p
F 程度であり、これら抵抗と静電容量との積による時
定数は1μsに達する。その結果、バルスの伝達特性が
著しく劣化し、特に中心部の画素における転送効率の劣
化、転送信号量の減少を引き起こし、高速動作を制限す
る。
2. Description of the Related Art FIG. 3 is a plan view showing an example of the configuration of transfer electrodes of a vertical register in an interline transfer type CCD imaging device according to the prior art. A first transfer electrode 303 made of a first layer of polycrystalline silicon film and a second transfer electrode 306 made of a second layer of polycrystalline silicon film have a comb-shaped shape in which the photoelectric conversion element 301 is cut out. arranged alternately. Driving pulses are normally applied from both ends of the transfer electrodes 303-308. The sheet resistance of polycrystalline silicon films, which are commonly used as materials for transfer electrodes, is several 1.
It has a high resistance of 0Ω, and for example, in a 2 million pixel CCD image sensor adapted to a 1-inch optical system compatible with HDTV, the resistance value from the edge to the center of one transfer electrode is 100Ω.
It will be about kΩ. On the other hand, the capacitance between the substrate and the substrate is 10p.
F, and the time constant due to the product of these resistances and capacitances reaches 1 μs. As a result, the pulse transfer characteristics are significantly deteriorated, causing deterioration in transfer efficiency and reduction in the amount of transferred signals, especially in pixels in the center, and limiting high-speed operation.

【0003】図4は、従来技術によるインターライン転
送型CCD撮像装置における垂直レジスタの転送電極構
成の別の例を示す平面図である。この例では、垂直レジ
スタの転送チャネル402上に転送方向に沿って配置さ
れた金属配線層410〜414によって同一の駆動パル
スが印加される転送電極(403と405、406と4
08)が共通に接続されている。そして金属配線層から
コンタクト部409を介して画素内部の転送電極に直接
駆動パルスを印加することによって、実効的な転送電極
の抵抗を低減してパルスの伝達特性を改善し、図3の例
に比べて1MHz近くの高速動作を実現している。
FIG. 4 is a plan view showing another example of the configuration of transfer electrodes of a vertical register in an interline transfer type CCD imaging device according to the prior art. In this example, transfer electrodes (403 and 405, 406 and 4
08) are commonly connected. By applying a driving pulse directly from the metal wiring layer to the transfer electrode inside the pixel via the contact portion 409, the effective resistance of the transfer electrode is reduced and the pulse transfer characteristics are improved. In comparison, it achieves high-speed operation of nearly 1MHz.

【0004】0004

【発明が解決しようとする課題】図4の例では4相駆動
の垂直レジスタを仮定しており、金属配線層には水平方
向4画素毎に同一の駆動パルスが印加される。したがっ
て1本の転送電極のコンタクト部も水平方向4画素の繰
り返しとなり、4画素分の転送電極の抵抗で高速動作が
制限される。
In the example shown in FIG. 4, a four-phase drive vertical register is assumed, and the same drive pulse is applied to the metal wiring layer for every four pixels in the horizontal direction. Therefore, the contact portion of one transfer electrode also repeats four pixels in the horizontal direction, and high-speed operation is limited by the resistance of the transfer electrode for four pixels.

【0005】本発明の目的は、上述のような従来の欠点
を除去した新しい電荷転送撮像装置を提供することにあ
る。
SUMMARY OF THE INVENTION An object of the present invention is to provide a new charge transfer imaging device that eliminates the drawbacks of the prior art as described above.

【0006】[0006]

【課題を解決するための手段】本発明は、光電変換素子
列および前記光電変換素子列と並行に配置され前記光電
変換素子にそれぞれ第1の転送電極と第2の転送電極を
対応させた垂直レジスタからなる画素列を複数個並列配
置した半導体チップを有する固体撮像装置において、前
記垂直レジスタ上に所定の開孔を有する絶縁膜を介して
転送方向に沿って配置され同一の駆動パルスが印加され
る前記第1の転送電極を共通に接続する第1の金属配線
層および前記第1の金属配置線層と直交し前記第2の転
送電極と接続された第2の金属配置線とを備えていると
いうものである。
[Means for Solving the Problems] The present invention provides a photoelectric conversion element column and a vertical transfer electrode arranged in parallel with the photoelectric conversion element column and having a first transfer electrode and a second transfer electrode corresponding to the photoelectric conversion element, respectively. In a solid-state imaging device having a semiconductor chip in which a plurality of pixel columns each consisting of a register are arranged in parallel, the vertical register is arranged along the transfer direction through an insulating film having a predetermined opening, and the same driving pulse is applied to the vertical register. a first metal wiring layer that commonly connects the first transfer electrodes; and a second metal wiring layer that is perpendicular to the first metal wiring layer and connected to the second transfer electrode. There is.

【0007】[0007]

【実施例】図1は、本発明の実施例のインターライン転
送型CCD撮像装置における垂直レジスタの転送電極構
成の一実施例を示す平面図である。本例では、同一の駆
動パルスが印加される1層目の多結晶シリコン膜からな
る第1の転送電極103〜105は、図4の従来例と同
様に垂直レジスタの転送チャネル102上に沿って配置
された第1の金属配線層111〜115によってコンタ
クト部109を介して共通に接続されている。一方、2
層目の多結晶シリコン膜からなる第2の転送電極106
〜108は、第1の金属配線層の間隙に設けられたコン
タクト部110を介して、第1の金属配線層とは直交す
るように配置された第2の金属配線層116〜119と
接続されている。本例でも4相駆動の垂直レジスタを仮
定しているが、水平方向に2画素毎に同一の駆動パルス
が印加されるため高速動作は2画素分の転送電極の抵抗
で制限されることになり、図4の従来例に比べて2MH
z以上とさらに高速動作を実現することが可能となる。 第1図の例では、第2の転送電極に対しても2画素毎に
コンタクト部を設けて第2の金属配線層と接続している
が、図からも明らかなように1画素毎にコンタクト部を
設けて第2の金属配線層と接続することも可能である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a plan view showing an embodiment of the configuration of transfer electrodes of a vertical register in an interline transfer type CCD imaging device according to an embodiment of the present invention. In this example, the first transfer electrodes 103 to 105 made of the first layer of polycrystalline silicon film to which the same driving pulse is applied are arranged along the transfer channel 102 of the vertical register as in the conventional example of FIG. They are commonly connected via a contact portion 109 by the arranged first metal wiring layers 111 to 115. On the other hand, 2
A second transfer electrode 106 made of a layered polycrystalline silicon film
108 are connected to second metal wiring layers 116 to 119 arranged orthogonally to the first metal wiring layer through contact portions 110 provided in gaps between the first metal wiring layers. ing. This example also assumes a four-phase drive vertical register, but since the same drive pulse is applied to every two pixels in the horizontal direction, high-speed operation is limited by the resistance of the transfer electrode for two pixels. , 2MH compared to the conventional example in Fig. 4
It becomes possible to realize even higher speed operation at speeds higher than z. In the example shown in Fig. 1, a contact portion is also provided for the second transfer electrode every two pixels to connect it to the second metal wiring layer, but as is clear from the figure, a contact portion is provided for each pixel. It is also possible to provide a section and connect it to the second metal wiring layer.

【0008】図2は、本発明の第2の実施例のインター
ライン転送型CCD撮像装置における垂直転送電極の構
成を示す平面図である。本実施例においても、1層目の
第1の転送電極203〜205は、第1の実施例と同様
に垂直レジスタの転送チャンネル202上に転送方向に
沿って配置された第1の金属配線層211〜215によ
ってコンタクト部209を介して水平方向に2画素毎に
共通されている。一方、2層目の第2の転送電極206
〜208は、第1の金属配線層に設けられた開口部21
6内のコンタクト部210を介して、第1の金属配線層
とは直交するように配置された第2の金属配線層217
〜220と接続されている。本実施例においても、水平
方向に2画素毎に駆動パルスを印加しているため高速動
作は2画素分の転送電極の抵抗で制限されることになり
、図4の従来例に比べて約2MHzとさらに高速動作を
実現することが可能となる。さらに第1の実施例と同様
に、第2の転送電極に対して1画素毎にコンタクト部を
設けて第2の金属配線層と接続することも可能である。 また、本実施例ではコンタクト部210は第1、第2の
金属配線層の立体交差部に設けられ、第1の実施例のよ
うに、第1の金属配線層の間隙で第2の金属配線層と第
2の転送電極とを接続するコンタクト部を設ける必要が
ないために、この部分での第2の転送電極の幅を第1の
実施例よりも狭くすることができ、これにより開口率を
増大させ、感度の向上を図ることが可能となる。
FIG. 2 is a plan view showing the configuration of vertical transfer electrodes in an interline transfer type CCD imaging device according to a second embodiment of the present invention. In this embodiment as well, the first transfer electrodes 203 to 205 in the first layer are formed on a first metal wiring layer arranged along the transfer direction on the transfer channel 202 of the vertical register, as in the first embodiment. 211 to 215 are shared by every two pixels in the horizontal direction via the contact portion 209. On the other hand, the second transfer electrode 206 in the second layer
-208 are openings 21 provided in the first metal wiring layer.
A second metal wiring layer 217 is disposed perpendicularly to the first metal wiring layer via a contact portion 210 in 6.
~220. In this embodiment as well, since a drive pulse is applied to every two pixels in the horizontal direction, high-speed operation is limited by the resistance of the transfer electrode for two pixels, and the operating frequency is approximately 2 MHz compared to the conventional example shown in FIG. This makes it possible to achieve even higher speed operation. Further, as in the first embodiment, it is also possible to provide a contact portion for each pixel to the second transfer electrode and connect it to the second metal wiring layer. Further, in this embodiment, the contact portion 210 is provided at a three-dimensional intersection between the first and second metal wiring layers, and as in the first embodiment, the contact portion 210 is provided at a three-dimensional intersection between the first and second metal wiring layers. Since there is no need to provide a contact part connecting the layer and the second transfer electrode, the width of the second transfer electrode in this part can be made narrower than that in the first embodiment, which reduces the aperture ratio. It becomes possible to increase the sensitivity and improve the sensitivity.

【0009】上述した2つの実施例では、インターライ
ン転送型CCD撮像装置の例を示したが、より高速動作
が要求るされるフレームインターライン型CCD撮像装
置に本発明を適用できることは言うまでもない。
In the two embodiments described above, an example of an interline transfer type CCD imaging device was shown, but it goes without saying that the present invention can be applied to a frame interline type CCD imaging device that requires higher speed operation.

【0010】0010

【発明の効果】以上述べたように、本発明の電荷転送撮
像装置では、垂直レジスタを構成する転送電極に金属配
線を介して水平方向2画素毎に駆動パルスを印加するこ
とによって、従来例に比べてより高速動作を実現するこ
とが可能である。
As described above, in the charge transfer imaging device of the present invention, driving pulses are applied to the transfer electrodes constituting the vertical register every two pixels in the horizontal direction via metal wiring, thereby improving the charge transfer imaging device of the present invention. It is possible to achieve higher-speed operation compared to other methods.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明の第1の実施例を示すインターライン転
送型CCD撮像装置における垂直レジスタの平面図であ
る。
FIG. 1 is a plan view of a vertical register in an interline transfer type CCD imaging device showing a first embodiment of the present invention.

【図2】本発明の第2の実施例を示すインターライン転
送型CCD撮像装置における垂直レジスタの平面図であ
る。
FIG. 2 is a plan view of a vertical register in an interline transfer type CCD imaging device showing a second embodiment of the present invention.

【図3】一従来例を示すインターライン転送型CCD撮
像装置における垂直レジスタの平面図である。
FIG. 3 is a plan view of a vertical register in an interline transfer type CCD imaging device showing a conventional example.

【図4】別の従来例を示すインターライン転送型CCD
撮像装置における垂直レジスタの平面図である。
[Fig. 4] Interline transfer type CCD showing another conventional example
FIG. 3 is a plan view of a vertical register in the imaging device.

【符号の説明】[Explanation of symbols]

101、201、301、401  光電変換素子10
2、202、302、402  垂直レジスタの転送チ
ャネル 103〜105、203〜205、303〜305、4
03〜405  第1の垂直転送電極 106〜108、206〜208、306〜308、4
06〜408  第2の垂直転送電極 109、110、209、210  コンタクト部11
1〜115、211〜215  第1の金属配線層の開
口部 116〜119、217〜220  第2の金属配線層
410〜414  金属配線層
101, 201, 301, 401 photoelectric conversion element 10
2, 202, 302, 402 Vertical register transfer channels 103-105, 203-205, 303-305, 4
03-405 First vertical transfer electrodes 106-108, 206-208, 306-308, 4
06-408 Second vertical transfer electrode 109, 110, 209, 210 Contact part 11
1 to 115, 211 to 215 Openings in first metal wiring layer 116 to 119, 217 to 220 Second metal wiring layer 410 to 414 Metal wiring layer

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】  光電変換素子列および前記光電変換素
子列と並行に配置され前記光電変換素子にそれぞれ第1
の転送電極と第2の転送電極を対応させた垂直レジスタ
からなる画素列を複数個並列配置した半導体チップを有
する固体撮像装置において、前記垂直レジスタ上に所定
の開孔を有する絶縁膜を介して転送方向に沿って配置さ
れ同一の駆動パルスが印加される前記第1の転送電極を
共通に接続する第1の金属配線層および前記第1の金属
配線層と直交し前記第2の転送電と接続さた第2の金属
配線層とを備えていることを特徴とする固体撮像装置。
1. A photoelectric conversion element array and a first photoelectric conversion element arranged in parallel with the photoelectric conversion element array and each of the photoelectric conversion elements.
In a solid-state imaging device having a semiconductor chip in which a plurality of pixel columns each consisting of a vertical register in which a transfer electrode and a second transfer electrode are arranged in parallel, an insulating film having a predetermined opening is formed on the vertical register. a first metal wiring layer that commonly connects the first transfer electrodes arranged along the transfer direction and to which the same drive pulse is applied; and a first metal wiring layer that is perpendicular to the first metal wiring layer and that connects the second transfer electrode A solid-state imaging device comprising: a second metal wiring layer connected to the solid-state imaging device;
【請求項2】  第2の金属配線層は第1の金属配線層
と立体交差する部分において第2の転送電極と接続され
る請求項1記載の固体撮像置。
2. The solid-state imaging device according to claim 1, wherein the second metal wiring layer is connected to the second transfer electrode at a portion where the second metal wiring layer three-dimensionally intersects with the first metal wiring layer.
JP3115165A 1991-05-21 1991-05-21 Solid-state image pickup device Pending JPH04343272A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3115165A JPH04343272A (en) 1991-05-21 1991-05-21 Solid-state image pickup device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3115165A JPH04343272A (en) 1991-05-21 1991-05-21 Solid-state image pickup device

Publications (1)

Publication Number Publication Date
JPH04343272A true JPH04343272A (en) 1992-11-30

Family

ID=14655948

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3115165A Pending JPH04343272A (en) 1991-05-21 1991-05-21 Solid-state image pickup device

Country Status (1)

Country Link
JP (1) JPH04343272A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013074296A (en) * 2011-09-26 2013-04-22 P Mccartain John Metal strap type ccd image sensor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013074296A (en) * 2011-09-26 2013-04-22 P Mccartain John Metal strap type ccd image sensor

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