JPH04341928A - Automatic correcting device for optical disk reproduced signal pulse - Google Patents

Abstract

PURPOSE:To prevent the occurrence of a data error by feeding back voltage proportional to difference between the voltage proportional to the average value of the timing of a leading edge and the voltage proportional to the average value of the timing of a trailing edge to a reproduced signal input side. CONSTITUTION:A signal reproduced from an optical disk is supplied to the input 8 of a comparator 10. The leading edge and the trailing edge of the signal binarized by the comparator 10 are detected by an edge detection circuit 11, and this edge detection signal is inputted to the phase comparator 13 of a clock reproducing PLL circuit 12, and phase difference from a reproduced clock is detected. The phase difference output is supplied to a leading edge timing average circuit 16 and a trailing edge timing average circuit 17, and the voltage of the difference of their outputs is generated by a difference signal generation circuit 22. This voltage of the difference is supplied to the input terminal 9 of the comparator 10 through a slice level control voltage generation circuit 23.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for reproducing signals recorded on optical discs such as magneto-optical discs, phase-change optical discs, write-once type optical discs, and read-only optical discs.

0002

2. Description of the Related Art Optical disks such as magneto-optical disks and phase-change optical disks usually use digital recording, but in order to convert a simple PCM signal into a signal more suitable for optical disk recording, it has been ) RLL modulation and (2
, 7) A signal that has been modulated most suitably from among various modulation methods such as RLL modulation is used. There are two methods for recording code strings consisting of "0" and "1" created in this way: pit position recording method (mark-to-mark recording method) and pit-edge recording method (mark length recording method). be. In order to increase the recording density, pits and
The edge recording method is more advantageous. In the following, the description will mainly be given to magneto-optical disks, but the same applies to phase-change optical disks as well.

FIG. 14 is a waveform diagram for explaining the pit-edge recording method. (i) is a data word obtained by PCM modulating an audio signal or video signal, T is a bit interval, and (m) is a code word obtained from the data word of sequence (i) by (1,7) RLL modulation. In the waveform sequence of , the arrows indicate the ends of the codewords. Discrimination window width Tw=2T/3, minimum magnetization reversal interval Tmin
=4T/3, maximum magnetization reversal interval Tmax=16T/3. (n) is the signal (m) recorded on the track of a magneto-optical disk with pit edges, and the original signal is detected by detecting both ends of this mark. (j) is the reproduced waveform of the (n) signal from the magneto-optical disk. In the pit-edge recording method, the leading and trailing edges of the recording mark are the pulse positions to be detected, so it is sufficient to slice the waveform (j) at an appropriate slice level SL. Compare the reproduced signal with an appropriate threshold value as explained below.
The original recorded waveform can be obtained by converting it into a value.

When recording on a magneto-optical disk using a laser beam, the recording power often deviates from the optimum value in practical situations. It is also possible that the sensitivity of the recording medium is not constant on the optical disc. For these reasons, the shape of the recording mark deviates from the normal shape.

FIG. 15 shows an example of an eye pattern when a (1,7) RLL modulation code is recorded as pit-edge. Although it is natural that the amplitude decreases as the mark length during recording becomes shorter, the eye aperture center level also fluctuates up and down as the mark length changes. For this reason, if the original signal is restored by slicing the reproduced signal (j) at a fixed slice level SL during reproduction, the duty ratio of the pulse will fluctuate, thus causing a data error. It can be seen that in order to improve this, the duty fluctuation of the reproduced signal pulse can be reduced by appropriately selecting the slice level SL described above according to the waveform of FIG. 14.

FIG. 16 shows an example of an amplitude detection type DSL (data slice level) circuit for automatically correcting the slice level (see Chapter 7 of Triceps White Series No. 86 "Signal Processing Technology in Optical Recording"). ). Data recording on a magneto-optical disk is normally performed in units of sectors. At the beginning of each sector, there is approximately 1 preamble area for setting the phase synchronization of the demodulation clock.
0 bytes are prepared. The highest recording frequency is usually used as the preamble signal. The circuit shown in FIG. 16 uses this preamble signal to automatically correct the slice level SL. A reproduced signal from an optical disk is input from an input terminal 1 through an amplifier 3 and a waveform equalization circuit 4 to a peak rectification type center value detection circuit 5. The center value detection circuit 5 uses a combination of diodes, resistors, and capacitors connected in opposite directions to always output the center value of the upper and lower peaks of the input waveform and adds it to the sample hold circuit 6. On the other hand, the preamble gate signal enters the sample and hold circuit 6 from the input terminal 2, samples and holds the output of the center value detection circuit 5, and enters one input of the comparator 7. Therefore, a pulse can be obtained by slicing the reproduced signal applied to the other input of the comparator 7 at the center value of the upper and lower peak values of the preamble signal.

It has been experimentally proven that when the threshold level of the comparator 7 in FIG. 16 is set to a fixed value, this value may be set as the center value of the minimum amplitude level of the reproduced signal. Since the preamble provided at the beginning of a normal sector is the reproduction signal with the minimum amplitude, in FIG. 16, the slice level correction voltage obtained during this preamble period is used to correct each sector.

[0008]

The conventional system as described above has the following drawbacks. (a) In the above-mentioned amplitude detection type DSL circuit, the slice level to be corrected is determined by detecting the amplitude of the reproduced signal, so for a signal that has been subjected to waveform equalization, the reproduced signal amplitude is not compensated for by waveform equalization. , the amplitude is almost constant regardless of the recording frequency, so there is not much of a correction effect. (b) Since the correction voltage is detected only in the preamble region, the band to be corrected is determined by the sector frequency and cannot be arbitrarily selected. Also,
It is difficult to widen the band. (c) A sag occurs in the reproduced signal in the preamble area at the beginning of the sector due to DC cut by a capacitor in the reproduction circuit, and the amount of heat generated by the laser changes during recording, causing the recording power and wavelength to fluctuate in the middle of the sector. There are things to do,
If the DC component of that portion does not match the entire sector area, an error may occur in the correction voltage, and the correction may not operate normally. (d) This is oven loop control, and no control is performed regarding the amount of edge shift after binarization.

The present invention eliminates the drawbacks of the prior art described above, and makes it possible to maintain the reproduced signal even if the shape of the recording mark changes due to fluctuations in the emission power of the semiconductor laser or fluctuations in the sensitivity of the recording medium on the optical disk. It is an object of the present invention to provide an optical disk reproduction signal pulse automatic correction device that can minimize the occurrence of data errors by preventing the duty ratio from changing.

0010

[Means for Solving the Problems] In order to solve this problem, the optical disk reproduction signal pulse automatic correction device according to the present invention records the digital signal with a recording code such that the information is located at the rising edge and the falling edge of the waveform. The reproduction signal is a voltage proportional to the difference between the voltage proportional to the average value of the rising edge timing and the voltage proportional to the average value of the falling edge timing of the pulse train obtained by slicing the reproduction signal from the optical disc. It is configured to feed back to the input side to control the slice level of the reproduced signal.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram of a first embodiment of the present invention. The signal reproduced from the magneto-optical disk is applied to the input 8 of the comparator 10 via a preamplifier, an LPF for noise removal, an AGC circuit, and a waveform equalization circuit (not shown in the drawing). The other input 9 of the comparator 10 has
In addition to the feedback input described later, the output or fixed level of the peak rectification type center value detection circuit as already described with reference to FIG. 16 may be input. A rising edge and a falling edge of the signal binarized by the comparator 10 are detected by an edge detection circuit 11 using a differentiating circuit. This edge signal is sent to the phase comparator 13,
The signal is input to the phase comparator 13 of the clock recovery PLL circuit 12, which includes a charge pump 14 and a VCO 15, and the phase difference with the recovered clock is detected. This phase difference output is shown in Figure 1.
The pump up signal (b) and the pump down signal (c) shown in FIG. Using this pump up signal (b) and pump down signal (c) and the aforementioned binarized signal,
A rising edge timing averaging circuit 16 and a falling edge timing averaging circuit 17 detect the lead or lag amount of each edge relative to a reference.

FIG. 2 shows an example of an edge averaging circuit, and FIG. 3 shows examples of waveforms at each part thereof. The pump-up signal (b) and pump-down signal (c) output from the phase comparator 13 are generated from the rising edge (or falling edge) gate signal ( A) is selected, and the reproduction signal period is gated by the reproduction signal gate signal (d). These gated signals are averaged by the diode, resistor, and capacitor shown in the figure, and an averaged output (i) is obtained.

Furthermore, a rising edge timing averaging circuit 16 and a falling edge timing averaging circuit 17 are provided.
A difference signal generation circuit 22 generates a voltage of the difference between the outputs of , and a limiter circuit 24 and a compensation circuit 2 that compensates for frequency characteristics, etc. are used to prevent this voltage from exceeding the upper and lower limits.
The signal is fed back to the input terminal 9 of the first-stage comparator 10 through the slice level control voltage generation circuit 23 consisting of 5.

In the present invention, since the timing of the rising edge and the timing of the falling edge of the comparator output are individually controlled, the frequency band of the feedback loop is used in a band that is 1/2 or less of the frequency band of the PLL. do. If the band is wider than this, there is a possibility that malfunction will occur. Normally, the frequency band of a PLL is selected to be about 1/100 of the bit frequency, so the frequency band of the feedback loop in the present invention is selected to be about 1/200 to 1/2000 of the bit frequency for the above reasons.
selected.

FIGS. 4 and 5 show waveforms of various parts in order to explain the slice level in the present invention. FIG. 4 shows waveforms when the mark length on the recording medium is shorter than the normal value due to low power of the laser beam, etc., and FIG. 5 shows waveforms when the mark length is long due to high power of the laser beam, etc. In the drawings, the waveform indicated by the dotted line is the waveform when the mark length is normal. In both figures, (
j) is the comparator input, SL is the slice level, (k
) is the comparator output, (a-1) is the edge detection circuit output, (a-2) is the waveform of (a-1) during the delay time of the circuit, and in this example, the VCO clock shown in (v). It is delayed by a period of 1/2 cycle. (b) is a pump up signal, and (c) is a pump down signal. (b-1), (c-1), (A) are pump-up signals and pump-up signals for rising edges.
The down signal and averaging circuit output are shown respectively. (b-2
), (c-2), and (B) respectively show the pump up signal, pump down signal, and averaging circuit output for the falling edge. (A-B) shows a difference signal between the (A) signal and (B) signal. In FIGS. 4 and 5, this (
A-B) It can be seen that the positive and negative signals are different. This (A-B) signal is compensated for frequency characteristics, etc., and fed back to the input terminal 9 of the comparator 10 as a slice level control voltage.

FIG. 6 explains the improvement of edge shift by slice level correction, and is drawn for the case where the mark length is short. (j-1), (k-1
) and (a-3) respectively show the comparator input, the comparator output, and the edge detection circuit output when the slice level SL1 is the center value. The waveform shown by the dotted line is when the mark length is normal. (j-2), (k-
2) and (a-4) show cases where the slice level is improved, and show the comparator input, comparator output, and edge detection circuit output, respectively. slice level SL1
is the case of the center value, whereas SL2 is the corrected slice level. Set slice level to SL
It can be seen that by lowering the timing from 1 to SL2, the comparator output is returned to the normal timing.

FIG. 7 shows the nonlinearity of slice level and edge timing changes. (j), (
k), (a-1)...(v), etc. are shown in Figures 4 and 5, respectively.
This shows a waveform similar to that shown in . Regular slice level S
When the slice level is lowered from L, the state where the slice level SL is SL1 is the limit point at which it can be normally detected. If the slice level is further lowered from this state and the slice level SL is set to SL2, the phase with respect to the VCO clock will be reversed. In Figure 7, the pump
The up and pump down signals indicate this condition. Since this is clearly not a correct state, the aforementioned limiter circuit 23 is used to avoid this.

FIG. 9 illustrates that when the recording power is low and the mark length is short, an error occurs when reproducing without correcting the slice level SL according to the present invention, in comparison with FIG. 8 for a normal case. It is a diagram. (j-1), (k-
1), (a-5), (v), etc. are the same as those in FIGS. 4 and 5. (p) is code data by (1,7) RLL modulation, and (q-1) shows the demodulated output when recording and reproduction are performed normally. (p) and (q-1) are completely the same. (q-2) shows the demodulated output when the slice level is not corrected even though the recording mark length is shorter than the normal value, and an error has occurred in the demodulated output (q-2). Indicates the condition.

FIG. 10 is a block diagram of a second embodiment of the present invention, and shows a case where the control in the first embodiment described above is performed by software. The difference voltage between the output voltage of the rising edge timing averaging circuit 16 and the output voltage of the falling edge timing averaging circuit 17 is taken into the controller 27 via the A/D converter 26, subjected to calculation, and /A converter 28 outputs it as a slice level control voltage, and feeds it back to input terminal 9 of first stage comparator 10 as in the first embodiment.

In FIG. 11, the outputs of the timing averaging circuits 16 and 17 for each edge are switched by a selector 29 and taken into the controller 27.

FIG. 12 is a block diagram showing a third embodiment of the present invention. Since the configuration is a combination of the configuration of FIG. 1 and the configuration of FIG. 10, the selector 29 can appropriately switch between hardware and software control. Configuration of Figure 1 and Figure 11
Of course, it is also possible to combine the configurations.

FIG. 13 is a flowchart showing a control procedure by the controller 27 shown in FIG. It is determined whether the reproduced signal is from the signal recording area other than the gap area, and if it is from the signal recording area, the average value of the rising edge timing and the average value of the falling edge timing of the reproduced signal waveform is determined. Type A/D converter 2
6 to the controller 27. The controller 27 calculates the difference between the two types of average values, and if the amplitude of the difference voltage is within an allowable range, a slice level control voltage corresponding to the value is calculated. The slice level control voltage is applied so that the difference between the average value of rising edge timing and the average value of falling edge timing becomes small. The detected timing shift amount is output as a positive or negative voltage with respect to the phase lead or lag. Therefore, correction is also performed in both positive and negative directions accordingly.

[0023] If the voltage value of the difference calculation output when inputting the average value of the rising edge timing and the average value of the falling edge timing exceeds the allowable range,
A limiter operation is performed to correct the slice level with a predetermined fixed value.

[0024] Whether the differential voltage value does not exceed the allowable range or exceeds it, the slice level is corrected by adjusting the control voltage according to the correction amount determined by the controller 27.
This is done by feeding back to the input terminal 9 of the comparator 10 via the D/A converter 28.

By performing the operations described above from measuring the amount of shift in edge timing to correcting the slice level at regular intervals in the signal recording area other than the gap area, it is possible to dynamically respond to edge shifts. can do.

[0026]

[Effects of the Invention] As explained in detail above, in controlling the slice level of the reproduction signal pulse from an optical disc, whereas the conventional method uses open loop control,
Since the method according to the present invention detects and corrects the final edge shift amount using a feedback loop including the VCO, more accurate correction is performed. Therefore, it is possible to prevent data errors from occurring due to variations in the duty ratio of reproduction pulses.

[0027] In addition, since this method operates on the entire region including the preamble, it has a sufficient correction effect even on the reproduced signal that has been subjected to waveform equalization, and the correction frequency band can be arbitrarily selected. It is easy to widen the band. moreover,
Sag may occur in the preamble area at the beginning of the sector due to DC cut by the capacitor in the playback circuit, and the amount of heat generated by the laser during recording may fluctuate, causing the recording power and wavelength to fluctuate in the middle of the sector. Even if the DC component does not match the entire sector area, no error occurs in the correction voltage, and accurate correction control can be performed.

[0028] As described above, the pit-edge recording method for optical discs can be put to practical use only by applying the present invention.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing one example of an edge detection circuit used in the present invention.

FIG. 3 is an operational waveform diagram of each part of the edge detection circuit.

FIG. 4 is a time chart for explaining operations regarding slice levels in the present invention.

FIG. 5 is a time chart for explaining operations regarding slice levels in the present invention.

FIG. 6 is a time chart for explaining improvement in edge shift by slice level correction in the present invention.

FIG. 7 is a time chart for explaining the nonlinearity of slice level and edge timing changes in the present invention.

FIG. 8 is a time chart for explaining normal operation according to the present invention.

FIG. 9 is a time chart for explaining an error operation when the correction according to the present invention is not performed.

FIG. 10 is a block diagram showing a second embodiment of the present invention.

FIG. 11 is a block diagram showing a modification of the embodiment of FIG. 10;

FIG. 12 is a block diagram showing a third embodiment of the present invention.

FIG. 13 is an operation flow of the controller used in the embodiment of FIG. 11;

FIG. 14 is a time chart for explaining the pit-edge recording method that is the premise of the present invention.

FIG. 15 is a diagram showing an example of an eye pattern when a (1, 7) RLL modulation code is pit-edge recorded.

FIG. 16 is a circuit diagram showing a conventional data slice level circuit for automatically correcting slice levels.

[Explanation of symbols]

1, 2 Input terminal 3 Amplifier 5 Center value detection circuit 6 Sample hold circuit 7 Comparators 8, 9 Input 10 of comparator 10 Comparator 11 Edge detection circuit 12 PLL circuit for clock reproduction 13 Phase comparator 14 Charge pump 15 VCO 16 Rising edge timing Averaging circuit 17
Falling edge timing averaging circuit 22 Difference signal generation circuit 23 Slice level control voltage generation circuit 24 Limiter circuit 25 Compensation circuit 26 A/D converter 27 Controller 28 D/A converter 29 Selector

Claims (3)

[Claims] Claim 1: Proportional to the average value of the timing of the rising edge of a pulse train obtained by slicing a playback signal from an optical disk recorded with a recording code such that the digital signal information is on the rising edge and falling edge of the waveform. Optical disc playback signal pulse automatic correction that controls the slice level of the playback signal by feeding back a voltage proportional to the difference between the voltage and a voltage proportional to the average value of falling edge timing to the playback signal input side. Device. Claim 2: Proportional to the average value of the timing of the rising edge of a pulse train obtained by slicing a reproduced signal from an optical disk recorded with a recording code such that the digital signal information is on the rising edge and falling edge of the waveform. 2. The optical disc playback signal pulse according to claim 1, wherein a voltage proportional to the average value of the voltage and the timing of the falling edge is determined, and a voltage proportional to the difference between the two voltages is fed back to the input side via a limiter. Automatic correction device. 3. Proportional to the average value of the timing of the rising edge of a pulse train obtained by slicing a reproduced signal from an optical disk recorded with a recording code such that the information of the digital signal is on the rising edge and falling edge of the waveform. means for determining a voltage proportional to the average value of the timing of the falling edge; means for AD converting the two voltages or a voltage proportional to the difference thereof; and normal values of the timing of the rising and falling edges. means for determining whether or not the amount of displacement from the ? means for generating a voltage; means for generating a slice level control voltage for the reproduced signal pulse according to a predetermined voltage value by performing a limiter operation when the amount of variation determined by the determination is outside a permissible range; and the slice level An optical disk reproduction signal pulse automatic correction device comprising means for DA converting a control voltage and feeding it back to an input side.