JPH0434026U - - Google Patents
Info
- Publication number
- JPH0434026U JPH0434026U JP7477190U JP7477190U JPH0434026U JP H0434026 U JPH0434026 U JP H0434026U JP 7477190 U JP7477190 U JP 7477190U JP 7477190 U JP7477190 U JP 7477190U JP H0434026 U JPH0434026 U JP H0434026U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- resistor
- voltage
- bpc
- time shortening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Oscillators With Electromechanical Resonators (AREA)
- Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
第１図は本考案回路の第１実施例を用いた、無
線機の電圧制御端子付き温度補償型基準発振回路
の構成を示す接続図、第２図は第１図示の回路に
おける積分回路の動作説明図、第３図は第２実施
例を用いた、無線機の電圧制御端子付き温度補償
型基準発振回路の構成を示す接続図、第４図は第
３図示の第２実施例における微分回路の動作説明
図、第５図は同じく積分回路の動作説明図、第６
図は従来の電圧制御端子付き温度補償型基準発振
回路の一例の構成を示す接続図、第７図は第６図
示の従来回路における積分回路の接続図、第８図
はその動作説明図である。
Ｒ５……抵抗、Ｒ６〜Ｒ８……分圧抵抗、Ｃ１
……コンデンサ、ＶＣ……電圧制御端子、Ｖｃ…
…電圧、Ｖｏ……電圧、ＯＳＣ……基準発振回路
、ＴＣ……温度補償回路、ＴＣＯ……電圧制御端
子付き温度補償型基準発振回路、ＢＰＣ……バイ
パス回路、ＣＲ２……ダイオード、ＡＳ…アナロ
グスイツチ、Ｇ……ゲート、Ｒ９……抵抗、Ｃ２
……コンデンサ。
Fig. 1 is a connection diagram showing the configuration of a temperature compensated reference oscillation circuit with a voltage control terminal for a radio using the first embodiment of the circuit of the present invention, and Fig. 2 is an operation of the integrating circuit in the circuit shown in Fig. 1. An explanatory diagram, FIG. 3 is a connection diagram showing the configuration of a temperature compensated reference oscillation circuit with a voltage control terminal of a radio using the second embodiment, and FIG. 4 is a differential circuit in the second embodiment shown in FIG. Figure 5 is a diagram explaining the operation of the integrating circuit, and Figure 6 is a diagram explaining the operation of the integrating circuit.
The figure is a connection diagram showing the configuration of an example of a conventional temperature-compensated reference oscillator circuit with a voltage control terminal, FIG. 7 is a connection diagram of an integrating circuit in the conventional circuit shown in FIG. 6, and FIG. 8 is an explanatory diagram of its operation. . R5...Resistor, R6-R8...Voltage dividing resistor, C1
...Capacitor, VC...Voltage control terminal, Vc...
...Voltage, Vo...Voltage, OSC...Reference oscillation circuit, TC...Temperature compensation circuit, TCO...Temperature compensated reference oscillation circuit with voltage control terminal, BPC...Bypass circuit, CR2...Diode, AS...Analog Switch, G...gate, R9...resistance, C2
...Capacitor.
Claims (1)
Ｒ５を介して入力され、かつこの抵抗Ｒ５と積分
回路を構成するコンデンサＣ１を介して電圧制御
端子ＶＣより得られる電圧Ｖｃにより発振周波数
が制御される基準発振回路ＯＳＣに、温度補償回
路ＴＣを備えた電圧制御端子付き温度補償型基準
発振回路ＴＣＯにおいて、前記抵抗Ｒ５に並列に
バイパス回路ＢＰＣを接続せしめてなる周波数安
定時間短縮回路。 (2) バイパス回路ＢＰＣはダイオードＣＲ２回
路である請求項第(1)項記載の周波数安定時間短
縮回路。 (3) バイパス回路ＢＰＣはアナログスイツチＡ
Ｓの回路であり、この回路のアナログスイツチＡ
ＳのゲートＧにゲート電圧を印加する抵抗Ｒ９と
コンデンサＣ２よりなる微分回路を接続してなる
請求項第(1)項記載の周波数安定時間短縮回路。[Claims for Utility Model Registration] (1) A voltage Vo divided by a voltage dividing resistor is inputted through a resistor R5, and is connected to a voltage control terminal VC through a capacitor C1 that constitutes an integrating circuit with this resistor R5. In the reference oscillation circuit OSC whose oscillation frequency is controlled by the obtained voltage Vc, in the temperature compensated reference oscillation circuit TCO with a voltage control terminal and equipped with a temperature compensation circuit TC, a bypass circuit BPC is connected in parallel to the resistor R5. A frequency stabilization time shortening circuit. (2) The frequency stabilization time shortening circuit according to claim (1), wherein the bypass circuit BPC is a diode CR2 circuit. (3) Bypass circuit BPC is analog switch A
S circuit, and analog switch A of this circuit
2. The frequency stabilization time shortening circuit according to claim 1, wherein a differentiating circuit comprising a resistor R9 and a capacitor C2 for applying a gate voltage to the gate G of S is connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7477190U JPH0434026U (en) | 1990-07-13 | 1990-07-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7477190U JPH0434026U (en) | 1990-07-13 | 1990-07-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0434026U true JPH0434026U (en) | 1992-03-19 |
Family
ID=31614760
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7477190U Pending JPH0434026U (en) | 1990-07-13 | 1990-07-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0434026U (en) |
-
1990
- 1990-07-13 JP JP7477190U patent/JPH0434026U/ja active Pending
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