JPH04339415A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPH04339415A
JPH04339415A JP3068163A JP6816391A JPH04339415A JP H04339415 A JPH04339415 A JP H04339415A JP 3068163 A JP3068163 A JP 3068163A JP 6816391 A JP6816391 A JP 6816391A JP H04339415 A JPH04339415 A JP H04339415A
Authority
JP
Japan
Prior art keywords
voltage
general
terminal
purpose terminal
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3068163A
Other languages
Japanese (ja)
Inventor
Motoo Akasaka
元雄 赤坂
Akira Ban
伴 明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP3068163A priority Critical patent/JPH04339415A/en
Publication of JPH04339415A publication Critical patent/JPH04339415A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To easily investigate the factor of a malfunction due to the abnormal voltage input from an external part in a semiconductor integrated circuit. CONSTITUTION:When the voltage higher than a power terminal 52 is inputted to a general purpose terminal 51, the voltage of a joint A becomes the voltage lower than inputted to the general purpose terminal 51 and higher than the voltage of power terminals 52 and 53. When the voltage of the joint A and the voltage of a power terminal 53 are inputted to a comparator 4 and the voltage of the joint A is higher than the voltage of the power terminal 53, a comparing output signal (l) is outputted and stored through a writing circuit 6 to an EEPROM circuit 7. When the voltage lower than the potential of a ground point is inputted to the general purpose terminal 51, the voltage of the joint A becomes the voltage higher than the voltage inputted to the general purpose terminal 51 and lower than the voltage of the ground point. When the voltage of the joint A and the voltage of the ground point are inputted to a comparator 5 and the voltage of the joint A is lower than the voltage of the ground point, a comparing output signal (2) is outputted, and stored through the writing circuit 6 to the EEPROM circuit 7.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は半導体集積回路に関する
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits.

【0002】0002

【従来の技術】一般に、半導体集積回路においては、雑
音等によりラッチアップが発生して、内部回路が破壊さ
れるという問題点がある。このため、半導体集積回路の
汎用端子には保護回路が設けられて、内部回路の破壊を
防止する対策がとられている。図2に示されるのは、こ
の汎用端子である。なお、図2においては、説明上、特
に必要ということがないので、内部回路等は一切省略さ
れて記載されていない。図2に示されるように、半導体
集積回路8の保護回路としては、汎用端子54に対して
、電源端子55と接地点との間に直列に接続されるダイ
オード9および10が設けられており、両ダイオードの
接続点(節点A)に汎用端子54が接続されている。
2. Description of the Related Art Semiconductor integrated circuits generally have the problem that latch-up occurs due to noise and the like, resulting in destruction of internal circuits. For this reason, protection circuits are provided at general-purpose terminals of semiconductor integrated circuits to prevent damage to the internal circuits. What is shown in FIG. 2 is this general purpose terminal. Note that in FIG. 2, internal circuits and the like are not shown at all because they are not particularly necessary for the purpose of explanation. As shown in FIG. 2, as a protection circuit for the semiconductor integrated circuit 8, diodes 9 and 10 are provided which are connected in series between the power supply terminal 55 and the ground point with respect to the general-purpose terminal 54. A general-purpose terminal 54 is connected to the connection point (node A) between both diodes.

【0003】図2において、汎用端子54に、電源端子
55に印加される電源電圧よりも高い電圧が入力された
場合には、ダイオード9が順バイアスとなり、汎用端子
54から節点A、ダイオード9を介して、電源端子55
を経由して電源に電流が流入する。この時に、節点Aの
電圧は、汎用端子54から接点Aに至るまでの回路の抵
抗値をR1 、節点Aからダイオード9を介して電源端
子55に至るまでの抵抗値をR2 とすると、(節点の
電圧)={(汎用端子54の電圧)−(電源端子55の
電圧)}×{R1 /(R1 +R2 )}+(電源端
子55の電圧) となる。
In FIG. 2, when a voltage higher than the power supply voltage applied to the power supply terminal 55 is input to the general-purpose terminal 54, the diode 9 becomes forward biased, and the voltage from the general-purpose terminal 54 to the node A and the diode 9 is Through the power terminal 55
Current flows into the power supply via. At this time, the voltage at node A is determined by (node voltage)={(voltage at general-purpose terminal 54)-(voltage at power supply terminal 55)}×{R1/(R1+R2)}+(voltage at power supply terminal 55).

【0004】従って、内部回路に印加される電圧を、汎
用端子54に入力された電圧よりも下げることが可能と
なり、ラッチアップを起りにくくすることができる。同
様に、汎用端子54に接地点の電位よりも低い電圧が入
力された場合においても、ダイオード10が順バイアス
となることにより、内部回路に印加される電圧を、汎用
端子54に入力される電圧よりも高くすることが可能と
なり、ラッチアップを起りにくくすることができる。
Therefore, it is possible to lower the voltage applied to the internal circuit than the voltage input to the general-purpose terminal 54, making latch-up less likely to occur. Similarly, even when a voltage lower than the potential of the ground point is input to the general-purpose terminal 54, the diode 10 becomes forward biased, so that the voltage applied to the internal circuit is reduced to the voltage input to the general-purpose terminal 54. This makes it possible to make it higher than the current value, making it difficult for latch-up to occur.

【0005】[0005]

【発明が解決しようとする課題】上述した従来の半導体
集積回路においては、汎用端子に対応して設けられてい
る一対のダイオードにより形成される保護回路において
、ダイオードの順バイアスに伴なって流れる電流に起因
して、半導体集積回路の基板またはウェル内にキャリア
の注入が行われ、これらのダイオードの近傍の基板また
はウェルの電位が変動して、内部回路に含まれる保持回
路等に誤動作を誘発させるという欠点があり、且つ当該
誤動作の要因の究明が困難であるという欠点がある。
[Problems to be Solved by the Invention] In the conventional semiconductor integrated circuit described above, in a protection circuit formed by a pair of diodes provided corresponding to a general-purpose terminal, a current flows due to forward bias of the diode. Due to this, carriers are injected into the substrate or well of the semiconductor integrated circuit, and the potential of the substrate or well near these diodes fluctuates, causing malfunctions in the holding circuits included in the internal circuits. There is a drawback that it is difficult to investigate the cause of the malfunction.

【0006】[0006]

【課題を解決するための手段】本発明の半導体集積回路
は、汎用端子に対応する入力回路として、陰極側が電源
端子に接続され、陽極側が前記汎用端子に接続される第
1のダイオードと、陰極側が前記汎用端子に接続され、
陽極側が接地点に接続される第2のダイオードと、前記
電源端子の電圧(1)と、前記第1および第2のダイオ
ードの接続点の電圧(2)とを比較して、電圧(1)>
電圧(2)に対応する第1の比較出力信号を出力する第
1のコンパレータと、前記第1および第2のダイオード
の接続点の電圧(2)と、前記接地点の電圧(3)とを
比較して、電圧(2)<電圧(3)に対応する第2の比
較出力信号を出力する第1のコンパレータと、前記第1
および第2のコンパレータより出力される第1および第
2の比較出力信号を格納する記憶回路と、を備えて構成
される。
[Means for Solving the Problems] A semiconductor integrated circuit of the present invention includes, as an input circuit corresponding to a general-purpose terminal, a first diode whose cathode side is connected to a power supply terminal and whose anode side is connected to the general-purpose terminal; side is connected to the general purpose terminal,
A voltage (1) is obtained by comparing the voltage (1) of the second diode whose anode side is connected to the grounding point, the voltage (1) of the power supply terminal, and the voltage (2) of the connection point of the first and second diodes. >
a first comparator that outputs a first comparison output signal corresponding to the voltage (2), a voltage (2) at the connection point of the first and second diodes, and a voltage (3) at the ground point; a first comparator that compares and outputs a second comparison output signal corresponding to voltage (2)<voltage (3);
and a storage circuit that stores the first and second comparison output signals output from the second comparator.

【0007】[0007]

【実施例】次に、本発明について図面を参照して説明す
る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

【0008】図1は本発明の一実施例における保護回路
の部分を示すブロック図であり、内部回路等は省略され
て記載されていない。図1に示されるように、本実施例
の汎用端子に対応する入力回路は、汎用端子51、電源
端子52および53に対応して、ダイオード2および3
と、コンパレータ4および5と、書込み回路6と、EE
PROM回路7とを備えて構成される。
FIG. 1 is a block diagram showing a portion of a protection circuit in an embodiment of the present invention, and internal circuits and the like are omitted and not shown. As shown in FIG. 1, the input circuit corresponding to the general-purpose terminal of this embodiment includes diodes 2 and 3 corresponding to the general-purpose terminal 51 and power supply terminals 52 and 53.
, comparators 4 and 5, write circuit 6, and EE
It is configured to include a PROM circuit 7.

【0009】図1において、汎用端子51に、電源端子
52よりも高い電圧が入力された場合には、ダイオード
2が順バイアスとなり、節点Aの電圧は、汎用端子51
に入力された電圧よりも低くなるが、電源端子52およ
び53の電圧よりは高い電圧となる。これらの節点Aの
電圧および電源端子53の電圧は、コンパレータ4に入
力されるが、コンパレータ4は、節点Aの電圧が、電源
端子53の電圧よりも高い時においてのみ、両者の比較
出力を信号(1)として出力する機能を有しており、従
って、上記の状態においては、コンパレータ4からは、
節点Aの電圧が、電源端子53の電圧よりも高い状態を
示す信号(1)が出力されて書込み回路6に入力され、
書込み回路6を介して、EEPROM回路7に当該信号
(1)の情報が格納される。
In FIG. 1, when a voltage higher than that of the power supply terminal 52 is input to the general-purpose terminal 51, the diode 2 becomes forward biased, and the voltage at the node A is applied to the general-purpose terminal 51.
However, the voltage is higher than the voltage at power supply terminals 52 and 53. The voltage at node A and the voltage at power supply terminal 53 are input to comparator 4, but comparator 4 outputs a comparison output between the two as a signal only when the voltage at node A is higher than the voltage at power supply terminal 53. (1), therefore, in the above state, the comparator 4 outputs
A signal (1) indicating that the voltage at node A is higher than the voltage at power supply terminal 53 is output and input to write circuit 6;
The information of the signal (1) is stored in the EEPROM circuit 7 via the write circuit 6.

【0010】また、汎用端子51に、接地点の電位より
も低い電圧が入力された場合には、ダイオード3が順バ
イアスとなり、節点Aの電圧は、汎用端子51に入力さ
れた電圧よりも高くなるが、接地点の電圧よりは低い電
圧となる。これらの節点Aの電圧および接地点の電圧は
、コンパレータ5に入力されるが、コンパレータ5は、
節点Aの電圧が、接地点の電圧よりも低い時においての
み、両者の比較出力を信号(2)として出力する機能を
有しており、従って、上記の状態においては、コンパレ
ータ5からは、節点Aの電圧が、接地点の電圧よりも低
い状態を示す信号(2)が出力されて書込み回路6に入
力され、書込み回路6を介して、EEPROM回路7に
当該信号(2)の情報が格納される。
Furthermore, when a voltage lower than the potential of the ground point is input to the general-purpose terminal 51, the diode 3 becomes forward biased, and the voltage at the node A becomes higher than the voltage input to the general-purpose terminal 51. However, the voltage is lower than the voltage at the ground point. These voltages at the node A and the voltage at the ground point are input to the comparator 5, but the comparator 5
It has the function of outputting the comparison output of both as signal (2) only when the voltage at node A is lower than the voltage at the ground point. Therefore, in the above state, comparator 5 A signal (2) indicating that the voltage at A is lower than the voltage at the ground point is output and input to the write circuit 6, and the information of the signal (2) is stored in the EEPROM circuit 7 via the write circuit 6. be done.

【0011】従って、上記の動作を介することにより、
半導体集積回路1において、何等かの誤動作が発生した
場合には、EEPROM回路7に格納されているデータ
内容を読出すことにより、当該誤動作の原因が、外部か
らの異常電圧によるラッチアップによるものか否かを容
易に判断することができる。
[0011] Therefore, by going through the above operations,
If some kind of malfunction occurs in the semiconductor integrated circuit 1, by reading the data contents stored in the EEPROM circuit 7, it can be determined whether the cause of the malfunction is latch-up due to an abnormal voltage from the outside. It can be easily determined whether or not.

【0012】0012

【発明の効果】以上説明したように、本発明は、汎用端
子に入力される異常電圧に対応して発生するラッチアッ
プの経過を記録することにより、誤動作の要因を容易に
究明することができるという効果がある。
[Effects of the Invention] As explained above, the present invention makes it possible to easily determine the cause of malfunction by recording the progress of latch-up that occurs in response to abnormal voltage input to a general-purpose terminal. There is an effect.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明の一実施例を示すブロック図である。FIG. 1 is a block diagram showing one embodiment of the present invention.

【図2】従来例を示す回路図である。FIG. 2 is a circuit diagram showing a conventional example.

【符号の説明】[Explanation of symbols]

1、10    半導体集積回路 2、3、9、10    ダイオード 4、5    コンパレータ 6    書込み回路 7    EEPROM回路 1, 10 Semiconductor integrated circuit 2, 3, 9, 10 Diode 4, 5 Comparator 6 Write circuit 7 EEPROM circuit

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  汎用端子に対応する入力回路として、
陰極側が電源端子に接続され、陽極側が前記汎用端子に
接続される第1のダイオードと、陰極側が前記汎用端子
に接続され、陽極側が接地点に接続される第2のダイオ
ードと、前記電源端子の電圧(1)と、前記第1および
第2のダイオードの接続点の電圧(2)とを比較して、
電圧(1)>電圧(2)に対応する第1の比較出力信号
を出力する第1のコンパレータと、前記第1および第2
のダイオードの接続点の電圧(2)と、前記接地点の電
圧(3)とを比較して、電圧(2)<電圧(3)に対応
する第2の比較出力信号を出力する第1のコンパレータ
と、前記第1および第2のコンパレータより出力される
第1および第2の比較出力信号を格納する記憶回路と、
を備えることを特徴とする半導体集積回路。
[Claim 1] As an input circuit corresponding to a general-purpose terminal,
a first diode whose cathode side is connected to the power supply terminal and whose anode side is connected to the general-purpose terminal; a second diode whose cathode side is connected to the general-purpose terminal and whose anode side is connected to the ground point; Comparing the voltage (1) with the voltage (2) at the connection point of the first and second diodes,
a first comparator that outputs a first comparison output signal corresponding to voltage (1)>voltage (2);
A first comparison output signal that compares the voltage (2) at the connection point of the diode with the voltage (3) at the ground point and outputs a second comparison output signal corresponding to voltage (2) < voltage (3). a comparator, and a storage circuit that stores first and second comparison output signals output from the first and second comparators;
A semiconductor integrated circuit characterized by comprising:
JP3068163A 1991-04-01 1991-04-01 Semiconductor integrated circuit Pending JPH04339415A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3068163A JPH04339415A (en) 1991-04-01 1991-04-01 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3068163A JPH04339415A (en) 1991-04-01 1991-04-01 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPH04339415A true JPH04339415A (en) 1992-11-26

Family

ID=13365822

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3068163A Pending JPH04339415A (en) 1991-04-01 1991-04-01 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH04339415A (en)

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