JPH04337853A - Operation history recorder for cache memory - Google Patents

Abstract

PURPOSE:To facilitate the analysis of a cache error on the operation history recorder of a cache memory. CONSTITUTION:In a cache memory device provided with a data part 4 and a tag part 10, a first count means 30, a second count means 31 and a read means 32 are given and an area recording the number of first replaced read bits and an area recording the number of second read bits which are write-hit are provided for the respective entry areas of the tag part 10. The first count means 30 increases the number of the first read hits recorded in the entry areas which correspond to the replaced read hits. The second count means 31 increases the number of the second read hits recorded in the entry areas which correspond to the read hits which are write-hit. The read means 32 reads and outputs the tag part and the data part when the cache memory device is detached owing to the occurrence of the cache error.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory operation history recorder. In recent years, in order to increase the speed of information processing devices, the number of devices equipped with cache memory has increased. Since the primary purpose of this cache memory is high-speed access, the main error detection mechanism is a parity check method. If a parity error occurs in the cache memory, the correct data is replaced from the main memory, or One method is to disable the cache memory and then directly access the main storage device.

[0002] On the other hand, when developing a device, a problem with the cache memory causes data to become garbled and causes the processor to run out of control, which is currently extremely difficult to analyze in terms of debugging. Therefore, there is a need to facilitate analysis of the causes of cache errors.

0003

[Prior Art] FIG. 4 is an explanatory diagram of a cache memory.
Gates and the like that control data paths are not shown. An outline of the cache operation will be explained below with reference to FIG.

[0004] The processor 1 uses a 32-bit (4 bytes = long word) processor. The data section 4 is composed of a high-speed memory, and in the event of a mishit in which the data addressed by the processor 1 does not exist in the data section 4, the data is transferred (replaced) from the main storage device 9 by a replace circuit 7.

[0005] The tag unit 3 uses A11 to A of the 32 bits (A31 to A0) of the address output by the processor 1.
It has 512 entry areas 3a that are addressed by 3, and each registers the data (2 longwords in this case) stored in the data section 4. Each entry area 3a has a V bit indicating validity/invalidity, and addresses A31~
It consists of an area for storing the value of A12, and the main storage device 9
Entry area 3 indicated by A11 to A3 of the addresses output when transferring data from to data section 4
The values of A31 to A12 are stored in a, and the data output from the main storage device 9 is stored in the areas of A11 to A2 in the data section 4.

[0006] At the time of reading, the comparator CMP 5
A31 to A1 output from processor CPU1
2 and the values of A31 to A12 addressed by A11 to A3 and output from the tag section 3. If they match and the V bit is "1" (valid), the corresponding data is stored in the data section 4. A hit signal "1" indicating the existence of the data is output. As a result, the data in the area designated by A11 to A2 of the data section 4 is output to the processor 1.

[0007] In this way, when data exists in the data section 4 of the high-speed memory, it is accessed at high speed. The address latch 2 latches address data A31 to A0 output from the processor 1 every CPU cycle, and in the event of a miss, the address latch 2
address information is output to the address line, and replacement is performed in block units (here, 2 long words). At this time, the replace circuit 7 transfers the first long word directly to the processor 1 and at the same time transfers it to the data section 4.
Subsequently, the address is incremented and the next long word is transferred from the main memory device 9 to the data section 4.

When data is written (updated), it is written to the main memory 9 and at the same time, if the corresponding data exists in the data section 4 (write hit), it is written to the data section 4.

Here, the parity checker/generator PC/PG8 generates parity data when storing it in the data section 4, and performs a parity check when reading it.If a parity error occurs, the cache is invalidated from now on. Detach or replace the relevant data.

0010

Conventionally, when an intermittent failure occurs in a cache memory, it is very difficult to determine whether the cause is a soft error or a circuit defect. Furthermore, even if the problem is caused by a circuit defect, it is extremely difficult to analyze which access in the cache memory is causing the problem.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, an object of the present invention is to provide a cache memory operation history recording device that facilitates failure analysis when an abnormality occurs in a cache memory in the development and maintenance of a device having a cache memory. purpose.

0012

[Means for Solving the Problems] In the principle diagram of the present invention shown in FIG. 1, 4 is a data section which stores part of the data stored in the main storage device. 10 is a tag section, and each entry area 10a has a first area for recording the number of read hits after replacement, and a second area for recording the number of read hits after write hit. A first counting means 30 increments the number of read hits of the first area recorded in the corresponding entry area 10a for each read hit after replacement. A second counting means 31 increments the number of read hits of the second area recorded in the corresponding entry area 10a for each read hit after a write hit. 32 is a reading means that invalidates the cache memory (
The tag section 10 at that point is
The contents of the data section 4 are then frozen so that they can be read later by a program.

[0013]

[Operation] The first counting means 30 increments the first number of read hits (number of read hits after replacement) recorded in the corresponding entry area 10a for each read hit after replacement. Second counting means 30
for each read hit after a write hit, increments the second read hit number (reset if replaced after a write hit) recorded in the corresponding entry area 10a.

Reference numeral 32 denotes a reading means that reads and outputs the contents of the tag section 10 and the data section 4 at the time when the cache memory device is disconnected due to occurrence of a cache error. FIG. 2 shows a case where two long words are replaced at once. When a read miss occurs at address A, data a and data b are replaced successively. At this time, data a is simultaneously output from the main memory to the processor, but when address B (A+1) is read accessed in the next cycle, a read hit occurs, so the first read hit number is 1. (2) If data b is abnormal at this time, the cache is invalidated and this record is output. ■Also, if data b is normal and data b is accessed again, it will be a read hit, so the first read hit number will be 2. If data b is abnormal at this time, the cache will be invalidated and 2 will be Output.

In the case of ■, since this is the first read hit after replacement, it is assumed that the replacement circuit is abnormal; in the case of ■, the first read hit is normal and the second is abnormal, so it is considered a soft error. Presumed. In the case of ■, even if data a is accessed and becomes abnormal, the probability that the replacement of data a will be abnormal and the replacement of data b will be normal is extremely small, so it is still presumed to be a soft error.

Similarly, based on the number of read hits after a write hit, it is estimated whether there is an abnormality in the write hit circuit or a soft error. As described above, failure analysis can be facilitated by recording the first and second read hit counts and outputting them together with the data in the data section 4 when the cache is invalidated.

[0017]

Embodiment FIG. 3 is a configuration diagram of an embodiment, which is applied to the configuration of FIG. 4, and the same reference numerals represent the same objects. Figure 3
In addition to the configuration of the tag unit 3 shown in FIG. 4, the tag unit 10 includes 2-bit areas H0 and H1 for recording the number of read hits after replacement for each entry area 10a.
and record the number of read hits after a write hit (including cases where the write hit was replaced).
It includes bit areas H3 and H2 and a 1-bit area WH that stores information as to whether or not it has been replaced after a write hit.

The decoder DEC12 outputs a read hit signal, a read miss signal, and a write hit signal based on the hit/miss output of the AND circuit 6 and the read/write control signal.

The counter CTR 14 is reset by a replace signal C indicating that replacement is in progress;
In response to the read hit signal A, the value (2) of H1 and H0 read from the tag unit 10 is loaded, incremented, and stored in H1 and H0. As a result, the history of the number of read hits after replacement is recorded in areas H1 and H0. Note that when the value reaches 3, it is configured not to be incremented any further. Furthermore, storage control is performed by a control circuit (not shown).

Counter CTR 13 is reset by write hit signal B, and by read hit signal A.
After loading the values H3 and H2 read from the tag unit 10, they are incremented and stored in H3 and H2. As a result, the history of the number of read hits after write hits is recorded in areas H3 and H2. Note that when the value reaches 3, it is configured not to be incremented any further.

Reference numeral 15 denotes a flip-flop, which is set by the write hit signal B and reset by the replace signal C. If WH=1, the data has not been replaced after a write hit, so the values of H3 and H2 represent the number of read hits after a write hit.

The reading means 32 is constituted by a program and is stored in the main storage device 9. This reading means 3
2 is activated after the cache is invalidated due to the occurrence of a parity error, and the tag section data line 2 is activated from the tag section 10 to the tag section data line 2.
0 and data transceivers TRV 16, TRV 1
8, from the data section 4, TRV 17, TRV
18, each data at the time of a cache error occurrence, which is saved even after the cache is invalidated, is read out, stored in the main storage device 9, and output to a printer or the like.

By reading this record, the following is estimated. (1) If the value of the counter consisting of H1 and H0 is 1 or less, a read hit occurs due to continuous address access after replacement, indicating that the data at that time is abnormal, so it is assumed that the replacement circuit 7 is abnormal. Presumed. (2) If the counter value of H1 and H0 is 2 or more, it is abnormal because it has been hit twice or more after replacement.
It is presumed to be a soft error. (3) If WH=1 and the value of the counter made up of H3 and H2 is 1 or less, it is possible that the first read hit after the write hit caused an error, so there is an error in the write hit circuit. It is estimated to be. (4) If WH = 1 and the values of H3 and H2 are 2 or more, it is possible that the first read hit after the write hit was normal, and the second and subsequent read hits became abnormal, so it is a soft error. It is estimated to be.

As described above, by recording the history of the number of read hits after replacement and after write hits, it is possible to output the number of read hits at the time of a cache error, which facilitates failure analysis.

[0025] In the embodiment, 2 blocks are transferred as block transfers.
Although the case of long words has been shown, it goes without saying that it can be implemented regardless of the number of replacements, such as 4 long words.

[0026]

[Effects of the Invention] As explained above, since the present invention records and outputs the operation history of the cache memory,
This has the effect of facilitating failure analysis during development and maintenance of cache memory.

[Brief explanation of the drawing]

[Figure 1] Principle diagram of the present invention

[Figure 2] Principle explanatory diagram

[Figure 3] Configuration diagram of one embodiment

[Figure 4] Cache memory explanatory diagram

[Explanation of symbols]

1 Processor CPU 2 Address latch 3 Tag section 4 Data section 5 Comparator CMP 6 AND circuit 7 Replace circuit 8 Parity checker/generator PC/PG9
Main memory 10 Tag unit 11 Driver DV 12 Decoder DEC 13 14 Counter CTR 15 Flip-flop FF 16 17 18 Data transceiver 20
Tag section data line 30 First counting means 31 Second counting means 32 Reading means

Claims (1)

[Claims] 1. A data section (4) for storing a part of data stored in a main storage device; and a tag section (10) having a plurality of entry areas (10a) for registering the stored data. In a cache memory device that outputs data from the data section in the case of a read hit, replaces data from the main memory device in the case of a read miss, and updates the data in the data section in the case of a write hit, a read hit occurs for each entry. This is an operation history recording device for a cache memory that records numbers, and includes a first counting means (30), a second counting means (31), and a reading means (32), and each entry area (10a ) teeth,
It has a first area for recording the number of read hits after replacement, and a second area for recording the number of read hits after write hit, and the first counting means (30) counts the number of read hits after replacement. The second counting means (31) increments the number of read hits of the first area recorded in the corresponding entry area, and the second counting means (31) increments the number of read hits recorded in the corresponding entry area for each read hit after the write hit. The reading means (32) reads and outputs the contents of the tag section and the data section at the time when the cache memory device is disconnected due to occurrence of a cache error. A cache memory operation history recording device characterized by: