JPH04337599A - Correlation dual sampling circuit - Google Patents

Abstract

PURPOSE:To amplify a signal from a CCD without harming a characteristic for restraining a noise. CONSTITUTION:A first MOS transistor to input the non-inverse output of a previous stage to a gate is multi-stagely constituted of a source follower circuit where a second MOS transistor to impress a reference voltage on the gate is connected in cascade. The non-inverse output of the CCD is inputted to the gate of the first MOS transistor Tr5, the inverse output of the CCD is taken out of a signal inverse circuit and impressed on the gate of the second MOS transistor Tr6 and when a clock arrives, the gate voltage of the second transistor is reset by a reset transistor Tr4'.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CCD output circuit.

0002

2. Description of the Related Art FIG. 3 shows a conventional correlated double sampling circuit (hereinafter referred to as CDS circuit), in which C0
, C1, C2 are capacitances, Tr1 is a depletion type MOS transistor, Tr2 to Tr9 are enhancement type MOS transistors, VD is a power supply voltage, GND is a ground terminal, φR is a reset clock terminal for the capacitance C0, φCL is a clamp for the capacitance C1 sample hold clock terminal, CCD is charge transfer element, V0
is the output terminal. VA, VB, and VC are reference voltage terminals, and V1 to V5 indicate voltages at each point.

Next, the operation will be explained using the timing chart shown in FIG. When the φR clock enters at time t1, V1 is reset to VD, and V2 is set to VD.
-Reset to VTH2. (VTH2 is the threshold voltage of transistor Tr2.) Time t
When φR decreases at 2 and turns off the transistor Tr1, the voltages of V1 and V2 are slightly lowered due to the capacitive coupling between the gate and source of the transistor Tr1. Next, when the clamp clock φCL is input at time t3, V3 becomes V
V4 is reset to VD-VTH5. (VTH5 is the threshold voltage of transistor Tr5.) When the signal charge is transferred from the CCD at time t4 and the voltage drops, the change Vs
ig1 is transmitted to V3 by capacitive coupling by electric capacitance C1, and the potentials of V3 and V4 are approximately Vsig1.
only. When the sample clock φSH is input at time t5, the potential of V4 is transmitted to V5, and the signal charge is stored in the capacitor C2. And the sample clock φ
When SH falls, the voltage of V5 is held and V0 is output as V5-VTH8. (VTH8 is the threshold voltage of transistor Tr8.) Thereafter, from time t6, the same operation as from time t1 is repeated.

0004

[Problem to be solved by the invention] Since the conventional CDS circuit is configured as described above, the C
The signal from the CD is outputted through three stages of source followers (transistors Tr2-Tr3, Tr5-Tr6, Tr8-Tr9). Since the gain per stage of source follower is less than 1, the overall gain decreases when the signal passes through three stages of source followers, and there is a problem that the S/N ratio deteriorates for small signals. The present invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain a CDS circuit in which the signal gain does not deteriorate.

[0005]

[Means for Solving the Problems] The present invention provides a source follower circuit in which a first transistor whose control electrode receives the non-inverting output of the previous stage is connected in cascade to a second transistor whose control electrode is applied with a reference voltage. is configured in multiple stages, and C
In a correlated double sampling circuit that shifts the phase of the output of a CD using a clock signal for each stage of source follower circuit and outputs it to the next stage, an inverted signal of the output of the previous stage source follower circuit is taken out and outputted to the second stage of the next stage. A signal inverting circuit supplies the signal to the control electrode of the transistor, and a reset circuit resets the output of the signal inverting circuit using a predetermined clock signal.

[0006]

[Operation] The non-inverted signal from the previous stage is input to the control electrode of the first transistor, and the inverted signal is input to the control electrode of the cascade-connected second transistor to amplify the signal from the CCD.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of a correlated double sampling circuit according to the present invention, and the same parts as in FIG. 3 are denoted by the same reference numerals, and the explanation thereof will be omitted. In the figure, C1' is a capacitance, TrB is a depletion type MOS transistor, Tr4', TrA, ArC, and TrD are enhancement type MOS transistors, and φCL' is a capacitance C1'
This is a clamp clock terminal that clamps the clock.

Next, the operation will be explained using the timing chart shown in FIG. When clock φR enters at time t1, V1 is reset to VD, and V2 is set to VD.
-Reset to VTH2. (VTH2 is the threshold voltage of transistor Tr2.) Since transistors TrA and TrB constitute an inverting amplifier, an inverted signal of V2 appears at V6. V7 is V6-VTHC (VTHC is transistor TrC
is the threshold voltage. ). Time t2
The clock φR falls and the transistor Tr1 turns OFF.
When F, the voltages of V1 and V2 are slightly lowered due to the capacitive coupling between the gate and source of transistor Tr1, and conversely, the voltages of V6
, the voltage of V7 is slightly increased. When the clamp clocks φCL and φCL' are input at time t3, V3 becomes V
D, and V8 is reset to GND. When the charge is transferred from the CCD at time t4 and the voltage of V1 drops, the change Vsig1 is transmitted to V3 by capacitive coupling by the capacitance C1, and the potential of V3 drops by approximately Vsig1. Further, V6 increases by Vsig1 due to a change in V1, and the potential of V8 increases by approximately Vsig1 due to capacitive coupling due to capacitance C1'.

As a result, V3 decreases, so the resistance between the source and drain of transistor Tr5 increases, and V3 decreases.
8 increases, the constant 9 between the source and drain of transistor Tr6 becomes smaller, and V4 is amplified and lowered. When the sample clock φSH enters at time t5, V
The potential of 4 is transmitted to V5, and the signal charge is transferred to the capacitance C
It can be stored in 2. Then, when the clock φSH falls, the voltage of V5 is held and V0 becomes V5 - VTH.
Output as 8. (VTH8 is a transistor Tr
8 threshold voltage. ) and below, time t6
From then on, the same operation as at time t1 is repeated.

0010

[Effects of the Invention] As described above, according to the present invention, by using a non-inverted signal and an inverted signal, it is possible to amplify a signal without impairing the noise suppression characteristics of the CDS circuit. This has the effect that the S/N ratio does not deteriorate even when

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of a correlated double sampling circuit according to the present invention.

FIG. 2 is a timing chart showing the operation of FIG. 1;

FIG. 3 is a diagram of a conventional correlated double sampling circuit.

FIG. 4 is a timing chart showing the operation of FIG. 3;

[Explanation of symbols]

Claims (1)

[Claims] Claim 1: A multi-stage source follower circuit is constructed in which a first transistor inputting the non-inverting output of the previous stage to a control electrode is cascaded to a second transistor to which a reference voltage is applied to the control electrode. In a correlated double sampling circuit in which the output is phase-shifted by a clock signal for each source follower circuit in each stage and outputted to the next stage, an inverted signal of the output of the previous stage source follower circuit is taken out and output to the second transistor in the next stage. 1. A correlated double sampling circuit comprising: a signal inversion circuit that supplies a signal to a control electrode; and a reset circuit that resets the output of the signal inversion circuit using a predetermined clock signal.