JPH043370U - - Google Patents
Info
- Publication number
- JPH043370U JPH043370U JP4229690U JP4229690U JPH043370U JP H043370 U JPH043370 U JP H043370U JP 4229690 U JP4229690 U JP 4229690U JP 4229690 U JP4229690 U JP 4229690U JP H043370 U JPH043370 U JP H043370U
- Authority
- JP
- Japan
- Prior art keywords
- under test
- insulating substrate
- position corresponding
- terminal
- output terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 1
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Testing, Inspecting, Measuring Of Stereoscopic Televisions And Televisions (AREA)
Description
第１図はこの考案の一実施例を説明するための
側面図、第２図はこの考案による校正用治具の回
路構造を説明するための接続図、第３図はこの考
案による校正用治具の実施例を説明するためのブ
ロツク図、第４図はその動作を説明するための波
形図、第５図は従来のアナログＩＣテスタの校正
方法を説明するためのブロツク図である。
１００……アナログＩＣテスタ本体、２００…
…被試験アナログＩＣ、３００……ＤＵＴボード
、５００……校正用治具、５０１……絶縁基板、
５０２，５０２Ａ〜５０２Ｎ，５０２Ｑ……導電
ピン、５０３……マルチプレクサ。
Figure 1 is a side view for explaining one embodiment of this invention, Figure 2 is a connection diagram for explaining the circuit structure of the calibration jig according to this invention, and Figure 3 is a side view for explaining an embodiment of the calibration jig according to this invention. FIG. 4 is a waveform diagram for explaining its operation, and FIG. 5 is a block diagram for explaining a conventional method of calibrating an analog IC tester. 100...Analog IC tester body, 200...
...Analog IC under test, 300...DUT board, 500...Calibration jig, 501...Insulating substrate,
502, 502A to 502N, 502Q...conductive pins, 503...multiplexer.
Claims (1)
基板に植設された複数の導電ピンと、 Ｂ 上記絶縁基板に実装され被試験ＩＣに信号が
印加される端子に対応する位置の導電ピンを入力
端子に接続し、被試験ＩＣの出力端子に対応する
位置の導電ピンを出力端子に接続したマルチプレ
クサと、 によつて構成したアナログＩＣテスタの校正用治
具。[Scope of Claim for Utility Model Registration] A. A plurality of conductive pins implanted on an insulating substrate in the same arrangement as the terminal arrangement of the IC under test, and B. Terminals mounted on the above insulating substrate to which signals are applied to the IC under test. A multiplexer having a conductive pin at a position corresponding to the input terminal connected to the input terminal and a conductive pin at a position corresponding to the output terminal of the IC under test connected to the output terminal;
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4229690U JP2517456Y2 (en) | 1990-04-20 | 1990-04-20 | Calibration tool for analog IC tester |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4229690U JP2517456Y2 (en) | 1990-04-20 | 1990-04-20 | Calibration tool for analog IC tester |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH043370U true JPH043370U (en) | 1992-01-13 |
| JP2517456Y2 JP2517456Y2 (en) | 1996-11-20 |
Family
ID=31553718
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4229690U Expired - Fee Related JP2517456Y2 (en) | 1990-04-20 | 1990-04-20 | Calibration tool for analog IC tester |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2517456Y2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4313799B2 (en) * | 2003-09-09 | 2009-08-12 | 株式会社アドバンテスト | Calibration comparison circuit |
-
1990
- 1990-04-20 JP JP4229690U patent/JP2517456Y2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2517456Y2 (en) | 1996-11-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| DE69028435D1 (en) | Integrated circuit with test circuit | |
| JPH043370U (en) | ||
| JPS62124572U (en) | ||
| JPS6230971A (en) | Semiconductor integrated circuit device | |
| JPS63142767U (en) | ||
| JPH0132393Y2 (en) | ||
| JPH0344580A (en) | Bias test board for semiconductor device | |
| JPS5848580Y2 (en) | Indicator/Recorder | |
| JPH0582769B2 (en) | ||
| JPH01298665A (en) | Pin grid array socket with auxiliary terminal | |
| JPH0261717B2 (en) | ||
| JPS6393576U (en) | ||
| JPH01107973U (en) | ||
| JPH056375B2 (en) | ||
| JPS6439565A (en) | Test board for semiconductor device | |
| JPS6124249A (en) | Master slice system semiconductor integrated circuit device | |
| JPS6234383U (en) | ||
| JPS61189278U (en) | ||
| JPS63178326U (en) | ||
| JPS62239542A (en) | Probe card | |
| JPS63157936U (en) | ||
| JPS63265U (en) | ||
| JPH0239179U (en) | ||
| JPH029884U (en) | ||
| JPH0449881U (en) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |