JPH04336453A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH04336453A
JPH04336453A JP13848691A JP13848691A JPH04336453A JP H04336453 A JPH04336453 A JP H04336453A JP 13848691 A JP13848691 A JP 13848691A JP 13848691 A JP13848691 A JP 13848691A JP H04336453 A JPH04336453 A JP H04336453A
Authority
JP
Japan
Prior art keywords
semiconductor device
groove
ceramic substrate
chassis
metal plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13848691A
Other languages
Japanese (ja)
Inventor
Yasuichi Ikeda
池田 保一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP13848691A priority Critical patent/JPH04336453A/en
Publication of JPH04336453A publication Critical patent/JPH04336453A/en
Pending legal-status Critical Current

Links

Landscapes

  • Mounting Of Printed Circuit Boards And The Like (AREA)

Abstract

PURPOSE:To protect a ceramic substrate against cracking by making a groove in the bottom face of the metal board of a semiconductor device, when a set of semiconductor device is assembled on a chassis, thereby protecting the ceramic substrate against driving stress of screw due to irregularities or foreign matter on the surface of the chassis. CONSTITUTION:A screw 5 is inserted into a fixing hole 3a of a metal board 3' in order to secure a semiconductor device to a chassis 4. A groove 6 is made in the bottom face of the metal board 3' between the end face of a ceramic substrate 1 mounted on the metal board 3' and the screw hole 3a. Consequently, even if irregularities or foreign matter exists on the surface of the chassis 4, driving force of screw is absorbed at the part which is made thin through the groove 6 thus suppressing the stress to be applied on the ceramic substrate as low as possible. Furthermore, since the groove 6 is made in the bottom face of the metal board 3', solder is prevented from flowing into the groove.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】この発明はセラミック基板を金属
板の上に搭載した半導体装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a semiconductor device in which a ceramic substrate is mounted on a metal plate.

【0002】0002

【従来の技術】図2は従来の半導体装置を示す断面図で
あり、図において、1はセラミック基板、2は半田、3
は金属板、3aは取付穴である。このような半導体装置
において、セラミック基板1と金属板3は半田2によっ
て接合されている。
2 is a sectional view showing a conventional semiconductor device. In the figure, 1 is a ceramic substrate, 2 is a solder, and 3 is a sectional view showing a conventional semiconductor device.
is a metal plate, and 3a is a mounting hole. In such a semiconductor device, a ceramic substrate 1 and a metal plate 3 are bonded together by solder 2.

【0003】次に動作について説明する。図2に示すよ
うに、金属板3の取付穴3aにネジ5を挿入し、このネ
ジ5によって半導体装置はシャーシ4に固定される。
Next, the operation will be explained. As shown in FIG. 2, screws 5 are inserted into the mounting holes 3a of the metal plate 3, and the semiconductor device is fixed to the chassis 4 by the screws 5.

【0004】0004

【発明が解決しようとする課題】従来の半導体装置は以
上のように構成されているので、シャーシの表面に凸凹
があったり、金属板の裏面とシャーシの表面との間に異
物が介在した場合、ネジ止め時の力により、ストレスが
セラミック基板に加わり、基板にクラックが入ったり、
基板が割れるなどの問題があった。
[Problems to be Solved by the Invention] Conventional semiconductor devices are constructed as described above, so if the surface of the chassis is uneven or a foreign object is present between the back surface of the metal plate and the surface of the chassis, , stress is applied to the ceramic board due to the force of screwing, which may cause cracks in the board,
There were problems such as the board breaking.

【0005】この発明は上記のような問題点を解消する
ためになされたもので、高出力用の半導体装置をセット
のシャーシ上に組み立てる場合、シャーシ表面の凸凹や
、異物の介在があってもネジ止め時の力がセラミック基
板に加わり基板割れが生じることを防止することができ
る半導体装置を得ることを目的とする。
[0005] This invention was made to solve the above-mentioned problems, and when a high-output semiconductor device is assembled on a chassis of a set, even if there are irregularities on the chassis surface or foreign objects are present, An object of the present invention is to obtain a semiconductor device that can prevent the occurrence of substrate cracking due to force applied to a ceramic substrate when screwing.

【0006】[0006]

【課題を解決するための手段】この発明に係る半導体装
置は、セラミック基板の端面と金属板のネジ締め部の間
で金属板のセラミック基板搭載部と反対側の面に溝を設
けた構造をもつようにしたものである。
[Means for Solving the Problems] A semiconductor device according to the present invention has a structure in which a groove is provided on the surface of the metal plate opposite to the ceramic substrate mounting portion between the end surface of the ceramic substrate and the screw tightening portion of the metal plate. It was designed to last.

【0007】[0007]

【作用】この発明による半導体装置は、金属板に下面よ
り溝を設けているので、シャーシ表面の凸凹や異物の介
在があっても、それらによってネジ止め時に発生する力
がその溝により厚みの薄くなった場所で吸収され、セラ
ミック基板へのストレスを極力防止することができる。
[Operation] In the semiconductor device according to the present invention, the grooves are formed in the metal plate from the bottom surface, so even if there are irregularities on the chassis surface or foreign objects, the force generated when screwing is absorbed by the grooves and the thickness is reduced. The stress on the ceramic substrate can be prevented as much as possible.

【0008】また、溝は金属板の下面に設けられている
ので、半田付時に半田が溝に流れ込むのを防ぐことがで
きる。
Furthermore, since the groove is provided on the lower surface of the metal plate, it is possible to prevent solder from flowing into the groove during soldering.

【0009】[0009]

【実施例】以下、この発明の一実施例を図について説明
する。図1は本発明の一実施例による半導体装置を示す
断面図であり、図において、1はセラミック基板、2は
半田、3’はこの発明による金属板で、金属板3’上に
接合されたセラミック基板の端面の位置する部分とネジ
止め部3aの間において金属板3’の下面から溝6を設
けた構造になっている。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention. In the figure, 1 is a ceramic substrate, 2 is solder, and 3' is a metal plate according to the present invention, which is bonded on the metal plate 3'. It has a structure in which a groove 6 is provided from the lower surface of the metal plate 3' between the portion where the end surface of the ceramic substrate is located and the screw fixing portion 3a.

【0010】次に動作について説明する。図1に示すよ
うに、金属板3’の取り付け穴3aにネジ5を挿入し、
このネジ5により半導体装置はシャーシ4に固定される
。この時、金属板3’の下面に設けられた溝6が、金属
板3’上のセラミック基板1の端面とネジ取り付け穴3
aの間に位置する。
Next, the operation will be explained. As shown in FIG. 1, insert the screw 5 into the mounting hole 3a of the metal plate 3',
The semiconductor device is fixed to the chassis 4 by the screws 5. At this time, the groove 6 provided on the lower surface of the metal plate 3' connects the end surface of the ceramic substrate 1 on the metal plate 3' with the screw mounting hole 3.
Located between a.

【0011】このように本実施例によれば、半導体装置
の基板を接合する金属板3’の下面に溝6を設けた構成
としたから、この装置をシャーシ上に組み立てる際に、
シャーシ表面の凸凹や異物の介在によりネジ止め時の力
が基板にストレスとして加わるのを防止でき、従って基
板のクラック等が防止できる。
As described above, according to this embodiment, since the groove 6 is provided on the lower surface of the metal plate 3' to which the substrate of the semiconductor device is bonded, when assembling this device on the chassis,
It is possible to prevent the force applied when screwing the screws from being applied as stress to the board due to irregularities on the surface of the chassis or the presence of foreign matter, and therefore cracks in the board can be prevented.

【0012】また、本実施例においては、該溝は下面に
設けたので、半田付け時に半田がその溝に流れこむこと
はない。
Furthermore, in this embodiment, since the groove is provided on the bottom surface, solder does not flow into the groove during soldering.

【0013】[0013]

【発明の効果】以上のようにこの発明によれば、半導体
装置の金属板の下面に溝を設けたことにより、当該装置
をセットのシャーシ上に組み立てる場合、シャーシ表面
の凸凹や異物の介在によりネジ止め時の力がセラミック
基板に加わるストレスを極力防止することが可能になり
、基板のクラックや割れの防止対策の向上が図れる効果
がある。
As described above, according to the present invention, by providing a groove on the lower surface of a metal plate of a semiconductor device, when the device is assembled on a chassis of a set, unevenness on the surface of the chassis or the presence of foreign matter can be avoided. This makes it possible to prevent as much stress as possible from being applied to the ceramic substrate during screw tightening, which has the effect of improving measures to prevent cracks and splits in the substrate.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】本発明による半導体装置の側面図である。FIG. 1 is a side view of a semiconductor device according to the present invention.

【図2】従来の半導体装置の側面図である。FIG. 2 is a side view of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1    セラミック基板 2    半田 3    金属板 4    シャーシ 5    ネジ 6    溝 3a  ネジ止め穴 1 Ceramic substrate 2 Solder 3 Metal plate 4 Chassis 5 Screw 6 Groove 3a Screw hole

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  半導体素子ならびに回路を表面に形成
したセラミック基板を半田付により金属板上に搭載した
半導体装置において、上記セラミック基板の端面と金属
板のネジ止め部の間で、上記金属板のセラミック基板搭
載部と反対側に溝を設けたことを特徴とする半導体装置
1. In a semiconductor device in which a ceramic substrate on which a semiconductor element and a circuit are formed is mounted on a metal plate by soldering, the metal plate is disposed between the end face of the ceramic substrate and the screwed portion of the metal plate. A semiconductor device characterized in that a groove is provided on the side opposite to the ceramic substrate mounting part.
JP13848691A 1991-05-13 1991-05-13 Semiconductor device Pending JPH04336453A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13848691A JPH04336453A (en) 1991-05-13 1991-05-13 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13848691A JPH04336453A (en) 1991-05-13 1991-05-13 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH04336453A true JPH04336453A (en) 1992-11-24

Family

ID=15223221

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13848691A Pending JPH04336453A (en) 1991-05-13 1991-05-13 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH04336453A (en)

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