JPH0433412A - Re-timing circuit - Google Patents

Abstract

PURPOSE:To attain pulse delete processing or pulse addition processing effectively by adjusting a change timing by a timing adjustment means when the result of detection of a phase difference shows the same consecutive codes for the prescribed number of times. CONSTITUTION:A counter 12 counts the number of times of consecutive '+' or '-' and a comparator circuit 13 compares the count with a predetermined reference value. When the number of times of the same code state of a phase difference reaches a reference value, a pulse width signal is outputted from the comparator circuit 13 and inputted to a weighting circuit 11. That it, the counter 12 and the comparator circuit 13 are provided to apply weighting when the same code state of the internal timing, the reception data and the phase difference is consecutive for the prescribed number of times of over, that is, the phase between the internal timing and the reception data is deviated. Thus, the pulse delete processing or pulse addition processing are quickly implemented.

Description

TECHNICAL FIELD The present invention relates to a retiming circuit, and more particularly to a retiming circuit that controls received data containing jitter to follow the internal timing of a device.

Conventional technology Conventionally, in this type of retiming circuit, internal timing is sampled using received data that includes jitter, and pulse addition processing or pulse deletion processing is performed by weighting only the absolute value of the delay amount between the internal timing and the received data. By dividing the result and using it as the internal timing,
The internal timing was made to follow the received data.

In other words, in the conventional retiming circuit, pulse addition processing or pulse deletion processing is performed every time the received data changes. Therefore, there is a drawback that the jitter of the received data is directly reflected in the internal timing, and the operation of the circuits of each part of the device using the internal timing as a clock becomes unstable.

In addition, in order to solve this problem, a reversible counter is provided,
It is also possible to consider a configuration in which pulse addition processing or pulse deletion processing is performed only when the counted value exceeds a predetermined value. In other words, the pulse addition process or the pulse deletion process is not performed every time, but only when the count value exceeds a predetermined value.

The conventional retiming circuit will be explained using FIG. 2.

FIG. 2 is a block diagram showing the configuration of a conventional retiming circuit. In the figure, terminal I of this retiming circuit
Received data a is input to N2.

In addition, in this retiming circuit, the phase difference between the internal timing b input to the terminal INI and the received data a input to the terminal IN2 is weighted, and the signal n of the terminal OUT, which is the output thereof, is Control is performed so that the frequency is divided by a frequency generator and fed back to the terminal IN1.

In order to perform such control, first, the delay amount detection circuit 8
Find the phase difference between internal timing b and received data a. The phase difference C is input to the bit conversion circuit 9.

In the bit conversion circuit 9, the phase difference C is punched out using the clock p from the oscillator 1 and replaced with digital data X. For example, when punching out the phase difference C shown in FIG. 7 using the clock p, the digital data X becomes "51".

Returning to FIG. 2, the digital data value X is the comparator circuit 10.
are input and compared with several types of reference values. Then, a signal with a pulse width corresponding to the comparison result is input to the weighting circuit 11.

For example, if the standard value is 1.5.10, the 5th
As shown in the table in Figure (a), the bit conversion circuit 9
The value X of the digital data replaced in is 1.5
．． It is determined which of the three reference values of 10 it is between. If the determination result is A-D in FIG. 12A, the corresponding signal having the pulse width A-D in FIG.

Returning to FIG. 2, the -time storage circuit 5 temporarily stores and holds received data a or internal timing b, and has input/output terminals as shown in FIG. In other words, the internal timing b is input to the data input terminal, and the received data a is input to the clock terminal, and the signal that rises first is held at "1", and the signal that rises later is held at "0". be done. Therefore, one of the output d corresponding to the internal timing b and the output e corresponding to the received data a is always “
1" and the other as "0°. It should be noted that a well-known flip-flop is used in this negative time storage circuit, and the arrangement of the input/output terminals of the other temporary storage circuits in FIG. 2 is also the same.

Returning to FIG. 2, in the circuit 11, the weighting is performed using the internal timing b held in the -time storage circuit 5 and the received data a.
The one that is ahead in phase, that is, the one that rises first, is weighted in accordance with the pulse width of the signal from the comparison circuit 10. This weighting is carried out in the circuit 11 by punching out the signal of a predetermined pulse width from the comparator circuit 10 at the clock p, similar to the bit conversion circuit 9, and replacing it with the signal f or g. In other words, the comparison circuit 10
The weighting is performed according to the pulse width of the signal from the signal, that is, the phase difference.

For weighting, the processed signals f and g are processed using a reversible counter (up/down).
down counter) 6. This reversible counter 6 counts the number of pulses of a signal added by processing, and the weighting counts up according to the number of pulses of the output signal f of the circuit 11, and counts up the number of pulses of the output signal g. Count down according to the number. Then, when the counted value reaches a predetermined value, the NAND condition of the NAND circuit 14 is satisfied. Since the NAND circuit 14 of this example has three inputs, that is, three bits, the count value is “7” (“1” in binary).
11''), the NAND condition is satisfied. Note that the reversible counter 6 is reset by the temporary storage circuit 2.

Here, the switch 7 is provided to forcibly establish the NAND condition of the NAND circuit 14. The three outputs of this switch 7 correspond to each of the three outputs of the reversible counter 6, and the value of each corresponding bit can be forcibly set to "1". In other words, the setting value of this switch 7 can determine the opening degree for performing pulse deletion processing or pulse addition processing.

For example, if you want to satisfy the NAND condition when the count value is "3"("011" in binary), set the switch 7 so that the most significant bit of the 3-bit output is always "1". By doing this, the count value will be 3.
When it becomes @, the input value of the NAND circuit 14 is “111”
(binary number), the NAND condition is satisfied, and the output m is “0”.
It becomes ゛.

Note that the NAND condition is established only when the count value of the reversible counter reaches a predetermined value, so in the above example, the count is increased by the number of pulses of the output signal f, and While counting down by the number, the count value increases, and the NAND condition is satisfied only when the count value reaches "3".

When the NAND condition of the NAND circuit 14 is satisfied, pulse deletion processing or pulse addition processing is performed. Below, the operation of each part of the circuit will be explained separately for the case where the internal timing b is ahead of the received data a and the case where the received data a is ahead of the internal timing b.

(1) When internal timing b is ahead of received data a First, as described above, the phase difference C between internal timing b and received data a is punched out using clock p in the bit conversion circuit 9, and converted into digital data X. Convert. The digital data X is compared with several types of reference values in a comparator circuit 10, and a signal having a pulse width corresponding to the comparison result is given to a weighting circuit 11. In the weighting circuit 11, the pulse width of the signal is further punched out using the clock p.

Here, referring to the time chart of FIG. 3, the weighted result of punching in the circuit 11 is added to the output d of the temporary storage circuit 5 corresponding to the advancing internal timing b, and the output signal f is The waveform will have pulses added like this.

This output signal f causes the count value of the reversible counter 6 to be counted up, and when the NAND condition of the NAND circuit 14 is satisfied, the output m is inputted to the preset terminal of the temporary storage circuit 2. Then, the data output becomes “1”,
-The clear state of the time memory circuit 3 is released, and the data output j
becomes “0” (■). As a result, the - hour memory circuit 4 is temporarily brought into a clear state, and its data output l becomes 0'' (■).

However, the data output j of the temporary memory circuit 3 which uses this data output l as the data input becomes "1" at the next clock, and as a result, the data output of the -hour memory circuit 2 becomes "0".
Become (■)

In the above operations of temporary storage circuits 2.3 and 4, -
There are times when the data output of the time memory circuit 3 becomes "1", but the output e of the -time memory circuit 5 is always "0". Therefore, the output q of the NAND circuit 15 is always "1". .

Furthermore, the NAND circuit 16 which receives the output q of the NAND circuit 15 and the data output k of the - hour memory circuit 4 has an output n of "0" when the - hour memory circuit 4 is in the clear state.
It becomes 1. Therefore, the pulse is deleted due to the "0" period. The above is the pulse deletion process.

When the pulse deletion process is performed, the frequency of the output n decreases. When this output n is divided by a frequency divider (not shown), the frequency of the divided signal, that is, the internal timing b, decreases. Therefore, the pulse width of internal timing b becomes larger,
This allows the internal timing b to follow the rising retiming of the received data a.

(2) When received data a is ahead of internal timing b First, as described above, the phase difference C between internal timing b and received data a is punched out using clock p in the bit conversion circuit 9, and converted into digital data X. Convert. The digital data X is compared with several types of reference values in a comparator circuit 10, and a signal having a pulse width corresponding to the comparison result is given to a weighting circuit 11. In the weighting circuit 11, the pulse width of the signal is further punched out using the clock p.

Here, referring to the time chart of FIG. 4, the output e of the temporary storage circuit 5 corresponding to the advanced received data a
For weighting, the result of punching in the circuit 11 is added, and the output signal g has a waveform with added pulses as shown in the figure.

This output signal g causes the reversible counter 6 to count up 11 values, and when the NAND condition of the NAND circuit 14 is satisfied, the output m is input to the preset terminal of the temporary storage circuit 2. Then, the data output j becomes "1", the clear state of the negative time memory circuit 3 is released, and the data output j becomes "0" (■). As a result, - time memory circuit 4
is temporarily cleared, and its data output g is “0”.
”become (■).

However, the data output j of the temporary memory circuit 3 which uses this data output g as the data input becomes "1" at the next clock, and as a result, the data output of the -hour memory circuit 2 becomes "0".

In the above operations of temporary storage circuits 2.3 and 4, -
There are times when the data output of the time memory circuit 3 becomes "1", and the output e of the -time memory circuit 5 is always "1", so there are times when the output q of the NAND circuit 15 becomes "0". be.

Furthermore, the NAND circuit 16 which receives the output q of the NAND circuit 15 and the data output k of the - hour memory circuit 4 as inputs has the output q of the NAND circuit 15 as "0" when the - hour memory circuit 4 is in the clear state. Then, the output n becomes "1" (■). Therefore, a pulse is added during the period in which the output n is "1". The above is the pulse addition process.

When the pulse addition process is performed, the frequency of the output n increases. When this output n is divided by a frequency divider (not shown), the frequency of the divided signal, that is, the internal timing b increases. Therefore, the pulse width of internal timing b becomes smaller,
This allows the internal timing b to follow the rising retiming of the received data a.

However, in the conventional retiming circuit described above, pulse deletion processing or pulse addition processing is performed when the count value of the reversible counter exceeds a predetermined value, and the received data is continuously delayed with respect to the internal timing. Even if the count value exceeds the predetermined value, there is a drawback that processing is performed in the same manner as when the count value exceeds the predetermined value while repeatedly going up and down.

OBJECTS OF THE INVENTION The present invention has been made to solve the above-mentioned conventional drawbacks, and its purpose is to provide a retiming circuit that can more effectively perform pulse deletion processing or pulse addition processing. .

Structure of the Invention A retiming circuit according to the present invention includes a detection means for detecting a phase difference between a change timing of received data and a change timing of an internal clock of the device, and adjusts a change timing of the internal clock according to the detection result. a retiming circuit having a timing adjustment means, the retiming circuit having a timing adjustment means, the retiming circuit controlling the timing adjustment means to adjust the change timing when the detection result of the phase difference by the detection means is the same sign for a predetermined number of consecutive times; It is characterized by having timing adjustment control means.

Example Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of a retiming circuit according to the present invention, and parts equivalent to those in FIG. 2 are designated by the same reference numerals. In the figure, the retiming circuit according to an embodiment of the present invention differs from that in FIG. 2 in that a counter 12 and a comparison circuit 13 are added.

First, in the comparator circuit 10, digital data X is compared with several types of reference values, similar to the conventional example shown in FIG. In the comparison operation, the continuous state of the sign of the phase difference is determined. For example, if the state where the internal timing is delayed than the received data is "+" and the state where the received data is delayed than the internal timing is "-", then
The number of consecutive +'' or - is output to the counter 12.

The counter 12 counts the number of consecutive "+" or -". Then, the comparison circuit 13 compares the counted value with a predetermined reference value. Same sign state of phase difference When the number of times reaches the reference value, a signal with a predetermined pulse width is output from the comparator circuit 13, and the weighting is input to the circuit 11.

In other words, the counter 12 and the comparison circuit 13 weight the internal timing and the received data when the same sign state of the phase difference continues for a predetermined number of times or more, that is, when the internal timing and the received data are out of phase. It is designed to do this.

In the circuit 11, the weighting is performed by first adding the pulse widths of the output signal of the comparator circuit 10 and the output signal of the comparator circuit 13, and punching out the pulse width of the signal after the addition using the clock p, and adding it to the signal f or g. The weighting of replacement performs processing.

In other words, in the conventional retiming circuit shown in FIG. 2, counting is performed without considering the state of the sign of the phase difference, whereas in this embodiment, the sign of the phase difference between the internal timing and the received data is the same. When the number of consecutive times exceeds a predetermined value, the reversible counter gives more weight to the count. As a result, if the internal timing and the received data are out of phase, the count value of the reversible counter will reach the predetermined value earlier, so pulse deletion processing or pulse addition processing will be performed sooner, and the internal This allows timing jitter to be kept low.

Note that in this embodiment, weighting is performed according to the comparison results of both the comparison circuit 10 and the comparison circuit 13, but even if weighting is performed according to the comparison result of only the comparison circuit 13, the pulse deletion process can be performed more quickly. Alternatively, it is clear that pulse addition processing is performed.

As described in detail, the present invention takes into account the number of consecutive times in which the sign of the phase difference between the internal timing and the received data is the same, and performs pulse deletion processing or pulse addition processing earlier, thereby improving the internal timing. This has the effect of keeping the jitter low.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the configuration of a retiming circuit according to an embodiment of the present invention, Figure 2 is a block diagram showing the configuration of a conventional retiming circuit, and Figure 3 is a diagram showing the case where the internal timing is ahead of the received data. Figure 4 is a time chart when the internal timing is behind the received data, Figure 5 (a) is a table showing an example of the weighting reference value in the circuit, and Figure 5 (b) is the same. A waveform diagram showing an example of the pulse width corresponding to the reference value in Figure (b), Figure 6 is a layout diagram of each input/output terminal of the temporary storage circuit, and Figure 7 is a conceptual diagram of bit conversion processing in the bit conversion circuit. be. Explanation of symbols of main parts 1... Oscillator 2.3.4.5... - Time memory circuit 6...
- Reversible counter 8...Delay amount detection circuit 9...Bit conversion circuit 10.13...Comparison circuit 11...Weighting circuit 12... ...Counting circuit diagram 2

Claims (1)

[Claims] (1) detection means for detecting a phase difference between the change timing of the received data and the change timing of the internal clock of the device;
a retiming circuit having a timing adjustment means for adjusting the change timing of the internal clock according to the detection result, when the detection result of the phase difference by the detection means is the same sign for a predetermined number of consecutive times; A retiming circuit comprising timing adjustment control means for controlling the change timing by the timing adjustment means.