JPH04334126A - Phase detection circuit - Google Patents

Abstract

PURPOSE:To eliminate a dead band area by applying a measured signal to two phase detection circuits, applying a reference signal to one phase detection circuit, applying a reference signal delayed at a delay line by a width of a dead band area to the other phase detection 1 circuit and adding detection outputs of the phase detection circuits. CONSTITUTION:When a phase difference between a reference signal 1A and a measured signal 1B is large, an output of a comparator 7 turns off an analog switch 8, only an output of a phase detection circuit 3A is outputted to an output terminal 10, and when the phase difference between the reference signal 1A and the measured signal 1B is small, an output of the comparator 7 turns off the analog switch 8 and a sum signal of outputs of the phase detectors 3A, 3B is outputted from the output terminal 10.

Description

[Detailed description of the invention]

0001

[Industrial Field of Application] This invention relates to a phase shifter for communication equipment.
It concerns phase detection circuits used in lock-loop synchronous circuits, phase-lock loop oscillator circuits for frequency synthesizers, etc.

0002

2. Description of the Related Art Next, the configuration of a phase detection circuit according to the prior art will be explained with reference to FIG. 1A in Fig. 4 is a reference signal, 1B
3A is a phase detector, 4A is a low-pass filter, and 5A is an adder circuit. Phase detector 3A is MC404
This is a frequency phase detection type phase detector represented by No. 4.

Next, the operation of the phase detection circuit shown in FIG. 4 will be explained with reference to FIG. FIG. 5A is a waveform diagram of the reference signal 1A,
FIG. 5A is a waveform diagram of the signal under test 1B. The phase θ1 in FIG. 5A is ahead of the phase θ2 in FIG. 5B. FIG. 5C shows a voltage waveform at the terminal 33 of the phase detector 3A, which is a signal having a pulse width equal to the difference between the phases θ1 and θ2. FIG. 5D shows a voltage waveform at the terminal 34 of the phase detector 3A, which is fixed at H level.

Next, the waveform when the phase θ2 is ahead of the phase θ1 will be explained with reference to FIG. 6A to 6E correspond to FIGS. 5A to 5E, respectively. The terminal 33 of the phase detector 3A is fixed at H level, and the output of the terminal 34 of the phase detector 3A becomes a signal having a pulse width proportional to the phase difference, as shown in FIG. 6D. The output of the phase detector 3A is converted into a signal proportional to the phase difference by a low-pass filter 4A.

Next, the relationship between the phase difference between phases θ1 and θ2 and the output of the low-pass filter 4A will be explained with reference to FIG. 7A shows the signal waveform at the terminal 43 of the low-pass filter 4A, and FIG. 7B shows the signal waveform at the terminal 44 of the low-pass filter 4A. The output of the low-pass filter 4A is input to an adder circuit 5A. The adder circuit 5A calculates the difference between the signals and outputs the difference. FIG. 7C shows the output waveform of the adder circuit 5A.

[0006]

In FIG. 4, the width of the pulse signal generated at the terminals 33 and 34 is not proportional to the phase difference (θ1-θ2) due to the internal delay time of the phase detector 3A. A dead area like this is created.

[0007] In this invention, the signal under test is applied to two phase detection circuits, the reference signal is applied as is to one of the phase detection circuits, and the reference signal is applied to the other phase detection circuit using a delay line. It is an object of the present invention to provide a phase detection circuit that eliminates a dead area by adding a signal delayed by the amount of time and adding the detection outputs of two phase detection circuits.

[0008]

[Means for Solving the Problem] In order to achieve this object, the present invention includes a phase detector 3A having a reference signal 1A connected to an input terminal 31 and a signal under test 1B connected to an input terminal 32; A delay line 2 that delays the reference signal 1A by the width of the dead area, a phase detector 3B to which the output of the delay line 2 is connected to the input terminal 36 and the signal under test 1B to the input terminal 37, and a phase detector 3A. A low-pass filter 4A receives the output of the phase detector 3B, a low-pass filter 4B receives the output of the phase detector 3B, an adder circuit 5A receives the output of the low-pass filter 4A, and the output of the low-pass filter 4B receives the output of the low-pass filter 4B. An adder circuit 5B as an input, a comparator 7 connected to the output of the adder circuit 5B, an analog switch 8 connected to the output of the adder circuit 5B and controlled by the output of the comparator 7, and an output of the adder circuit 5A. and an inverting amplifier 9 that adds the outputs of the analog switch 8 and the reference signal 1A.When the phase difference between the reference signal 1A and the signal under test 1B is large, the analog switch 8 is turned off by the output of the comparator 7, and the output of the phase detector 3A is When the phase difference between the reference signal 1A and the signal under test 1B becomes small, the analog switch 8 is turned on, and the sum signal of the outputs of the phase detector 3A and the phase detector 3B is output to the output terminal 10.
Output from 0.

[0009]

[Operation] Next, the configuration of the phase detection circuit according to the present invention will be explained with reference to FIG. In Figure 1, 2 is a delay line, 3B is a phase detector, 4B is a low-pass filter, 5B is an adder circuit, 6A and 6B
7 is a resistor, 7 is a comparator, 8 is an analog switch, 9 is an inverting amplifier, 10 is an output terminal, and the others are the same as in FIG. The reference signal 1A and the signal under test 1B are input to a phase detector 3A, and the phase detection signal is input to a low-pass filter 4A.
are added by the adder circuit 5A.

The reference signal 1A is input to the terminal 36 of the phase detector 3B via the delay line 2, and the signal under test 1B is input to the terminal 37 of the phase detector 3B. The delay line 2 is for delaying by the width of the dead area. The outputs of the phase detector 3B are added from the low-pass filter 4B by an adder circuit 5B. The output of the adder circuit 5B is the analog switch 8 and the comparator 7.
is input. Comparator 7 outputs a control signal according to the output of adder circuit 5B. By appropriately setting the operating voltage of the comparator 7, the comparator 7 operates the analog switch 8 using a control signal, and when the output of the adder circuit 5B becomes small, the analog switch 8 is turned on, and the phase detector 3A and phase detector The detected signals from the detector 3B are added together by an inverting amplifier 9 and output. When the output of the adder circuit 5B becomes large, the comparator 7 turns off the analog switch 8 and outputs only the output of the phase detector 3A.

Next, the signal waveform diagram of FIG. 1 will be explained with reference to FIG. 2. FIG. 2A shows the output waveform of the adder circuit 5A, and like FIG. 7C, there is a dead area. Figure 2A shows the adder circuit 5.
This is the output waveform of B, and there is a dead area. FIG. 2C is a waveform diagram of a control signal that is the output of the comparator 7 and turns the analog switch 8 on and off. When the voltage value in Fig. 2A becomes larger than the set voltage value of comparator 7, Fig. 2C turns off.
When the voltage value in FIG. 2A becomes smaller than the set voltage value of the comparator 7, the voltage in FIG. 2C turns on. FIG. 2D is a waveform diagram of the output terminal 10, in which the output of the phase detector 3A is switched -180
The slope of the signal waveform at the output terminal 10 is φ~ except for the points at +180° and the point where the analog switch 8 turns on and off.
It is maintained between 2φ and there is no dead area.

0012

Embodiment Next, the circuit of the embodiment shown in FIG. 1 will be explained with reference to FIG. 2A and 2B in FIG. 3 are logic circuits forming the delay line 2. In FIG. The low-pass filters 4A and 4B are composed of resistors and capacitors. Adder circuits 5A and 5B each include three operational amplifiers.

[0013]

[Effects of the Invention] According to the present invention, the signal under test is applied to two phase detection circuits, the reference signal is directly applied to one of the phase detection circuits, and the reference signal is applied to the other phase detection circuit using a delay line. Since a signal delayed by the width of the dead area is added and the detection outputs of the two phase detection circuits are added, the dead area that occurs in the frequency phase detection type phase detection circuit can be eliminated. At the same time, by controlling the summation circuit of the outputs of two phase detectors according to the output voltage of the phase detector, the range of -180° to +180° is the same as when operating with one phase detector. It can operate as a phase detection circuit over the entire range.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a phase detection circuit according to the present invention.

FIG. 2 is a signal waveform diagram of FIG. 1;

FIG. 3 is a circuit diagram of the embodiment of FIG. 1;

FIG. 4 is a configuration diagram of a phase detection circuit according to the prior art.

FIG. 5 is an explanatory diagram of the operation of the phase detection circuit of FIG. 4;

FIG. 6 is a waveform diagram when phase θ2 in FIG. 4 is ahead of phase θ1.

7 is an explanatory diagram of the relationship between the phase difference between phases θ1 and θ2 in FIG. 4 and the output of the low-pass filter 4A; FIG.

[Explanation of symbols]

1A reference signal 1B Signal under measurement 2 Delay line 3A phase detector 3B Phase detector 4A Low-pass filter 4B Low-pass filter 5A Adder circuit 5B Adder circuit 6A resistance 6B Resistance 7 Comparator 8 Analog switch 9 Inverting amplifier 10 Output terminal

Claims (1)

[Claims] [Claim 1] The reference signal (1A) is connected to the first input terminal (
31), and the signal under test (1B) is connected to the second input terminal (32);
A delay line (
2) and the output of the delay line (2) is connected to the third input terminal (3
6), the signal under test (1B) is connected to the fourth input terminal (37), and the output of the first phase detector (3A) is input. a first low-pass filter (4A) that inputs the output of the second phase detector (3B); A first addition circuit (5A) that receives the input, a second addition circuit (5B) that receives the output of the second low-pass filter (4B), and a second addition circuit (5A) that receives the output of the second low-pass filter (4B).
A comparator (7) connected to the output of the second adder circuit (5B), an analog switch (8) connected to the output of the second adder circuit (5B) and controlled by the output of the comparator (7), It is equipped with an inverting amplifier (9) that adds the output of the adder circuit (5A) and the output of the analog switch (8).
When the phase difference between A) and the signal under test (1B) is large, the analog switch (8) is turned off by the output of the comparator (7), and only the output of the first phase detector (3A) is connected to the output terminal (10). ), the reference signal (1A) and the signal under test (
When the phase difference of 1B) becomes small, the analog switch (8)
is turned on, and the sum signal of the outputs of the first phase detector (3A) and the second phase detector (3B) is output to the output terminal (10).
A phase detection circuit characterized in that an output is output from.