JPH04332139A - Manufacture of electronic structure component with junction surface for soldering other article - Google Patents

Manufacture of electronic structure component with junction surface for soldering other article

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Publication number
JPH04332139A
JPH04332139A JP13041291A JP13041291A JPH04332139A JP H04332139 A JPH04332139 A JP H04332139A JP 13041291 A JP13041291 A JP 13041291A JP 13041291 A JP13041291 A JP 13041291A JP H04332139 A JPH04332139 A JP H04332139A
Authority
JP
Japan
Prior art keywords
brazing
workpiece
plated
peripheral wall
soldering
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13041291A
Other languages
Japanese (ja)
Inventor
Takaharu Miyamoto
隆春 宮本
Fumio Miyagawa
文雄 宮川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP13041291A priority Critical patent/JPH04332139A/en
Publication of JPH04332139A publication Critical patent/JPH04332139A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To easily and effectively form an electronic structure component without labor by plating a primarily processed junction surface for soldering a material to be processed, and secondarily processing a soldering material except the junction surface to be soldered. CONSTITUTION:Junction surfaces 50, 70 for soldering other article of members A, B to be processed, to be scarcely moistened with a primarily processed soldering material, are so plated as to be easily moistened with the soldering material. Then, the members A, B to be processed, for forming a surface part in which a soldering material except the junction surfaces 50, 70 of the plated members A, B, are secondarily processed, the surface parts of the plated members A, B for forming a surface part undesirably adhered with the soldering material are removed, and an electronic structure component is formed. Thus, the component in which the surfaces 50, 70 for soldering other component are plated to be easily wettable with the soldering material and the surface undeisrably adhered with the soldering material except it are not plated, can be easily and effectively formed.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、セラミック端子をろう
付けする半導体収納装置周壁等の他物品ろう付け用接合
面を有する電子構造部品の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an electronic structural component having a joint surface for brazing other articles such as a peripheral wall of a semiconductor housing device to which ceramic terminals are brazed.

【0002】0002

【従来の技術】従来より、半導体チップを収容するキャ
ビティ周壁を高熱伝導性の銅−タングステン合金などで
形成してなる、メタルパッケージと呼ばれる半導体収納
装置がある。
2. Description of the Related Art Conventionally, there has been a semiconductor storage device called a metal package in which a peripheral wall of a cavity for accommodating a semiconductor chip is formed of a highly thermally conductive copper-tungsten alloy.

【0003】この装置では、その周壁の一部に、接続線
路を持つセラミック端子をろう付けしている。
[0003] In this device, a ceramic terminal having a connection line is brazed to a part of the peripheral wall.

【0004】ところで、銅−タングステン合金などから
なる周壁はろう材に濡れにくいので、その周壁にセラミ
ック端子をろう付けする際には、周壁表面にニッケルめ
っき等のめっきを施して、周壁表面をろう材に濡れやす
い状態としている。
By the way, a peripheral wall made of copper-tungsten alloy or the like is difficult to wet with brazing material, so when brazing a ceramic terminal to the peripheral wall, the surface of the peripheral wall is coated with nickel plating, etc. The material is in a state where it is easy to get wet.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、上記め
っきを施した周壁にセラミック端子をろう付けした場合
には、セラミック端子ろう付け用のろう材が、セラミッ
ク端子をろう付けした周壁の接合面以外の、周壁内底面
等に流出して付着した。そして、それらの付着したろう
材が、例えば周壁内底面にボンディングする半導体チッ
プやチップ搭載用のステージ等に種々の悪影響を与えた
。具体的には、半導体チップやステージを周壁内底面に
ボンディングした際に、周壁内底面に付着したろう材で
、チップ底面やステージ底面と周壁内底面との間に隙間
が生じてしまった。そして、半導体チップが発する熱を
周壁を通して半導体収納装置外部に効率良く放散できな
くなったり、半導体チップやステージのボンディング材
にろう材中の銀が混入する等して、ボンディング材の接
合力が低下したりした。
[Problem to be Solved by the Invention] However, when a ceramic terminal is brazed to the above-mentioned plated peripheral wall, the brazing material for ceramic terminal brazing is applied to a surface other than the joint surface of the peripheral wall to which the ceramic terminal is brazed. , flowed out and adhered to the inner bottom surface of the surrounding wall, etc. The adhering brazing filler metal had various adverse effects on, for example, semiconductor chips bonded to the inner bottom surface of the peripheral wall, stages for mounting the chips, and the like. Specifically, when a semiconductor chip or stage was bonded to the inner bottom surface of the peripheral wall, a gap was created between the bottom surface of the chip or the stage and the inner bottom surface of the peripheral wall due to the brazing material adhering to the inner bottom surface of the peripheral wall. Then, the heat generated by the semiconductor chip cannot be efficiently dissipated to the outside of the semiconductor storage device through the surrounding wall, and the bonding strength of the bonding material decreases due to the silver in the brazing material getting mixed into the bonding material for the semiconductor chip or stage. It was.

【0006】これは、セラミック端子の接合面以外の周
壁内底面等にもニッケルめっき等のめっきが施されてい
て、それらの底面等がろう材に濡れやすい状態にあるの
で、セラミック端子ろう付け用ろう材が、それらの周壁
内底面等に流出するからである。
[0006] This is because the inner bottom surface of the peripheral wall other than the bonding surface of the ceramic terminal is also plated with nickel or other plating, and these bottom surfaces are easily wetted by the brazing material. This is because the brazing filler metal flows out onto the inner bottom surface of those surrounding walls.

【0007】なお、このような難点を解消するために、
上記周壁のセラミック端子ろう付け用接合面のみに部分
めっきを施す方法が考えられる。しかし、近時の半導体
収納装置は益々小型化、高密度化が進んでいて、その周
壁形状も小型精緻化しており、そのような小型精緻化し
た周壁のセラミック端子ろう付け用接合面のみに、部分
めっきを的確に施すことは、多大な困難を伴い、事実上
不可能に近い。
[0007] In order to solve these difficulties,
A method may be considered in which partial plating is applied only to the ceramic terminal brazing joint surface of the peripheral wall. However, recent semiconductor storage devices have become increasingly smaller and more dense, and the shape of their surrounding walls has also become smaller and more sophisticated. Accurately applying partial plating is extremely difficult and virtually impossible.

【0008】また、セラミック端子を周壁にろう付けし
た後、周壁内底面等を切削、研磨等して、それらの表面
に流出して付着したろう材を除去する方法も考えられる
。しかし、上記と同様に、小型精緻化した周壁内底面等
を、セラミック端子を傷付けずに切削、研磨等して、そ
れらの表面に流出して付着したろう材を除去することは
、多大な困難を伴い、事実上不可能に近い。
Another conceivable method is to braze the ceramic terminal to the peripheral wall and then cut, polish, etc. the inner bottom surface of the peripheral wall to remove the brazing material that has flowed and adhered to those surfaces. However, similar to the above, it is extremely difficult to remove the brazing filler metal that has flowed and adhered to the surfaces of small and refined peripheral walls by cutting, polishing, etc. without damaging the ceramic terminals. , making it virtually impossible.

【0009】これらと同様なことは、ろう材に濡れやす
いめっきを施した各種の他物品ろう付け用の接合面を有
するその他の小型精緻化した電子構造部品にも言える。
[0009] The same can be said of other small and sophisticated electronic structural parts having bonding surfaces for brazing various other products in which the brazing material is plated with easy wettability.

【0010】本発明は、このような課題に鑑みてなされ
たもので、他物品ろう付け用接合面にろう材に濡れやす
いめっきを施して、それ以外のろう材を付着させたくな
い表面部分にめっきを施していない電子構造部品を容易
かつ的確に形成可能な、他物品ろう付け用接合面を有す
る電子構造部品の製造方法(以下、製造方法という)を
提供しようとするものである。
[0010] The present invention has been made in view of the above problems, and includes plating that is easily wetted by the brazing material on the joint surface for brazing other products, and plating the surface area on which other brazing materials are not desired to adhere. It is an object of the present invention to provide a method for manufacturing an electronic structural component (hereinafter referred to as a manufacturing method) that can easily and accurately form an electronic structural component that is not plated and has a joint surface for brazing other articles.

【0011】[0011]

【課題を解決するための手段】上記目的を達成するため
に、本発明の製造方法は、電子構造部品形成用のろう材
に濡れにくい被加工部材に1次加工を施して、その被加
工部材に他物品ろう付け用接合面を形成する工程と、そ
の1次加工を施した被加工部材の少なくともろう付け用
接合面にめっきを施して、そのろう付け用接合面をろう
材に濡れやすい状態とする工程と、そのめっきを施した
被加工部材のろう付け用接合面以外の少なくともろう材
を付着させたくない表面部分を形成する被加工部材部分
に2次加工を施して、電子構造部品を形成する工程とを
含むことを特徴としている。
[Means for Solving the Problems] In order to achieve the above object, the manufacturing method of the present invention performs primary processing on a workpiece that is difficult to wet with a brazing material for forming electronic structural parts, and A process of forming a joint surface for brazing other articles, and plating at least the joint surface for brazing of the workpiece that has undergone the primary processing, and a state where the joint surface for brazing is easily wetted by the brazing material. Electronic structural components are manufactured by performing secondary processing on the part of the plated workpiece that forms at least the surface area on which the brazing material is not to be attached, other than the joint surface for brazing. The method is characterized in that it includes a step of forming.

【0012】0012

【作用】上記工程からなる製造方法においては、1次加
工を施した被加工部材の少なくともろう付け用接合面に
めっきを施した際に、ろう付け用接合面以外の被加工部
材表面にめっきが施された状態となっても、その後に、
そのめっきを施した被加工部材のろう付け用接合面以外
のろう材を付着させたくない表面部分を形成する被加工
部材部分に2次加工を施した際に、そのろう材を付着さ
せたくない表面部分を形成するめっきが施された被加工
部材表面部分を取り除くことができる。そして、他物品
ろう付け用接合面にめっきを施して、それ以外のろう材
を付着させたくない表面部分にめっきを施していない電
子構造部品を容易かつ的確に形成できる。
[Operation] In the manufacturing method consisting of the above steps, when plating is applied to at least the joint surface for brazing of the workpiece that has undergone the primary processing, the plating is not applied to the surface of the workpiece other than the joint surface for brazing. Even if it is applied, after that,
When secondary processing is performed on the part of the workpiece that forms a surface area other than the joint surface for brazing of the plated workpiece, where you do not want the solder metal to adhere, you do not want the solder metal to adhere to it. The plated surface portion of the workpiece forming the surface portion can be removed. Then, by applying plating to the joint surface for brazing other articles, it is possible to easily and accurately form an electronic structural component in which the other surface parts to which the brazing material is not desired to be plated are not applied.

【0013】[0013]

【実施例】次に、本発明の実施例を図面に従い説明する
。図1は本発明の製造方法により形成可能な電子構造部
品を用いた半導体収納装置を示し、詳しくはその斜視図
を示している。以下、この図中の半導体収納装置を説明
する。
Embodiments Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a semiconductor storage device using electronic structural components that can be formed by the manufacturing method of the present invention, and specifically shows a perspective view thereof. The semiconductor storage device shown in this figure will be explained below.

【0014】図において、10は、ろう材に濡れにくい
高熱伝導性の、銅−タングステン合金、近時開発された
第1、第2、第3モリブデン基合金の何れかで形成した
、半導体チップ収容用のキャビティ60周囲を囲む周壁
である。
In the figure, reference numeral 10 denotes a semiconductor chip housing made of a copper-tungsten alloy, a recently developed first, second, or third molybdenum-based alloy, which has high thermal conductivity and is difficult to get wet with the brazing material. This is a peripheral wall surrounding the cavity 60 for use.

【0015】ここで、第1モリブデン基合金とは、ニッ
ケル2〜12重量%、銅1.5〜8重量%を含み、残部
がモリブデンおよび不可避的不純物の組成のモリブデン
基合金を言い、その詳細は特願平2−232792号明
細書に記載されている。
[0015] Here, the first molybdenum-based alloy refers to a molybdenum-based alloy containing 2 to 12% by weight of nickel, 1.5 to 8% by weight of copper, and the balance being molybdenum and unavoidable impurities. is described in Japanese Patent Application No. 2-232792.

【0016】第2モリブデン基合金とは、ニッケル2〜
12重量%、鉄1.5〜8重量%を含み、残部がモリブ
デンおよび不可避的不純物の組成のモリブデン基合金を
言い、その詳細は特願平2−232791号明細書に記
載されている。
[0016] The second molybdenum-based alloy is nickel 2-
This refers to a molybdenum-based alloy having a composition of 12% by weight, 1.5 to 8% by weight of iron, and the balance being molybdenum and unavoidable impurities, the details of which are described in Japanese Patent Application No. 2-232791.

【0017】第3モリブデン基合金とは、ニッケル2〜
12重量%、鉄1.5〜8重量%、タングステン2〜1
2重量%を含み、残部がモリブデンおよび不可避的不純
物の組成のモリブデン基合金を言い、その詳細は特願平
2−232791号明細書に記載されている。
[0017] The third molybdenum-based alloy is nickel 2-
12% by weight, iron 1.5-8% by weight, tungsten 2-1
2% by weight, with the balance being molybdenum and unavoidable impurities, the details of which are described in Japanese Patent Application No. 2-232791.

【0018】周壁10は、上端が広く開口した有底の方
形箱体状をしていて、その左右の側壁12a,12bの
内外に、階段面14a,14bをそれぞれ備えている。
The peripheral wall 10 has a rectangular box shape with a bottom and a wide opening at the upper end, and has stepped surfaces 14a and 14b on the inside and outside of the left and right side walls 12a and 12b, respectively.

【0019】階段面14a,14bを備えた左右の側壁
12a,12b中央部には、凹部16a,16bを設け
ていて、それらの凹部16a,16bに、接続線路32
を備えたセラミック端子30をそれぞれろう付けしてい
る。
Recesses 16a, 16b are provided in the center portions of the left and right side walls 12a, 12b provided with step surfaces 14a, 14b, and connecting lines 32 are provided in these recesses 16a, 16b.
Ceramic terminals 30 each having a diameter are brazed to each other.

【0020】セラミック端子30の接続線路32外端に
は、金属製のリード40を接続している。
A metal lead 40 is connected to the outer end of the connection line 32 of the ceramic terminal 30.

【0021】セラミック端子30上端面を含む周壁10
上端面には、シールリング20をろう付けしている。
Peripheral wall 10 including the upper end surface of ceramic terminal 30
A seal ring 20 is brazed to the upper end surface.

【0022】図1に示した半導体収納装置は、以上のよ
うに構成していて、この装置では、その周壁10を、本
発明の製造方法を用いて形成可能である。
The semiconductor storage device shown in FIG. 1 is constructed as described above, and in this device, the peripheral wall 10 can be formed using the manufacturing method of the present invention.

【0023】以下、この半導体収納装置の周壁10を本
発明の製造方法に従い形成した場合の好適な実施例を説
明する。
A preferred embodiment in which the peripheral wall 10 of this semiconductor storage device is formed according to the manufacturing method of the present invention will be described below.

【0024】ろう材に濡れにくい、銅−タングステン合
金、第1、第2、第3モリブデン基合金の何れかからな
る周壁10形成用の長方形ブロック状をした被加工部材
Aを用意している。そして、図2に示したように、その
被加工部材Aに1次加工を施して、その被加工部材Aに
セラミック端子ろう付け用接合面50とシールリングろ
う付け用接合面70をそれぞれ形成している。詳しくは
、図2に示したように、エンドミル等を用いて、被加工
部材Aの左右端部中央表面に、盲穴状をした縦長の切欠
き穴52をそれぞれ設けて、それらの切欠き穴52内周
面の一部に、セラミック端子ろう付け用接合面50を形
成している。それと共に、被加工部材A上端面をラッピ
ング等して平滑化し、被加工部材A上端面の一部にシー
ルリングろう付け用接合面70を形成している。
A workpiece A in the shape of a rectangular block for forming the peripheral wall 10 is prepared, which is made of a copper-tungsten alloy or a first, second, or third molybdenum-based alloy that is difficult to wet with the brazing material. Then, as shown in FIG. 2, primary processing is performed on the workpiece A to form a ceramic terminal brazing joint surface 50 and a seal ring brazing joint surface 70 on the workpiece A, respectively. ing. Specifically, as shown in FIG. 2, blind hole-shaped vertically elongated notches 52 are respectively provided in the center surface of the left and right ends of the workpiece A using an end mill or the like, and these notches are A ceramic terminal brazing joint surface 50 is formed on a part of the inner circumferential surface of the ceramic terminal 52 . At the same time, the upper end surface of the workpiece A is smoothed by lapping or the like, and a seal ring brazing joint surface 70 is formed on a part of the upper end surface of the workpiece A.

【0025】または、ろう材に濡れにくい、銅−タング
ステン合金、第1、第2、第3モリブデン基合金の何れ
かからなる周壁10形成用の長帯形ブロック状をした被
加工部材Bを用意している。そして、図3に示したよう
に、その被加工部材Bに1次加工を施して、その被加工
部材Bにセラミック端子ろう付け用接合面50とシール
リングろう付け用接合面70をそれぞれ形成している。 詳しくは、図3に示したように、エンドミル等を用いて
、被加工部材Bの表面中央の縦方向に、盲穴状をした縦
長の切欠き穴52や縦長穴54をそれぞれ所定間隔あけ
て複数個並べて設けて、それらの切欠き穴52や縦長穴
54内周面の一部にセラミック端子ろう付け用接合面5
0をそれぞれ形成している。それと共に、被加工部材B
上端面をラッピング等して平滑化し、被加工部材B上端
面の一部にシールリングろう付け用接合面70を形成し
ている。
Alternatively, a workpiece B in the form of a long strip block for forming the peripheral wall 10 is prepared, which is made of a copper-tungsten alloy or a first, second, or third molybdenum-based alloy that is difficult to wet with the brazing material. are doing. Then, as shown in FIG. 3, primary processing is performed on the workpiece B to form a ceramic terminal brazing joint surface 50 and a seal ring brazing joint surface 70 on the workpiece B, respectively. ing. Specifically, as shown in FIG. 3, blind cutout holes 52 and vertical holes 54 are formed at predetermined intervals in the longitudinal direction at the center of the surface of the workpiece B using an end mill or the like. A ceramic terminal brazing joint surface 5 is provided in a part of the inner peripheral surface of the notch hole 52 or the vertically long hole 54.
0 respectively. At the same time, workpiece B
The upper end surface is smoothed by lapping or the like, and a seal ring brazing joint surface 70 is formed on a part of the upper end surface of the workpiece B.

【0026】次に、それらの1次加工を施した被加工部
材AやBのセラミック端子ろう付け用接合面50とシー
ルリングろう付け用接合面70を含む被加工部材AやB
周囲表面全体に、ニッケルめっき等のめっき(図示せず
)を施して、それらのろう付け用接合面50を含む被加
工部材AやB周囲表面全体を、銀ろう等のろう材に濡れ
やすい状態としている。
Next, the workpieces A and B, which have been subjected to the primary processing, include the ceramic terminal brazing joint surface 50 and the seal ring brazing joint surface 70.
Plating (not shown) such as nickel plating is applied to the entire surrounding surface, and the entire surrounding surface of workpieces A and B, including the joint surface 50 for brazing, is easily wetted by a brazing material such as silver solder. It is said that

【0027】または、セラミック端子ろう付け用接合面
50とシールリングろう付け用接合面70、あるいはそ
れに加えてそれらの周辺の被加工部材AやB上端面とそ
の側面の一部等を除く、被加工部材AやB表面をめっき
付着防止用の樹脂材等からなるマスキング部材(図示せ
ず)で覆った状態で、被加工部材AやB表面にめっき(
図示せず)を施して、それらのろう付け用接合面50,
70、あるいはそれに加えてそれらの周辺の被加工部材
AやB上端面とその側面の一部等に部分めっき(図示せ
ず)を施し、それらのろう付け用接合面50,70、あ
るいはそれに加えてそれらの周辺の被加工部材AやB上
端面とその側面の一部等をろう材に濡れやすい状態とし
ている。そして、被加工部材AやBのセラミック端子ろ
う付け用接合面50とシールリングろう付け用接合面7
0以外の被加工部材A周囲表面に無駄なめっきを施すの
を防いでいる。
Alternatively, the ceramic terminal brazing joint surface 50 and the seal ring brazing joint surface 70, or in addition to these, the workpiece A or B, excluding the upper end surface and a part of the side surface thereof, may be used. Plating (
(not shown) and their brazing joint surfaces 50,
70, or in addition, partial plating (not shown) is applied to the upper end surfaces and side surfaces of workpieces A and B around them, and the joint surfaces 50, 70 for brazing, or in addition The upper end surfaces and side surfaces of workpieces A and B in the vicinity thereof are in a state where they are easily wetted by the brazing material. Then, the ceramic terminal brazing joint surface 50 and the seal ring brazing joint surface 7 of the workpieces A and B
This prevents wasteful plating on the surrounding surface of workpiece A other than 0.

【0028】次に、エンドミル等を用いて、上記メッキ
を施した被加工部材AまたはBのろう材を付着させたく
ない表面部分を形成する被加工部材AやB部分に、2次
加工を施している。それと共に、その他の上記めっきを
施した被加工部材AまたはBのセラミック端子ろう付け
用接合面50とシールリングろう付け用接合面70以外
の所定の被加工部材AやB部分にも、必要とする2次加
工を施している。
[0028] Next, using an end mill or the like, secondary processing is performed on the plated workpiece A or B on the part of the workpiece A or B that forms the surface portion to which the brazing metal is not desired to adhere. ing. At the same time, other predetermined parts of the workpiece A or B other than the ceramic terminal brazing joint surface 50 and the seal ring brazing joint surface 70 of the workpiece A or B that have been plated are Secondary processing is performed to

【0029】具体的には、図2に示した被加工部材Aに
あっては、その被加工部材A上端面中央に、上端が広く
開口した有底の方形状をしたキャビティ60を設けてい
る。それと共に、被加工部材Aの左右端部の内外に、階
段面14a,14bをそれぞれ設けている。
Specifically, in the workpiece A shown in FIG. 2, a rectangular cavity 60 with a bottom and a wide upper end is provided in the center of the upper end surface of the workpiece A. . At the same time, step surfaces 14a and 14b are provided inside and outside the left and right ends of the workpiece A, respectively.

【0030】図3に示した被加工部材Bにあっては、図
中に一点鎖線で示したように、被加工部材Bを、縦長穴
54中途部を横断して、横方向に複数に切断している。 そして、それらの複数に切断した被加工部材B上端面中
央に、上端が広く開口した有底の方形状をしたキャビテ
ィ60をそれぞれ設けている。それと共に、それらの切
断した被加工部材Bの左右端部の内外に、階段面14a
,14bをそれぞれ設けている。
In the workpiece B shown in FIG. 3, the workpiece B is cut horizontally into a plurality of pieces by crossing the midway part of the vertically elongated hole 54, as indicated by the dashed line in the figure. are doing. A rectangular cavity 60 with a bottom and a wide upper end is provided at the center of the upper end surface of the workpiece B cut into a plurality of pieces. At the same time, the step surfaces 14a are placed inside and outside the left and right ends of the cut workpiece B.
, 14b are provided respectively.

【0031】そして、図4に示したような、上端が広く
開口した有底の方形箱体状をした周壁10であって、そ
の左右側壁12a,12bの内外に階段面14a,14
bをそれぞれ設けると共に、その左右側壁12a,12
b中央に切欠き穴52や縦長穴54の一部からなる凹部
16a,16bをそれぞれ備えた、銅−タングステン合
金、第1、第2、第3モリブデン基合金の何れかからな
る周壁10を形成している。それと共に、凹部16a,
16b内側のセラミック端子ろう付け用接合面50と周
壁10上端面のシールリングろう付け用接合面70にろ
う材に濡れやすいめっき(図の破線でハッチングを施し
た部分)を施して、それ以外のろう材を付着させたくな
い周壁10内底面等にめっきを施していない周壁10を
形成している。
As shown in FIG. 4, the peripheral wall 10 is shaped like a rectangular box with a bottom and a wide opening at the upper end.
b, and the left and right side walls 12a, 12
b Forming a peripheral wall 10 made of any one of a copper-tungsten alloy, a first, a second, and a third molybdenum-based alloy, with recesses 16a and 16b each consisting of a notch hole 52 and a part of a longitudinal hole 54 in the center. are doing. At the same time, the recess 16a,
The ceramic terminal brazing joint surface 50 on the inner side of the ceramic terminal 16b and the seal ring brazing joint surface 70 on the upper end surface of the peripheral wall 10 are plated to be easily wetted by the brazing metal (the part hatched with broken lines in the figure), and the other An unplated peripheral wall 10 is formed on the inner bottom surface of the peripheral wall 10 to which it is not desired that the brazing material adheres.

【0032】図2ないし図4に示した周壁10の製造方
法は、以上の工程からなる。
The method for manufacturing the peripheral wall 10 shown in FIGS. 2 to 4 consists of the steps described above.

【0033】なお、この周壁10の製造方法においては
、1次加工の際に、被加工部材Aの左右端部に階段面1
4bを設けたり、被加工部材Bの左右端部やその中途部
表面に、切欠き穴52や縦長穴54を横断して、階段面
14b形成用の溝(図示せず)を設けたりして、2次加
工の際に、それらの階段面14bを設ける手数を省いて
も良い。ただし、そうした場合は、それらの階段面14
b表面をマスキング部材で覆わない限り、それらの階段
面14b表面にめっきが施された状態の周壁10が形成
される。
In addition, in this method of manufacturing the peripheral wall 10, step surfaces 1 are formed on the left and right ends of the workpiece A during the primary processing.
4b, or a groove (not shown) for forming the step surface 14b is provided on the left and right end portions of the workpiece B or on the surface of the midway portion thereof, crossing the notch hole 52 and the vertically elongated hole 54. , the trouble of providing those step surfaces 14b may be omitted during secondary processing. However, in such a case, those stair surfaces 14
Unless the surfaces b are covered with a masking member, the peripheral wall 10 is formed with plating applied to the surfaces of the step surfaces 14b.

【0034】図5は本発明の製造方法により形成可能な
電子構造部品を用いた他の半導体収納装置を示し、詳し
くはその斜視図を示している。以下、この図中の半導体
収納装置を説明する。
FIG. 5 shows another semiconductor storage device using electronic structural components that can be formed by the manufacturing method of the present invention, and specifically shows a perspective view thereof. The semiconductor storage device shown in this figure will be explained below.

【0035】図において、100は、ろう材に濡れやす
い高熱伝導性の、銅−タングステン合金、前述の第1、
第2、第3モリブデン基合金の何れかで形成した底板で
ある。
In the figure, reference numeral 100 indicates a copper-tungsten alloy having high thermal conductivity that is easily wetted by the brazing material;
The bottom plate is made of either a second or third molybdenum-based alloy.

【0036】底板100は、平板状をしていて、その上
端面中央に、半導体チップ搭載用の薄板状のステージ1
20を一体に突設している。
The bottom plate 100 has a flat plate shape, and a thin plate-shaped stage 1 for mounting a semiconductor chip is provided at the center of the upper end surface.
20 are integrally protruded.

【0037】底板100上端面周囲には、ほぼ方形枠体
状をしたセラミック枠体200を、そのセラミック枠体
200内側にステージ120を嵌入した状態で、搭載し
ている。そして、セラミック枠体200下端面に備えた
ろう材に濡れやすいめっき(図示せず)を施したメタラ
イズ層220を介して、セラミック枠体200下端面を
底板100上端面にろう付けしている。そして、底板1
00で、セラミック枠体200底面を気密に封じていて
、セラミック枠体200内側に半導体チップ収容用の有
底のキャビティ600を形成している。
A ceramic frame 200 having a substantially rectangular frame shape is mounted around the upper end surface of the bottom plate 100, with a stage 120 fitted inside the ceramic frame 200. Then, the lower end surface of the ceramic frame 200 is brazed to the upper end surface of the bottom plate 100 via a metallized layer 220 which is plated (not shown) and is easily wetted with a brazing material provided on the lower end surface of the ceramic frame 200. And the bottom plate 1
00, the bottom surface of the ceramic frame 200 is hermetically sealed, and a bottomed cavity 600 for accommodating a semiconductor chip is formed inside the ceramic frame 200.

【0038】セラミック枠体200は、その断面が逆T
字状をしていて、その内外周囲に階段面230a,23
0bをそれぞれ備えている。
The ceramic frame 200 has an inverted T cross section.
It has a character shape, and there are staircase surfaces 230a, 23 around the inside and outside.
0b.

【0039】セラミック枠体200内外の階段面230
a,230bには、メタライズからなる細帯状の接続線
路300を、セラミック枠体200内部を通して、複数
本連続して並べて備えている。
Step surfaces 230 inside and outside the ceramic frame 200
A, 230b are provided with a plurality of thin strip-shaped connection lines 300 made of metallized and arranged in succession through the inside of the ceramic frame 200.

【0040】セラミック枠体200外側の階段面230
bに備えた接続線路300外端には、細帯状をした金属
製のリード400をろう付けしている。
Stair surface 230 on the outside of ceramic frame 200
A thin strip-shaped metal lead 400 is brazed to the outer end of the connection line 300 provided in FIG.

【0041】セラミック枠体200上端面には、キャッ
プろう付け用のろう材に濡れやすいめっき(図示せず)
を施したメタライズ層240を備えている。
[0041] The upper end surface of the ceramic frame 200 is plated (not shown) that is easily wetted by the brazing material for cap brazing.
A metallized layer 240 is provided.

【0042】図5に示した半導体収納装置は、以上のよ
うに構成していて、この装置では、そのステージ120
を一体に突設した底板100を、本発明の製造方法を用
いて形成可能である。
The semiconductor storage device shown in FIG. 5 is constructed as described above, and in this device, the stage 120
A bottom plate 100 having an integrally protruding structure can be formed using the manufacturing method of the present invention.

【0043】以下、この半導体収納装置のステージ12
0を一体に突設した底板100を本発明の製造方法に従
い形成した場合の好適な実施例を説明する。
The stage 12 of this semiconductor storage device will be described below.
A preferred embodiment will be described in which a bottom plate 100 having an integrally protruding portion 0 is formed according to the manufacturing method of the present invention.

【0044】ろう材に濡れにくい、銅−タングステン合
金、第1、第2、第3モリブデン基合金の何れかからな
る底板形成用の方形ブロック状をした被加工部材Cを用
意している。そして、図6に示したように、その被加工
部材Cに1次加工を施して、その被加工部材C上端面周
囲に、セラミック枠体ろう付け用接合面500を形成し
ている。詳しくは、図6に示したように、エンドミル等
を用いて、被加工部材C上端面周囲に、階段面140を
連続して設けている。そして、被加工部材C上端面中央
に、方形平板状のステージ形成用部材122を残すよう
にしている。
A workpiece C in the shape of a rectangular block for forming a bottom plate is prepared, which is made of a copper-tungsten alloy or a first, second, or third molybdenum-based alloy and is difficult to wet with the brazing material. Then, as shown in FIG. 6, primary processing is performed on the workpiece C to form a ceramic frame brazing joint surface 500 around the upper end surface of the workpiece C. Specifically, as shown in FIG. 6, a step surface 140 is continuously provided around the upper end surface of the workpiece C using an end mill or the like. A rectangular plate-shaped stage forming member 122 is left at the center of the upper end surface of the workpiece C.

【0045】次に、その1次加工を施した被加工部材C
の階段面140を含む被加工部材C周囲表面全体にニッ
ケルめっき等のめっき(図示せず)を施して、その階段
面140を含む被加工部材C周囲表面全体を、ろう材に
濡れやすい状態としている。
Next, the workpiece C that has been subjected to the primary processing
Plating (not shown) such as nickel plating is applied to the entire surrounding surface of the workpiece C including the step surface 140, so that the entire surrounding surface of the workpiece C including the step surface 140 is easily wetted by the brazing material. There is.

【0046】または、被加工部材Cの階段面140、あ
るいはそれに加えてその周辺の被加工部材C上端面中央
のステージ形成用部材122周囲側面等を除く、被加工
部材C周囲表面をめっき付着防止用のマスキング部材で
覆った状態で、被加工部材C周囲表面にめっきを施して
、階段面140、あるいはそれに加えてその周辺のステ
ージ形成用部材122周囲側面等にめっき(図示せず)
を施し、階段面140、あるいはそれに加えてその周辺
のステージ形成用部材122周囲側面等をろう材に濡れ
やすい状態としている。そして、被加工部材Cのそれ以
外の被加工部材C周囲表面に無駄なめっきを施すのを防
いでいる。
Alternatively, the surrounding surface of the workpiece C, excluding the step surface 140 of the workpiece C, or in addition, the surrounding surface of the stage forming member 122 at the center of the upper end surface of the workpiece C, is coated to prevent adhesion of plating. While covered with a masking member, the surface around the workpiece C is plated, and the step surface 140, or in addition, the side surface around the stage forming member 122 in the vicinity thereof is plated (not shown).
The step surface 140 or, in addition, the side surfaces around the stage forming member 122 in the periphery thereof are made to be easily wetted by the brazing material. This prevents wasteful plating on the surrounding surface of the workpiece C other than that of the workpiece C.

【0047】次に、エンドミル等を用いて、上記めっき
を施した被加工部材Cのろう材を付着させたくない表面
部分を形成するステージ形成用部材122上端面に、切
削等の2次加工を施している。それと共に、その他の上
記めっきを施した被加工部材Cの階段面140以外の被
加工部材C周囲側面やその底面等に、ラッピング等の2
次加工を施している。
Next, using an end mill or the like, perform secondary processing such as cutting on the upper end surface of the stage forming member 122 that forms the surface portion of the plated workpiece C to which the brazing metal is not desired to adhere. are giving. At the same time, the surrounding side surfaces and bottom surfaces of the workpiece C other than the step surface 140 of the workpiece C to which the above-mentioned plating has been applied are coated with wrapping, etc.
The next processing is being carried out.

【0048】そして、図7に示したような、底板100
上端面周囲に連続する階段面140を設けると共に、底
板100上端面中央に薄板状のステージ120を一体に
突設した、銅−タングステン合金、第1、第2、第3モ
リブデン基合金の何れかからなる底板100を形成して
いる。それと共に、底板100のセラミック枠体ろう付
け用接合面500を構成する階段面140にろう材に濡
れやすいめっき(図の破線でハッチングを施した部分)
を施して、それ以外のろう材を付着させたくないステー
ジ120上端面やその他の底板100周囲側面等にめっ
きを施していない底板100を形成している。
[0048] Then, a bottom plate 100 as shown in FIG.
A continuous step surface 140 is provided around the upper end surface, and a thin plate-like stage 120 is integrally protruded from the center of the upper end surface of the bottom plate 100, and is made of copper-tungsten alloy, first, second, or third molybdenum-based alloy. A bottom plate 100 is formed. At the same time, the step surface 140 that constitutes the ceramic frame brazing joint surface 500 of the bottom plate 100 is plated to be easily wetted by the brazing material (the part hatched with broken lines in the figure).
The bottom plate 100 is formed by applying no plating to the upper end surface of the stage 120 and other side surfaces around the bottom plate 100 to which other brazing metals are not desired to be attached.

【0049】図6および図7に示した底板100の製造
方法は、以上の工程からなる。
The method for manufacturing the bottom plate 100 shown in FIGS. 6 and 7 consists of the steps described above.

【0050】[0050]

【発明の効果】以上説明したように、本発明の製造方法
によれば、セラミック端子、シールリング、セラミック
枠体等の他物品ろう付け用接合面にろう材に濡れやすい
めっきを施して、それ以外のろう材を付着させたくない
表面部分にめっきを施していない、半導体収納装置の周
壁、ステージを一体に突設した底板等の、ろう材に濡れ
にくい被加工部材からなる電子構造部品を、手数を掛け
ずに容易かつ的確に形成可能となる。
[Effects of the Invention] As explained above, according to the manufacturing method of the present invention, the joint surfaces for brazing other products such as ceramic terminals, seal rings, and ceramic frames are plated to be easily wetted by the brazing material. Electronic structural parts made of workpieces that are difficult to get wet with brazing material, such as peripheral walls of semiconductor storage equipment and bottom plates with integrally protruding stages, which have unplated surfaces where you do not want other brazing materials to adhere. It can be formed easily and accurately without much effort.

【0051】そして、それらのろう付け用接合面にセラ
ミック端子、シールリング、セラミック枠体等の他物品
をろう付けした際に、めっきを施していない被加工部材
の素地が露出している表面部分に漏れ出そうとするろう
材を、そのろう材に濡れにくい被加工部材の素地が露出
している表面部分で、ろう付け用接合面等へとはじき返
すことができる。そして、ろう材が、半導体チップやス
テージをボンディングする周壁内底面、シールリングを
ろう付けする周壁上端面、半導体チップをボンディング
する底板に一体に突設したステージ上端面等に漏れ出し
て付着して、種々の悪影響を与えるのを確実に防止でき
る。
[0051] When other articles such as ceramic terminals, seal rings, and ceramic frames are brazed to these joint surfaces for brazing, the surface portion where the base material of the workpiece that is not plated is exposed. The brazing material that is about to leak out can be repelled onto the brazing joint surface, etc. by the exposed surface of the workpiece material that is difficult to wet with the brazing material. Then, the brazing material leaks and adheres to the inner bottom surface of the peripheral wall to which the semiconductor chip and stage are bonded, the upper end surface of the peripheral wall to which the seal ring is brazed, the upper end surface of the stage integrally protruding from the bottom plate to which the semiconductor chip is bonded, etc. , it is possible to reliably prevent various adverse effects.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】本発明の製造方法により形成可能な電子構造部
品を用いた半導体収納装置の斜視図である。
FIG. 1 is a perspective view of a semiconductor storage device using electronic structural components that can be formed by the manufacturing method of the present invention.

【図2】図1の半導体収納装置の周壁を本発明の製造方
法により形成した場合の製造工程説明図である。
FIG. 2 is a manufacturing process explanatory diagram when the peripheral wall of the semiconductor storage device shown in FIG. 1 is formed by the manufacturing method of the present invention.

【図3】図1の半導体収納装置の周壁を本発明の製造方
法により形成した場合の製造工程説明図である。
FIG. 3 is a manufacturing process explanatory diagram when the peripheral wall of the semiconductor storage device shown in FIG. 1 is formed by the manufacturing method of the present invention.

【図4】図1の半導体収納装置の周壁を本発明の製造方
法により形成した場合の製造工程説明図である。
FIG. 4 is a manufacturing process explanatory diagram when the peripheral wall of the semiconductor storage device shown in FIG. 1 is formed by the manufacturing method of the present invention.

【図5】本発明の製造方法により形成可能な電子構造部
品を用いた半導体収納装置の斜視図である。
FIG. 5 is a perspective view of a semiconductor storage device using electronic structural components that can be formed by the manufacturing method of the present invention.

【図6】図5の半導体収納装置の周壁を本発明の製造方
法により形成した場合の製造工程説明図である。
FIG. 6 is a manufacturing process explanatory diagram when the peripheral wall of the semiconductor storage device shown in FIG. 5 is formed by the manufacturing method of the present invention.

【図7】図5の半導体収納装置の周壁を本発明の製造方
法により形成した場合の製造工程説明図である。
FIG. 7 is a manufacturing process explanatory diagram when the peripheral wall of the semiconductor storage device shown in FIG. 5 is formed by the manufacturing method of the present invention.

【符号の説明】[Explanation of symbols]

10  周壁 20  シールリング 30  セラミック端子 40  リード 50  セラミック端子ろう付け用接合面52  切欠
き穴 54  縦長穴 60  キャビティ 70  シールリングろう付け用接合面100  底板 120  ステージ 200  セラミック枠体 300  接続線路 400  リード 500  セラミック枠体ろう付け用接合面600  
キャビティ A  被加工部材 B  被加工部材 C  被加工部材
10 Peripheral wall 20 Seal ring 30 Ceramic terminal 40 Lead 50 Ceramic terminal brazing joint surface 52 Notch hole 54 Vertical hole 60 Cavity 70 Seal ring brazing joint surface 100 Bottom plate 120 Stage 200 Ceramic frame 300 Connection line 400 Lead 500 Ceramic Joint surface 600 for frame brazing
Cavity A Workpiece member B Workpiece member C Workpiece member

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  電子構造部品形成用のろう材に濡れに
くい被加工部材に1次加工を施して、その被加工部材に
他物品ろう付け用接合面を形成する工程と、その1次加
工を施した被加工部材の少なくともろう付け用接合面に
めっきを施して、そのろう付け用接合面をろう材に濡れ
やすい状態とする工程と、そのめっきを施した被加工部
材のろう付け用接合面以外の少なくともろう材を付着さ
せたくない表面部分を形成する被加工部材部分に2次加
工を施して、電子構造部品を形成する工程とを含むこと
を特徴とする他物品ろう付け用接合面を有する電子構造
部品の製造方法。
Claim 1: A step of performing primary processing on a workpiece that is difficult to wet with a brazing material for forming electronic structural parts, and forming a joint surface for brazing other products on the workpiece, and the primary processing. A step of plating at least the joint surface for brazing of the plated workpiece to make the joint surface for brazing easily wetted by the brazing metal, and a step of applying plating to the joint surface for brazing of the workpiece to which the plating has been applied. A joint surface for brazing other products, characterized by comprising the step of forming an electronic structural component by performing secondary processing on a part of the workpiece that forms at least a surface part to which no brazing material is to be attached. A method of manufacturing an electronic structural component comprising:
JP13041291A 1991-05-02 1991-05-02 Manufacture of electronic structure component with junction surface for soldering other article Pending JPH04332139A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13041291A JPH04332139A (en) 1991-05-02 1991-05-02 Manufacture of electronic structure component with junction surface for soldering other article

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13041291A JPH04332139A (en) 1991-05-02 1991-05-02 Manufacture of electronic structure component with junction surface for soldering other article

Publications (1)

Publication Number Publication Date
JPH04332139A true JPH04332139A (en) 1992-11-19

Family

ID=15033648

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13041291A Pending JPH04332139A (en) 1991-05-02 1991-05-02 Manufacture of electronic structure component with junction surface for soldering other article

Country Status (1)

Country Link
JP (1) JPH04332139A (en)

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