JPH04332113A - Semiconductor device and alignment method - Google Patents

Abstract

PURPOSE:To provide a semiconductor device which easily prevents dust from being generated due to release of an etching residue which remains on a side wall of a positioning mark without any reduction in detection sensitivity for the semiconductor device which is provided with the alignment mark for alignment at the time of patterning. CONSTITUTION:An alignment mark consisting of opposing region layers 17a and 17b which oppose each other and a band-shaped region layer 16a which is sandwiched by the opposing region layers 17a and 17b and generates a reflection light with a light intensity which is larger than that from the above opposing regions 17a and 17b for irradiation of a position detection light is provided on a surface layer of a semiconductor substrate 16.

Description

[Detailed description of the invention]

[0001] (Table of Contents) ・Industrial application field ・Conventional technology (Figures 7 to 10) ・Problem that the invention aims to solve ・Means to solve problems ・Effect (Figure 1) ・Example (Figures 2 to 6) ·Effect of the invention

0002

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and an alignment method, and more particularly to a semiconductor device having alignment marks for alignment during patterning and an alignment method.

0003

[Prior Art] Conventionally, alignment marks are formed in grooves using these insulating films and the like at the same time as patterning, as alignment marks for alignment when patterning insulating films and conductive films on semiconductor substrates. There is something.

[0004]Also, as a method for forming alignment marks, there are a method of transferring an alignment pattern on an exposure mask and a method of directly drawing an alignment pattern with an electron beam. There is a method using a mask formed on a transparent substrate with the same pattern or a transparent substrate on which only an alignment pattern is formed, and using infrared rays, a laser beam, or an electron beam as the position detection light.

[0005] FIGS. 7(a), (b), FIGS. 8(c), (d)
FIG. 2 is a cross-sectional view illustrating a method for forming alignment marks and an alignment method using a conventional exposure mask.

FIG. 7(a) is a cross-sectional view showing the state after forming the S/D region layer, in which reference numeral 1 indicates the element formation region, 2
4 is an alignment mark forming region, 4 is a SiO2 film selectively formed to separate element regions on the semiconductor substrate 3, 5a is a gate insulating film, and 5b is an alignment mark formed at the same time as the gate insulating film 5a. Insulating film constituting 9, 6
a is a gate electrode on the gate insulating film 5a, 6b is a conductive film forming the alignment mark 9 formed at the same time as the gate electrode 6a, 7a is an insulating film on the gate electrode 5a, and 7b is an alignment mark formed at the same time. an insulating film constituting 9;
8a and 8b are source/drain (S/D) region layers formed on the semiconductor substrate 3 on both sides of the gate electrode 6a.

First, an insulating film 10 is formed on the entire surface of the semiconductor substrate 3 in order to form an insulating film on the side walls of the gate electrode 6a (FIG. 7(b)).

Next, after forming the resist film 11, in order to transfer the mask pattern 12a on the exposure mask 12 to the resist film 11 in the area where the contact hole is to be formed, the mask pattern 12a is aligned at a corresponding position. Therefore, by moving the alignment pattern 12b on the exposure mask 12 onto the alignment mark 9 while irradiating infrared rays, and detecting the position of the infrared light reflected from the alignment mark 9 and the alignment pattern 12b, Align. After the alignment is completed, ultraviolet rays are irradiated to transfer the mask pattern 12a (FIG. 8(c)).

Next, after developing the resist film 11 to form a resist pattern 11a, the resist pattern 11a is
The insulating film 10 is patterned using as a mask. As a result, contact holes 13a and 13b are formed on the sidewall 10a made of the insulating film 10 on the sidewall of the gate electrode 6a and on the S/D region layers 8a and 8b (FIG. 8(d)).
.

Incidentally, etching residues (so-called heba residues) 10b of the insulating film remain on the sidewalls of the alignment marks 9 of the semiconductor device created in this way, and this remains during subsequent steps or during device manufacturing. It may peel off after completion of the process. Therefore, there is a problem that defects may occur in the conductive film, insulating film, etc. that are formed later.

[0011] Also, FIGS. 9(a), (b), and FIG. 10(c)
, (d) are cross-sectional views illustrating a method for forming alignment marks and an alignment method using a conventional direct writing method using an electron beam, in which countermeasures have been taken for the above-mentioned problems.

First, after the step shown in FIG. 7B, a resist film 11 is formed, and in order to directly draw a pattern on the resist film 11 in a region where a contact hole is to be formed, alignment is performed at a corresponding position. For this reason, the alignment mask 1 whose position is aligned with the pattern drawing device is placed on the alignment mark 9 while irradiating the He-Ne gas laser.
The alignment is performed by moving the alignment pattern 14a on the alignment mark 9 and detecting the position of the laser beam reflected from the alignment pattern 14b (FIG. 9(a)).

Next, after the alignment is completed, an electron beam is irradiated to directly draw on the resist film 11. At this time, the alignment mark 9 and its surrounding area are covered with an insulating film 10 in order to prevent the formation of a sticky residue 10b as shown in FIG. 8(d), so the alignment mark 9 and its surrounding area are also exposed to the electron beam. irradiate (FIG. 9(b)).

Next, after developing the resist film 11 to form resist patterns 11b and 11c, the insulating film 10 is selectively etched and removed using the resist patterns 11b and 11c as masks. As a result, a sidewall 10c made of the insulating film 10 and an S
Contact holes 13c, 1 are formed on /D region layers 8a, 8b.
3d is formed, and the alignment mark 9 and its surrounding area are covered with an insulating film 10d (FIG. 10(c)).
).

After that, resist patterns 11b and 11c are formed.
After removing the contact holes 13c and 13d, S/D electrodes 15a and 15b are formed to complete the semiconductor device (FIG. 10(d)).

[0016]

[Problem to be solved by the invention] By the way, FIG. 8(d)
The alignment mark 9 and its surrounding area are also irradiated with the electron beam in order to cover the alignment mark 9 and its surrounding area with an insulating film 10d in order to prevent the formation of a sticky residue 10b as shown in FIG. Regarding b)), there is a problem in that it takes a very long time to scan the electron beam, and the throughput is significantly reduced.

[0017]Also, the alignment mark 9 is formed using an insulating film 10d.
There is a problem in that the step is reduced and the detection sensitivity is reduced.

The present invention has been made in view of such conventional problems, and eliminates dust caused by peeling off etching residues remaining on the side walls of alignment marks, without requiring much effort and while preventing a decrease in detection sensitivity. The object of the present invention is to provide a semiconductor device that can prevent the occurrence of such problems.

[0019]

[Means for Solving the Problems] The above-mentioned problem firstly consists of two opposing region layers facing each other on the surface layer of a semiconductor substrate, and the opposing region layer being sandwiched between the opposing region layers and facing the irradiation of position detection light. This is achieved by a semiconductor device characterized in that it has an alignment mark consisting of a band-shaped region layer that produces reflected light with a greater light intensity than the light intensity of the reflected light from the region layer, and secondly, the opposing region layer is Achieved by the semiconductor device according to the first invention, characterized in that the semiconductor device is a region layer into which impurities are introduced by ion implantation, and the band-shaped region layer is a region layer into which impurities are not introduced by ion implantation, and thirdly, Achieved by the semiconductor device according to the first aspect of the present invention, wherein the opposing region layer is a region layer into which impurities are not introduced by ion implantation, and the band-shaped region layer is a region layer into which impurities are introduced by ion implantation. , fourthly, a transparent substrate on which a positional relationship is aligned with the pattern transfer means and on which an alignment pattern is formed, and a semiconductor substrate on which an alignment mark according to the first, second, or third aspect of the invention is formed; After overlapping, the alignment pattern and the alignment mark are aligned by irradiating position detection light and detecting the reflected light from the alignment pattern and the reflected light from the alignment mark. This is achieved by an alignment method characterized by performing.

[0020]

[Operation] FIGS. 1(a) and 1(b) show the experimental results of the inventor of the present application. That is, FIG. 1(a) shows the cross-sectional structure of an experimental sample, and the H beam used as position detection light when aligning a pattern on this sample using an exposure method or a direct writing method.
The reflected light detected when e-Ne laser light is irradiated is shown. Figure (b) shows a top view of the experimental sample.

The sample is a Si substrate (semiconductor substrate) 16
Selectively accelerate boron ions with an energy of 50 keV,
Ion implantation was performed at a dose of 4 x 1012 cm-2,
Boron ion introduced area layers (opposing area layers) 1 facing each other with a band-shaped non-introduced area layer (band-shaped area layer) 16a in between.
7a and 17b (Fig.
(a)).

When such a Si substrate 16 is irradiated with He-Ne laser light and the reflected light is detected by a reflection type detector, reflected light as shown in FIG. 1(a) is detected from the non-introduced region layer 16a. Almost no reflected light was detected from the introduction region layers 17a and 17b. At present, the reason for this is still unclear, but the introduction region layer 17 by impurity ion implantation
It is conceivable that reflected light at a predetermined detection position decreases due to a decrease in light reflectance at a and 17b or an increase in scattered light due to the occurrence of minute irregularities on the surface. In addition, in the experiment, the light intensity of the reflected light from the non-introduction area layer 16a was determined from the introduction area layer 1.
Although the intensity is greater than that of the reflected light from 7a and 17b, this relationship may be reversed depending on the type of impurity.

Therefore, as in the alignment method of the present invention, the positional relationship is aligned with the pattern transfer means, the transparent substrate on which the alignment pattern is formed, and the semiconductor on which the introduction area layer and the non-introduction area layer are formed. After overlapping the board,
By irradiating the position detection light, it is possible to selectively detect the reflected light from the non-introduced area layer using the difference in intensity between the reflected light from the introduced area layer and the non-introduced area layer. Therefore, by adjusting the positional relationship between the reflected light from the non-introduced area layer and the reflected light from the alignment pattern, and aligning the alignment pattern and the non-introduced area layer, the transferred pattern and the semiconductor It is possible to align with the transferred area on the substrate. Note that when the light intensity of the reflected light from the introduced region layer is greater than the light intensity of the reflected light from the non-introduced region layer, the reflected light from the introduced region layer is used.

In the semiconductor device of the present invention, the introduction region layer and the non-introduction region layer formed on the surface layer of the semiconductor substrate are used as alignment marks, so unlike the conventional case, they do not protrude from the surface of the semiconductor substrate. , it is possible to prevent etching residue from remaining on the side wall. Also,
Therefore, it is no longer necessary to cover the alignment mark with an insulating film to prevent peeling off of etching residues, as is the case in the past, and therefore it is possible to prevent a decrease in detection sensitivity. Furthermore,
Since the alignment mark can be formed by ion implantation, it can be formed at the same time as forming the conductivity type region layer of the element region, and it does not require much effort. This eliminates the generation of dust caused by etching residue without much effort.
It can be easily prevented.

[0025]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. Figure 2 (a), (b), Figure 3 (c), (
d), FIGS. 4(e) to 4(g), and FIGS. 5(h) and (i) are cross-sectional views illustrating an alignment method and a semiconductor device manufacturing method according to an embodiment of the present invention.

FIG. 2(a) is a cross-sectional view showing the state after the gate electrode is formed but before the S/D region layer is formed. In the figure, reference numeral 20 indicates an element formation region, and 21 normally indicates an element formation region. An alignment mark forming area, which is a common area with the cutting area (dicing line) for turning the wafer into chips, 23
selective oxidation (L
24 is a gate insulating film made of SiO2 film in the element region; 25 is a gate electrode made of polysilicon film on gate insulating film 24; 26 is on gate electrode 25; This is an insulating film made of a SiO2 film.

Further, 27 is an alignment mark forming area 2.
The alignment mark formed in 1 has the following configuration. That is, (1) S in the alignment mark forming area 13a
(2) an insulating film made of an SiO2 film formed on the i-substrate 22 at the same time as the gate insulating film 16a; (2) a polysilicon film having the same width as the insulating film and formed on the insulating film at the same time as the gate electrode 17a; (3) and an insulating film formed on the conductive film at the same time as the insulating film 26 and having the same width as the conductive film.

First, in this state, a film with a thickness of about 1
After forming a positive photoresist film with a thickness of about 2 μm and a length of about 2 μm in width and a length of Approximately 10μ
Two band-shaped resist patterns 28a and 28b of m are formed with an interval of about 2 μm and their longitudinal sides facing each other. As a result, the gate electrode 25 and the resist pattern 2
8a and 28b can be obtained (FIG. 2(b)).

Next, using the gate electrode 25, the resist patterns 28a and 28b, and the insulating film 23 made of a SiO2 film for separating the element regions as masks, an acceleration energy of 50
Boron ions are selectively implanted into the Si substrate 22 under the conditions of keV and a dose of 4×10 12 cm −2 . As a result, S/D region layers 29a and 29b are formed on the surface of the Si substrate 22 on both sides of the gate electrode 25 in the element region, and
A p-type introduced region layer 2 in which boron is introduced into the surface layer of the Si substrate 22 in the alignment mark forming region 21b and other than the forming regions of the resist patterns 28a and 28b.
9c to 29e (opposing region layers) are formed, and introduction region layer 2
Beneath the resist patterns 21a and 21b between 2c and 22e, boron non-introduced region layers (band-shaped region layers) 22a and 22b into which boron is not introduced are formed (FIG. 3(c)).
. FIG. 6(a) shows a top view of FIG. 3(c).

Next, after removing the resist patterns 28a and 28b, an insulating film 30 made of an SiO2 film with a thickness of about 5000 Å is formed on the entire surface by CVD (FIG. 3(d)).
).

Next, after forming a resist film 31 with a thickness of approximately 2 μm, the alignment mask (transparent substrate) is aligned with an electron beam scanning device (pattern transfer means), and an alignment pattern 32a is formed on the alignment mask (transparent substrate). 32 and the Si substrate 22 on which the introduction region layers 29c to 29e described above are formed.
After superimposing the above, He-Ne laser light (position detection light) is irradiated. At this time, due to the irradiation with the He-Ne laser beam, reflected light as shown in FIG.
, 22b, this reflected light and the reflected light from the alignment patterns 32a to 32c are detected using a reflective detector, and the alignment patterns 32a to 32c and the non-introduced area layers 22a and 22b are detected. Perform alignment. As a result, the drawing pattern of the electron beam scanning device and the gate electrode are aligned (FIG. 4(e)). Figure 6(b)
) shows a top view of FIG. 4(e).

Next, the resist film 3 is formed according to the drawing pattern.
1 is selectively irradiated with an electron beam to directly draw a pattern for forming contact holes. At this time, the alignment mark forming region 21b is not irradiated with the electron beam (FIG. 4(f)).

Next, unnecessary resist film 31 is removed by development.
(FIG. 4(g)), RIE using CF4 gas is performed using the remaining resist pattern 31a as a mask.
The insulating film 30 is selectively anisotropically etched and removed using a method. As a result, the side walls of the gate electrode 25 are made of SiO.
A sidewall 30a consisting of two films is formed, and S/D region layers 29a and 29b are formed at the periphery of the sidewall 30a.
Contact holes 33a and 33b are formed above (
Figure 5(h)).

After that, after removing the resist pattern 31a, the S/D electrode 34a is connected to the S/D region layers 29a, 29b at the bottoms of the contact holes 33a, 33b.
, 34b, the semiconductor device is completed (FIG. 5(
i)).

As described above, according to the semiconductor device having the alignment marks according to the embodiment of the present invention, the alignment marks are formed on the surface layer of the Si substrate 22, and the introduction region layers 29c to 29e facing each other, Introduction area layers 29c to 29
It is composed of band-shaped non-introduction region layers 22a and 22b sandwiched by a region e (FIG. 3(c)).

Therefore, unlike the conventional case, the alignment mark does not protrude onto the surface of the Si substrate 22, and it is possible to prevent etching residue from remaining on the side wall. Further, unlike the conventional method, it is no longer necessary to cover the alignment mark with an insulating film to prevent peeling off of etching residues, so it is possible to prevent a decrease in detection sensitivity. Furthermore, since alignment marks can be formed by ion implantation, they can be formed at the same time when forming the S/D region layers 29a and 29b in the element region (FIG. 3(c)), which saves time and effort. . Thereby, generation of dust due to etching residue can be easily prevented without much effort.

Further, according to the alignment method of the embodiment of the present invention, as shown in FIG. 4(e), the transparent substrate 32 on which the alignment pattern 32a is formed is aligned in position with the electron beam scanning device. and the Si substrate 22 on which alignment marks are formed, and then irradiate the position detection light,
The alignment pattern 32a and the non-introduction area layers 22a, 22b are aligned by detecting the reflected light from the alignment pattern 32a and the reflection light from the non-introduction area layers 22a, 22b.

Therefore, by utilizing the difference in intensity between the reflected light from the non-introduced area layers 22a and 22b and the reflected light from the introduced area layers 29c to 29e, the non-introduced area layers 22a and 22
Positioning can be performed in the same manner as before using the reflected light from b.

In the embodiment, introduction region layers 29c to 2
Boron is used as an impurity introduced into 9e,
It is also possible to use other types of impurities.

Furthermore, the light intensity of the reflected light from the non-introduced region layers 22a and 22b is greater than the light intensity of the reflected light from the introduced region layers 29c to 29e, but conversely, the light intensity of the reflected light from the non-introduced region layers 22a and 22b is Impurities are introduced into the opposing region layer 29c.
It is also possible to avoid introducing impurities into ~29e. In this case, by introducing impurities, the band-shaped region layer 22a
, 22b needs to be strong in intensity.

[0041]

As described above, according to the semiconductor device and the alignment method of the present invention, the semiconductor substrate surface layer has opposing region layers facing each other, and a region sandwiched between the opposing region layers and irradiated with position detection light. and a strip-shaped region layer that generates reflected light with a greater light intensity than the light intensity of the reflected light from the opposing strip-shaped region layer, and the alignment mark is used to perform alignment. It is carried out.

Therefore, by utilizing the difference in intensity between the reflected light from the boron-free region layer and the reflected light from the boron-introduced region layer, positioning can be performed using the reflected light from the boron-free region layer in the same way as in the conventional method. It can be performed.

Therefore, unlike the conventional case, the alignment mark does not protrude from the surface of the semiconductor substrate, and it is possible to prevent etching residue from remaining on the side wall. Further, unlike the conventional method, it is no longer necessary to cover the alignment mark with an insulating film to prevent peeling off of etching residues, so it is possible to prevent a decrease in detection sensitivity. Furthermore, since the alignment mark can be formed by ion implantation, it can be formed at the same time as, for example, forming the conductive type region layer of the element region, and it does not take much time. Thereby, generation of dust due to etching residue can be easily prevented without much effort.

[Brief explanation of drawings]

FIG. 1 is a principle diagram illustrating a semiconductor device and alignment method of the present invention.

FIG. 2 is a cross-sectional view (part 1) illustrating an alignment method and a semiconductor device manufacturing method according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view (part 2) illustrating the positioning method and semiconductor device manufacturing method according to the embodiment of the present invention.

FIG. 4 is a cross-sectional view (part 3) illustrating the positioning method and semiconductor device manufacturing method according to the embodiment of the present invention.

FIG. 5 is a cross-sectional view (No. 4) illustrating the alignment method and semiconductor device manufacturing method according to the embodiment of the present invention.

FIG. 6 is a top view illustrating an alignment method and a semiconductor device manufacturing method according to an embodiment of the present invention.

FIG. 7 is a cross-sectional view (part 1) illustrating a conventional alignment method and semiconductor device manufacturing method.

FIG. 8 is a cross-sectional view (Part 2) illustrating a conventional alignment method and semiconductor device manufacturing method.

FIG. 9 is a cross-sectional view (part 1) illustrating another conventional alignment method and semiconductor device manufacturing method.

FIG. 10 is a cross-sectional view (Part 2) illustrating another conventional alignment method and semiconductor device manufacturing method.

[Explanation of symbols] 1, 20 element formation area, 2, 21a, 21b alignment mark formation area, 3
Semiconductor substrate, 4, 5b 7a, 7b, 10, 10d, 23, 26,
30 insulating film, 5a, 24 gate insulating film, 6a, 25 gate electrode, 6b conductive film, 8a, 8b, 29a, 29b S/D region layer, 9, 2
7 Alignment mark, 10a, 10c, 30a Side wall, 10b
Heba residue, 11, 18, 31 Resist film, 11a, 11b, 11c, 28a, 28b, 31a
Resist pattern, 12 Exposure mask, 12a Mask pattern, 12b, 14a, 19a, 32a Alignment pattern, 13a to 13d, 33a, 33b Contact hole, 14, 19, 32 Alignment mask (transparent substrate), 15a, 15b, 34a , 34b S/D electrode, 16, 22 semiconductor substrate (Si substrate), 16a, 2
2a, 22b band-like region layer (non-introduction region layer), 17a
, 17b, 29c to 29e Opposing region layer (introduction region layer).

Claims (4)

[Claims] 1. Opposing region layers facing each other on a surface layer of a semiconductor substrate, and a light intensity that is sandwiched between the opposing region layers and is greater than the light intensity of light reflected from the opposing region layer upon irradiation with position detection light. What is claimed is: 1. A semiconductor device characterized by having an alignment mark made up of a band-shaped region layer that produces reflected light. 2. The semiconductor device according to claim 1, wherein the opposing region layer is a region layer into which impurities are introduced by ion implantation, and the band-shaped region layer is a region layer into which impurities are not introduced by ion implantation. . 3. The semiconductor device according to claim 1, wherein the opposing region layer is a region layer in which impurities are not introduced by ion implantation, and the band-like region layer is a region layer into which impurities are introduced by ion implantation. . 4. A transparent substrate aligned in position with a pattern transfer means and on which an alignment pattern is formed; and a semiconductor substrate on which an alignment mark according to claim 1, 2, or 3 is formed. By overlapping the above, irradiating the position detection light and detecting the reflected light from the alignment pattern and the reflected light from the alignment mark,
An alignment method comprising aligning the alignment pattern and the alignment mark.