JPH0433027A - Device for tracing specified data for updating secondary data base - Google Patents

Abstract

PURPOSE: To enable backup without delay in the case of fault at a 1st-order process controller by providing a device for tracking changes in the prescribed data of a 1st-order data base for the following update of a 2nd-order data base. CONSTITUTION: Between a 1st-order controller 30 and a 2nd-order controller 32, tracking devices 33 and 43 are provided for collecting the prescribed data in data under transfer to a 1st-order memory 32 simultaneously with the transfer to the 1st-order memory 32 and transferring these data to a backup process controller 40 later in order to update a data base for backup. Namely, since only the changed information is caught by the tracking devices 33 and 43 and the 2nd-order data base is updated, the update process can be more frequently executed in real time. Thus, when any fault information occurs, the time required for the 2nd-order controller 40 to succeed the function of the defective 1st-order controller 30 can be shortened to a minimum.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an apparatus for updating a secondary database of a redundant processor in a process control system. The present invention relates to an apparatus for tracking changes in predetermined data.

[Problems to be solved by conventional technology and invention]

No. 4,133.027, issued January 2, 1979, to J. A. Hoghn;
A process control system having a backup process control device such as that described and claimed in U.S. Pat. No. 4,141,066 issued to Y. It has a memory (RAM) and a dedicated read-only memory (ROM) and includes a next bank amplifier controller. The bank-up controller is essentially idle and thus may be performing some background tasks, or generally does not perform tasks directly related to process control functions. When a failure is detected in one of the primary process controllers, the data stored in the failed controller must be transferred to the RAM of the backup controller to carry out the actions of the primary controller. It won't happen. Such a system is called an l:N redundant system.

According to the present invention, in a 1:1 redundant system, a device e is provided for capturing and storing predetermined information when it is stored in a partial memory of a primary control device. The secondary database of the secondary device # (i.e., the secondary or bank-up control device) is periodically updated with information stored in the device of the present invention, and the updating process is performed by the CPU.

That is, it is performed to constrain the processor performance of the primary control unit, ie, to utilize a minimum amount of time without penalizing performance. Since the device of the present invention only captures (and then updates) changing sentence information, it can utilize the primary CPU, or microprocessor, more efficiently and perform the update process more frequently. It can be executed in a time-based manner.

Therefore, when a fault condition occurs, the time required for the secondary control equipment to fail and take over the functions of the primary control system is reduced to a substantially minimum.

[Means for solving problems]

Accordingly, the present invention provides an apparatus for collecting predetermined information stored in a primary database for subsequent updating of the secondary database.

The process control system includes a primary processor connected in part to memory via a bus. The primary gross sensor transfers the data to be stored to this partial memory. The apparatus of the present invention connected to the bus collects predetermined data of the data being transferred at the same time as the data is transferred to the primary memory. Predetermined data collected by the device is then transferred to the backup process controller to update the database of the backup process controller.

The device includes a storage element for storing collected data. The logical device controls the operation of the next device, including the collection of certain data. The control device of the apparatus of the present invention transfers predetermined data stored in the storage element to the bank-up process control device.

Therefore, an object of the present invention is to provide a device for collecting predetermined information.

Another object of the invention is to provide an apparatus for collecting predetermined information stored in a primary database.

Yet another object of the present invention is to provide an apparatus for collecting predetermined information stored in a primary database for subsequent updating of the secondary pig base.

These and other objects of the invention will become more apparent when considered in conjunction with the following description and accompanying drawings.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings, in which the same reference numerals indicate the same parts in the drawings,
Further, the drawings form part of the present invention.

Explanation will be made regarding FIG. FIG. 1 shows a block diagram of a process control system 10 having a plurality of redundant control devices utilizing the apparatus of the present invention, and more specifically, a primary control device 30, a secondary control device 30, and a secondary control device 30. A functional block diagram of a redundant process control device 20 including 40 is shown. In the following description, 30 of the two control devices is clearly shown as a primary control device and 40 is a secondary control device, but the control devices have bidirectionality. That is, any one of the redundant (or secondary) controllers can operate entirely as a primary or secondary controller.

The labels ``primary'' and ``secondary'' used here are merely a convenient means of identification and explanation.

Process control system 10 includes a plant control network 11 and a data highway 12 connected thereto, allowing a plurality of process control devices to be attached to data highway 12. The primary control device 30 includes a primary processor 31, a primary memory 32,
and a primary tracking device 33. The secondary controller 40 includes a secondary processor 41, a secondary memory 42, and a secondary tracking device 43.
including. The primary processor 31 and the secondary processor 41 are each connected to the data highway 12. The primary processor 31 has its primary memory 32 and the primary tracking device 3.
3, and the secondary processor 41 is connected to its secondary memory 4
2 and a secondary tracking device 43. The process control device 20 includes an analog input section (A/I) and an analog output section (A10).

Digital input section (D/I) and digital output section (D/l
)) are coupled to various inputs and outputs, which are used to indicate current information, i.e., current state, and to control processes of the process control system. Connects to various valves, pressure switches, pressure gauges, thermocouples, etc. Plant control network 11 was established on August 19, 1986 by R, A, Hea.
zel, and assigned to the same assignee as this application, may be of the type described in US Pat. No. 4,607.256. Although not shown, it is clear that various analog input/outputs and digital input/outputs are connected to the primary processor 31 and the secondary processor 41 via suitable interface devices. The device of the invention, the tracking device 33.43, will be explained in more detail below. In order to better understand the functionality and operation of the tracking device, before describing the tracking device 33.43, a system utilizing the device of the invention will be described.

Within the 70-cess control device 20, the determination as to which control device 30 or 40 should be the primary or secondary one is as follows:
This is done by downloading control personalities (ie, command information) from the plant control network 11. At that point, one of the controllers 30, 40 will become the primary controller and the other will take on the role of secondary controller, although in FIG.
40 are identified as a primary controller 30 and a secondary controller 40 for purposes of illustration. However, it will be appreciated that the primary controller could be controller 40, and similarly the secondary controller could be controller 30. After determining the primary/secondary roles of the control devices 30 and 40 in this way, the next control device f130 reads input data from valves, pressure gauges, etc., executes predetermined calculations, and outputs the results. Executes control processing algorithms, including outputting.

Data is also stored in primary memory 32.

There is an area of primary memory 32 that is designated as tracking memory (or tracking RAM). Writing to this area, the tracking RAM, is followed by the primary tracking device 33. The primary tracking device 33 stores predetermined data in its own internal storage (not shown) in a predetermined format, here shown as a packet, at the same time as it is written to the trace RAM. Upon completing its processing functions for a predetermined time interval, the primary processor 31 controls the secondary tracking device of data stored in the primary tracking device 33 by sending control signals to the primary tracking device 33. The transfer to 43 is started. Some control information, such as header information, byte count, data type, etc., is also transferred to the primary processor 31. Therefore, the secondary processor 41
retrieves the data stored in the secondary tracking device 43,
From the friend information packet stored in the secondary tracking device 43,
Generates necessary information and updates secondary memory 42. Secondary processor 41 receives those packets, performs integrity tests, and transfers the results of those tests in part to processor 31.
, calculates an address for retrieving the data value, and storing the data value at the identified address in the information packet in secondary memory 42 . By performing secondary memory updates in this manner, the primary CPU (i.e., the CPU of primary processor 31 (not shown)) does not have a performance penalty for writing trace memory; 31 bandwidth is effectively expanded.

The CPU utilized in processor 31.41 is, in the preferred embodiment, a Motoroli 68000 CPU.
selected from the series.

The primary controller 30 and the secondary controller 40 are connected via three media: the data highway 12, the link 13 between the primary tracking device 33 and the secondary tracking device 43, and the input/output Link (not shown)

This link is for A/I, A10, D/I and D
The primary processor 31 for interfacing with lo
and a path to which the secondary processor 41 is connected. Through these communication paths, the primary controller 30 can establish that the secondary controller 40 is present and operational, and that the secondary controller In order to determine when the primary controller (control device) should assume the primary state (or mode), it can be tested that the primary controller is in an operational state.

Explanation will be made regarding FIG. 2. FIG. 2 shows the allocation of time used by the primary processor 31. In the system according to the preferred embodiment of the invention, a cycle is defined as a one second time period, divided into eight subcycles. For each subcycle, the processor executes a predetermined algorithm as described above (represented as point processing in FIG. 2). The time required for point processing is less than the subcycle time. Upon completion of point processing, primary processor 31 begins transferring tracking data to secondary controller 40 (represented in FIG. 2 as a DBA data transfer). As can be easily seen from this time frame diagram, the data stored in the database of the secondary controller 40 lags the next data stored in the database of the primary controller 30 by one step (i.e., one subcycle). . (In systems where every write to primary memory is written to secondary memory, the primary and secondary maintain the same database. If a failure occurs during transmission, then the secondary will have a subset of bytes, ie, mismatched data. ) In the system of the present invention, as mentioned above, the secondary database has complete data, but is one step behind the data in the next database.

Explanation will be made regarding FIG. In FIG. 3, the primary memory 32
A partial memory map of is shown. This includes scanned data containing the actual values of the n9 outputs read from the valves, pressure gauges, etc. The portion shown as configuration data includes information indicating the selected option, the state of the point arrangement, the type of algorithm being executed, etc. The portion shown as process data to be banked up includes the results of the algorithm. Additionally, certain information is included indicating various functions in progress, such as various timers that are set, various alarms that are set, etc. The area of memory designated as DBA data is an area of partial memory 32 (i.e., RAM) that is allocated as trace memory 1. Writes to this area of primary memory 32 are collected by primary tracer 33 ( The data collected by the primary tracking device 33 takes the form of a predefined t'L packet, which is further described below.

Explanation will be made regarding FIG. 4. FIG. 4 shows seven orders of packets generated by primary tracking device 33 in a preferred embodiment of the invention. The upper data strobe value and the lower data strobe value indicate the value of the least significant address bits, and depending on the layout of the tracking memory, the four most significant address bits can be reserved. A trace memory packet is constructed on every write (byte or word) to trace memory, but only while memory trace is requested. One of the important features of the primary tracker 33 is that there is no performance penalty when writing to the track memory. The method of transferring changes to the primary database from the primary controller 30 to the secondary controller 40 using the apparatus of the present invention is described in further detail in the related applications cited above.

Explanation will be made regarding FIG. In FIG. 5, the primary control device 3
A block diagram of a preferred embodiment of the next tracking device 33 is also shown. The primary processor 31 is connected to a primary memory 32 via a primary tracker bus 301, also referred to herein as a local bus. A primary tracking device 33 is also connected to local bus 301 .

A data terminal of the first RAM 320 is connected to a data line of the local bus 301. The data terminal of the second RAM 330 is connected to the output terminal of a multiplexer (MUX) 310, the first input terminal of the second RAM 330 is connected to the data line of the local bus 301, and the second input terminal of the second RAM 330 is connected to the data line of the local bus 301. is connected to the address line of the local bus 301.

A counter 351 that sequentially counts addresses of the first RAM 320 and the second RAM 330 is a MUX 35 '2.
The second input terminal of MUX 352 is connected to the address line of local bus 301 .

A token bus controller (TBC) 353 that controls communication between the secondary tracking device 33 and the secondary tracking device 43 is connected to the local bus 30t. An interface device 354 connected to TBC 353 is also connected to link 13 and forms an interface between the TBCs. The TBC353 of the preferred embodiment of the present invention is manufactured by Motorola
MC68824Tok@n -Passing B
usController.

The tracking data packet is stored in the RAM 320 of the primary tracking device 33.
．． 330. Three-word packets are not stored sequentially, but in column form.

The primary tracker 133 stores packets based on the primary tracker's counter 351, which increments by one each time a packet is stored. This counter 351 is used by the primary processor 3 to check the amount of data to be transferred.
1 allows you to read more.

During the transfer of data stored in RAMs 320, 330, TBC 353 (i.e., the TBCs of the primary and secondary tracking devices) transfers the data so that the data is stored in the secondary tracking device's RAM (not shown). pass. As mentioned earlier, the structure of the secondary tracking device 43 is the same as that of the primary tracking device. Control logic 355 connects local bus 301
Connect to the control signals 5ELI, 5EL2,
Contains logic 357 that generates C0NT1, etc. Depending on the function to be performed, those signals track (collect or capture) data being written to primary memory 32 by the primary processor or to RAM 320,
Depending on whether data from 330 is to be stored in primary memory 32, the first input terminal or the second input terminal is selected. A CPU 356 connected to local bus 301 is also included in control logic 355 and coordinates control of the tracking device with primary processor 31.

Explanation will be made regarding FIG. 6. FIG. 6 shows a detailed block diagram of the structure of the memory elements, RAMs 320 and 330, of a preferred embodiment of the present invention. MUX310 is [1
311,! :, MUX 23j2 and MUX3313
It consists of The first RAM 320 is RAM3
321 and RAMD 2322, and the second RA
M330 has RAMA1331, RAMA2332,
RAMA3333. Each RAM 321, 322, 331, 332, 33 of the preferred embodiment
3 is 32K×8 bit RAM. In this way, R
AMDI 321 and RAPI[) 2322 store 16-bit data values (shown in Figure 4). RAMAl
RAM 333 stores the third word of the packet, ie, the three address bits and the upper/lower strobe bits. A predefined area of primary memory 32 (in the preferred embodiment, storage location 170)
000 to 19FFFF, FIX) fl;l:, stores the data to be captured. When the primary processor 31 is writing to this area of memory, the primary tracker 33 also captures the data and address and stores it in a 40-bit wide memory, RAMDI 321.
RAMD2322, RAMAl 331. RAMA2
332 and the first word of RAMA 3333, respectively. This memory is called "wide memory." 16
A total of 3 bits of data and a 19-bit address
It uses only 7 bits and also requires two control strobes (strobes UDS and LDS) to indicate whether a word or byte has been partially modified in memory. Wide memory is addressed by a 15-bit address cunter 351 during this time. The value of counter 351 is incremented by one for each wide write.

Thus, wide writes are performed sequentially to wide memory 37 bits at a time. The counter is initialized to zero by CPU 356, which forms part of control logic 355.

Further, the CPU 356 can read the value of the counter 351. Once the data collection is complete (i.e. at the end of the point processing time slot), the primary processor 31 should initiate the transfer to the primary tracking device 33 to the secondary controller 40, i.e. to the secondary tracking device 43. Notify.

Transfer is performed by TBC353. TBC is RAM
empty in the form of a 16-bit wide word (“narrow read screen”)
). When addressing RAM in narrow format, the address space (IC0OOO to IEFFFFF)
use. Since this space occupies an odd width of RAM, three banks of 16-bit wide address space are required. However, one of those banks (
IEOOOOKA to IEFFFFF) has significant data only at its lower height. The secondary tracker's TBC receives the data and performs a "narrow write" to its RAM. When all data has been transferred, counter 3
51 is reset and the next subcycle begins. During the next subcycle, the control logic RA of the secondary tracker
Duplicating the contents of the data stored in primary memory 32 by beginning to empty the contents of M and storing the data in secondary memory 42 .

Although not shown, the preferred embodiment of the present invention utilizes parity checking as a method of protecting memory accesses. It will be apparent to those skilled in the art that other forms of memory protection may be utilized without departing from the scope of the invention, but these are not described here.

While what is considered to be the preferred embodiment of the invention has been described, it will be obvious that many changes and modifications may be made without departing from the essential spirit of the invention. It is therefore intended that the appended claims cover all such changes and modifications as fall within the true scope of the invention.

[Brief explanation of the drawing]

FIG. 1 is a block diagram illustrating a process control system with redundant controllers; FIG. 2 is a diagram illustrating the time allocation defining one cycle of the controller; and FIG. 3 is a preferred embodiment of the invention. FIG. 4 is a partial memory map of a portion of the memory of an example control unit; FIG. 4 is a diagram illustrating the packet format of data captured in a preferred embodiment of the present invention; FIG. 5 is a diagram illustrating a preferred embodiment of a primary tracking device. A block diagram of the primary controller, FIG. 6, with particular emphasis on
FIG. 2 is a block diagram illustrating a storage element of a preferred embodiment of the present invention. 10... Process control system, 20... Process control device, 30... Primary control device, 31...
・Primary C sensor, 32...Primary memory, 33...
...Primary tracking device, 40...Secondary control device, 41.
...Primary processor, 42...Secondary memory, 43
...Secondary tracking device, 301...Primary control device bus, 310...Multiplexer, 320...First RAM, 330...Second RAM, 35
1... Counter, 352... Token pass control device, 354... Interface device, 355...
...Control logic, 356...CPU. Engraving of drawings (no change in content) Fig, 2 Fig, Ft'g, Procedural amendment (Kiya) 1. Indication of case in hand in 1995 Patent application No. 13g63 Cow No. 2, name of invention with two tabs !Relationship between the prescribed data and the case of the person making the amendment Patent Applicant's name (name) New Ill Incorporated F6, subject of amendment (subject of amendment) Contents of amendments to the scope of claims) As shown in the attached sheet, 1゜2゜Indication of the case: Japanese Patent Application No. 1996-138634 Name of the invention In order to update the secondary database, the specified date 4゜Agent's residence: 2 Nagata-cho, Chiyoda-ku, Tokyo No. 4-2 Hidewa Tameike Building Yamakawa International Patent Office Claims (1) Part of the processor is connected to a part of the memory via a bus, and the primary processor is to be stored in the primary memory. included in a process control system that transfers data, connected to the bus, and configured to collect predetermined data among the transferred data simultaneously with the transfer of the data to the primary memory; An apparatus for sequentially updating a database of a backup process control device, comprising: a) means for storing predetermined collected data; b) means operatively connected to said storage means for storing predetermined data including collection of predetermined data; Logic means for controlling the operation of the apparatus; C) control means operatively connected to said storage means and said logic means for transferring predetermined data stored in said storage means to a backup process control device. (2) In a device that simultaneously collects predetermined data among data transferred to the memory via a bus in order to continuously update the backup memory, the device comprises: a) storage means for storing the predetermined data; b) ) anal ffE
C) Logic means connected to the storage means for controlling the collection of the predetermined data; C) Logic means connected to the storage means and the logic means for storing the predetermined data stored in the storage means into a backup memory; and a control means for transmitting data to the computer. Back up your data Memory (±)
In a device that simultaneously collects predetermined data among data being transferred to the memory via a bus in order to continuously update the backup memory, the device comprises: a) storage means for storing the predetermined data; and b) storage. and logic means connected to means for controlling collection of said predetermined data.

Claims (3)

[Claims] (1) having a primary processor connected to a primary memory via a bus, the primary processor being included in a process control system and connected to the bus for transferring data to be stored in the primary memory; In an apparatus that collects predetermined data among the transferred data at the same time as the data is transferred to the primary memory, and sequentially updates a database of a backup process control device with the collected predetermined data, comprising: a) storage means for storing predetermined data collected; b) logic means operatively connected to said storage means for controlling the operation of said apparatus, including the collection of predetermined data; c) said storage means and said logic. control means operatively connected to the means for transferring predetermined data stored in the storage means to a backup process control device. (2) To subsequently update the backup memory,
A device for simultaneously collecting predetermined data among data being transferred to a memory via a bus, comprising: a) storage means for storing the predetermined data; b) connected to the storage means and configured to collect the predetermined data. an apparatus comprising: logic means for controlling; c) control means connected to said storage means and said logic means for transferring predetermined data stored in said storage means to a backup memory. (3) To subsequently update the backup memory,
A device for simultaneously collecting predetermined data among data being transferred to a memory via a bus, comprising: a) storage means for storing the predetermined data; b) connected to the storage means and configured to collect the predetermined data. and controlling logic means.