JPH0432974A - Determination system for wiring length of discrete wire - Google Patents

Abstract

PURPOSE:To improve the operation efficiency of DW(discrete wire) wiring by finding the margin value of variation in designed delay value in a DW wiring object section and determining the wiring length in the DW wiring object section within the range of the delay margin value. CONSTITUTION:A margin value calculating means 1 calculates a margin value which indicates the difference between an expected value of an integrated delay value and an actual integrated delay value at each section point in each route connecting an input point and an output point of a network. Then a DW router 13 refers to data regarding the margin value of the margin value calculating means 11 and data regarding the discrete wire laying object section in a DW wiring data storage means 12 to determine the wiring length of the discrete wire within the range of the margin value in each discrete wire object section. Consequently, the operation efficiency of the DW wiring is improved.

Description

[Detailed Description of the Invention] [Summary] Regarding a method for determining the wiring length of discrete wires to be laid when wiring using discrete wires occurs in a photographic printing circuit network, the present invention relates to a method for determining the wiring length of discrete wires to be laid in a photo printing circuit network. The purpose of this method is to increase the degree of freedom in selecting the wire length, make it easier to determine the wire length, and improve the wiring work efficiency.The purpose is to determine the wire length when discrete wires are used in the photo printing circuit network. In the method, for each interval point in each route connecting each input point and output point of a circuit network, a margin value calculation that calculates a margin value indicating the difference between the expected value of the cumulative delay value and the actual cumulative delay value. means and
A DW wiring data storage means in which data regarding the discrete wire wiring target section and the wiring length of each discrete wire wired therein is stored, and each data of the margin value calculation means and the DW wiring data storage means is stored. In reference to,
A configuration is provided in which a discrete wire router is provided to determine the wiring length of the discrete wire within a margin value in each discrete wire wiring target section.

[Industrial application field]

The present invention provides a method for determining the wiring length of discrete wires, which determines the wiring length of the discrete wires to be laid when wiring with discrete wires occurs in photo printed circuits including printed wiring circuits, integrated circuits, etc. Regarding the method.

[Conventional technology]

In photo printing circuits such as printed wiring circuits that include high-density elements such as integrated circuits, there is an increasing demand for faster processing, and expectations for the delay value of routes connecting arbitrary input points and output points in photo printing circuits are increasing. It has become necessary to reduce the value.

In such photo printed circuits, repair of pattern defects that occur during the manufacturing of photo printed circuit boards, i.e. touch-up (TOUCHUP, hereinafter referred to as T/U), or design changes after manufacturing the photo printed circuits, etc. , Discrete wires are used to rewire the touch-up points or to install new wiring in response to design changes.

In this case, it is not allowed that the section targeted for discrete wire wiring (hereinafter referred to as DW wiring) exceeds a prescribed delay value due to DW wiring, that is, becomes over-delayed.

Therefore, in the past, a discrete wire router (hereinafter referred to as a DW router) was used to determine the wiring length of the discrete wire so that the DW wiring target section had a value within a specified delay value range. I was doing it.

FIG. 5 shows the work process of the conventional discrete wire wiring length determination method.

Hereinafter, a conventional method for determining the wiring length of discrete wires will be explained in accordance with the order shown in this work process diagram.

(1) Process (photo) Various data necessary for designing a desired logic circuit on a printed circuit board are created in advance and stored in the design database 21.
will be registered.

(2) Process C) Using the design database 21, a logic design for designing a desired logic circuit on a photographic printing board and a mounting design for mounting a photographic printing circuit on which this logic circuit is mounted are performed.

(3) Process (3) Logical design and implementation design (E/C) performed in process (2)
Based on this, pattern design for the photo printed circuit board is performed, and locations requiring DW wiring are determined based on design changes (E/C).

(4) Step (4) A photographic printed circuit board is manufactured according to the pattern design made in step (3), and locations where Talatia knobs (T/U) are required are determined.

(5) Process (5) Data on design changes obtained in process (3) (hereinafter referred to as
E/C data) is registered in the E/C data file 22.

(6) Process (6) The touch-up location data (hereinafter referred to as T/U data) obtained in Step (4) is stored in the T/U data file 2.
Registered in 3.

(7) Process (7) The DW router 24 stores the E/C data file 22 and the T/
Data regarding design change locations and touch-up locations are extracted from the U data file 23, and first, a DW wiring target section is determined.

For these DW wiring target sections, a constant error tolerance range α is determined in accordance with the wiring length.

The DW router 24 selects the length of the discrete wire in each DWW line target section so that the length has a delay value within a designed specified error tolerance range (α).

(8) Step (8) According to each wiring length selected by the DW router 24,
DWW line work will be performed on the DWW line target section.

(9) Process (9) When all DWW line work for each DWW line target section is completed, check whether each route in the photo printing circuit including each DWW line target section is within the specified delay value range. A test will be conducted for this purpose. For the DWW line target section of the route that is over-delayed, the DW wiring is redone so that it falls within the prescribed delay value range.

In addition, if it is actually difficult to run the wiring with the wiring length instructed by the DW router 24 in step (7), the manufacturing department should contact the design department and have them determine the possible wiring length. Do it like this.

[Problem to be solved by the invention]

The conventional method for determining the wiring length of DW wiring is as follows:
A certain error tolerance range is determined for the WW line target section, and each DWW
The wiring length of the line target section was selected so that it fell within the error tolerance range.

For this reason, there is no flexibility when selecting the wiring length for DW wiring, and if a situation arises where it is difficult to perform DW wiring with the selected wiring length, the manufacturing department will contact the design department each time. Since a new wiring length has to be determined using the same method, it takes time to determine an appropriate wiring length, which is disadvantageous in that the working efficiency of DW wiring is reduced.

The present invention increases the degree of freedom in selecting a wiring length for DW wiring that satisfies conditions within a specified delay value range, facilitates the determination of the wiring length, and improves the work efficiency of DW wiring. The purpose of this invention is to provide an improved method for determining the length of discrete wires.

[Means to solve the problem]

The means adopted by the present invention to solve the above-mentioned problems are as follows:
This will be explained with reference to FIG. FIG. 1 is a block diagram showing the basic configuration of the present invention.

In FIG. 1, 11 is a margin calculation means, which calculates the difference between the expected cumulative delay value and the actual cumulative delay value for each section point in each route connecting each input point and output point of the circuit network. Processing is performed to calculate a margin value indicating .

Reference numeral 12 denotes a DWW line data storage means, which stores data regarding the discrete wire wiring target section and the wiring length of each discrete wire laid there.

Reference numeral 13 denotes a DW router, which performs discrete wire wiring by referring to the data regarding the margin value of the margin value calculation means 11 and the data regarding the discrete wire wiring target section of the DWW line data storage means 12. A process is performed to determine the wiring length of the discrete wire within the margin value in the wiring target section.

[For production]

When a circuit network such as a logic circuit is designed in a photo printing circuit, the margin value calculation means 11 calculates each route connecting each input point and output point of the circuit network based on a design database (not shown) regarding the circuit network. For each section point within the range, a margin value indicating the difference between the expected value of the cumulative delay value and the actual cumulative delay value is calculated.

On the other hand, a pattern design for the circuit network of the photo printing circuit is performed based on the logical design and implementation design, and the DWW line target section such as T/U data and E/C data and the DW line of each section are
Data regarding the wiring length of the wiring is available in the DW wiring data county section 1.
2 is stored.

The DW router 13 refers to the data regarding the DW line target section and the wiring length of the DW wiring in each section in the DW wiring data district section 12, and determines the DW wiring within the margin value ρ range of each route where the DW wiring is performed. Performs processing to determine wiring length.

That is, the DW router 13
calculate the DWW line target section information, the margin value calculation unit 11 calculates the margin value of the integrated delay value of the DWW line target section, and determine the wiring length of the DWW line target section within the range of the delay margin value. do.

The route delay margin value is variable, and the wire length of DW wiring selected based on it is generally larger than the wire length of the conventional fixed error tolerance range α, so the wire length Easy to select 0 For example, it is ideal to set the wiring length to a value that matches the design value, but if it is difficult to wire with a wiring length that matches the design value, set the delay margin value. A long wiring length can be selected within the range of .

Thereafter, DW wiring is performed for the DWW line target section according to the selected wiring length.

As explained above, the variable margin value for the designed delay value in the DWW line target section is determined, and the wiring length of the DWW line target section is determined within the range of the delay margin value. It is possible to increase the degree of freedom in selecting the wiring length of the DW wiring that satisfies the conditions within the value range, making it easier to determine the wiring length, and improving the working efficiency of the DW wiring.

〔Example〕

An embodiment of the present invention will be described with reference to FIGS. 2 to 4, taking as an example a case in which a logic circuit is formed on a photographic printed board. Fig. 2 is a process diagram of an embodiment of the present invention, Fig. 3 is an explanatory diagram of the cumulative delay value and margin value of the embodiment, and Fig. 4 is a flowchart of the wiring length selection process of the DW router of the embodiment. .

(A) Structure of the Embodiment In FIG. 2, (1) to (9) are processing steps, and the contents of the processing will be explained in the section of the operation of the next embodiment. Further, the margin value calculation means 11, the DWW line data storage means 12, and the DW router 13 are as described in FIG.

A design database 110 stores various data necessary for designing a desired logic circuit on a photographic printed board.

In the margin value calculation means 11, reference numeral 111 is a margin value calculation unit, which calculates, for each route of the circuit network, the difference between the expected design value of the delay value and the actual integrated delay value in each section within the route. Calculate the margin value.

Reference numeral 112 is a margin value file in which the margin values calculated by the margin value calculation unit lll are stored.

In the DW wiring data collection section 12, 121 is an E/C data file in which E/C data is stored. 122 is a T/U data file in which T/U data is stored.

(B) Operation of the Embodiment The operation of the embodiment will be explained with reference to FIGS. 2 to 4 in accordance with the processing order of the processing steps shown in FIG.

(1) Process (1) Various data necessary for designing a desired logic circuit on a photographic printed board are created in advance, and a design database 11
Registered as 0.

(2) Step (2) With reference to the design database 110, a logic design for designing a desired logic circuit on a photo-printed board and a mounting design for mounting a photo-printed circuit on which this logic circuit is mounted are performed. .

(Step (3)) The margin value calculation unit 111 of the margin value calculation means 11 refers to the design database 110 and calculates each interval point within the route for each route connecting each input point and output point of the logic circuit. A margin value indicating the difference between the expected value of the cumulative delay value and the actual cumulative delay value is calculated.

Figure 3 shows examples of the expected and actual cumulative delay values at each interval point in each route connecting each input point and output point of a logic circuit, as well as the margin value indicating the difference between the two. .

In FIG. 3, 21-26 are logic blocks such as AND circuits and flip-flops, and 31-35 are wiring sections connecting each logic block.

The logical block 20 is a logical block described to explain the configuration of each of the logical blocks 21 to 26, and "the number N surrounded by circles" indicates the bin N of the logical block.

"B" indicates the delay value (block delay value) of the logical block. rND indicates the delay value (net delay value) of the wiring section. "T" indicates the cumulative delay value up to the section point of interest (bin N in the figure). r3. is the interval point of interest (in the figure, bin N
) shows the margin value. "*E" is the expected value of the designed cumulative delay value at the final point of the route.

The margin value S is calculated from the expected value *E and the cumulative delay value T using the following formula.

S = *E-T Figure 3 shows the block delay value B, net delay value ND, integrated delay value T, margin value S, and final end of the route for each logical block and wiring section, which were obtained in this way. It shows the expected value *E.

For example, the integrated delay value T of bin 8 of the logic block 23
is 11, and the margin value is 1.

On the other hand, the cumulative delay value T of bin 9 of the logic block 26 is 14, and the margin value is -2. If the margin value is a positive value, it indicates that there is a margin in the integrated delay value T, and if it is a negative value, it indicates that there is no margin in the integrated delay value T.

Therefore, it can be seen that there is a margin in the delay value of the route leading to the logical block 23, but there is no margin in the delay value of the route leading to the logical block 26.

The integrated delay value and its margin value at each section point in each route of the logic circuit obtained as described above are registered in the margin value file 112.

(4) Step (4) Based on the logic design and packaging design done in step (2), pattern design for the photo printed circuit board is performed, and based on design changes, discrete wire wiring (hereinafter referred to as DW) is performed. (shown with wiring) is required.

(5) Step (5) A photo printed circuit board is manufactured according to the pattern design made in step (4), and locations requiring touch-up are determined. Now, assume that touch-up occurs in the wiring section 32.

(6) Process (6) Data on design changes determined in process (4) (hereinafter referred to as
) is the E/C data file 121
will be registered.

(7) Process (7) The touch-up location data (hereinafter referred to as T/U data) obtained in Step (5) is stored in T/U data file 1.
Registered on 22.

(8) Process (8) The DW router 13 stores the E/C data file 121 and the T
/U Read design change locations and touch-up locations from the data file 122, and set these as DW wiring target sections. The DW wiring target section in this embodiment is the wiring section 32 as described above. The wiring length selection process performed by the DW router 13 will be explained below according to the process steps with reference to FIG.

■ Processing S.

From the margin value file 112, the delay value of each wiring section in each route of the logic circuit, the integrated delay value and margin value at each section point are input. If these data are not registered in the margin file 112, process S described later
Move on to 4.

■ Processing S2 If these data are registered in the margin value file 112, it is further determined whether or not margin values are defined for the wiring section 32, which is the DW wiring target section obtained from the T/U data file 122. Determine whether If no definition has been made, the process moves to processing S4, which will be described later.

■ Processing S.

From the T/U data file 122, a delay value 3 is obtained as the delay value for the wiring section 32, as shown in FIG. On the other hand, from the margin value file 112, since the margin value of the bin 8 of the logic block 23 is 1 as shown in FIG. 3, 1 is obtained as the margin value of the delay value of the wiring section 32.

Therefore, from the delay values of both, the delay value is 3 to 4.
The wiring length of the wiring section 32 is selected within the range of .

In this case, DW&! The line length is selected to be as close as possible to the delay value of the pattern of the wiring section. When wiring is difficult, perform DW wiring within the wiring length range, including the allowance.By doing this, a long wiring length will be selected, so a wiring length that is difficult to be laid will be selected. This prevents the situation from occurring, and improves the efficiency of wiring work.

For example, even if it is difficult to route a designed delay value of 3 in the wiring section 32, a wiring length with a delay value of 4 or close to it within the margin is selected, so that the wiring can be completed easily. This makes it easy to use, eliminates the need to contact the design department as in the past, and improves wiring work efficiency.

If a valid wiring length within the margin value is selected, step (9), which will be described later, is performed. Note that when the margin value is a negative value, the DW wiring length is determined within a certain error tolerance range as before.

■ Processing S4 If the margin value related to the logic circuit is not registered in the margin value file 112 in the processing SI, and if the margin value of the wiring section 32 is not defined in the processing S2, the T/U It is checked whether the wiring length of the wiring section 32 obtained from the data file 122 is within an error tolerance defined for each DW wiring target section.

If the wiring length is within a predetermined error tolerance, step (9), which will be described later, is performed.

■ Processing S.

If the delay value of the wiring section 32 is not within a predetermined error tolerance in step S4, an error is notified due to over-delay.

(9) Step (9) According to each wiring length selected by the DW router 13,
DW wiring work is performed for the DW wiring target section.

0ω Process 00) When all the DW wiring work for each DW wiring target section is completed, check whether each route in the photo printing circuit including each DW wiring target section is within the specified delay value range. A test will be conducted for this purpose.

Although one embodiment of the present invention has been described above, the present invention is not limited to this embodiment, but can be implemented in various forms according to the gist of the invention.

For example, when DW wiring is performed in a plurality of sections within one route, the wiring length is selected in order from the section with the smallest margin value. In this way, it becomes possible to select a sufficient wiring length for each DW wiring target section.

〔Effect of the invention〕

As explained above, the present invention calculates a variable margin value for a designed delay value in a DW wiring target section,
Since the wiring length of the DW wiring target section is determined within the range of the delay margin value, the degree of freedom in selecting the wiring length of the DW wiring that satisfies the conditions within the specified delay value range is increased. This makes it easier to determine the wiring length and improves the work efficiency of DW wiring.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of the basic configuration of the present invention, Fig. 2 is a process diagram of an embodiment of the present invention, Fig. 3 is an explanatory diagram of the integrated delay value and margin value of the embodiment, and Fig. 4 is an illustration of the same embodiment. FIG. 5 is an explanatory diagram of a conventional discrete wire wiring length selection process. 1 and 2, 11... Margin value calculation means, 12... DW wiring data storage means, 13... Discrete wire router (DW router), 110... Design database, 111
...Margin value calculation unit, 112...Margin value file, 1
21...E/C data file, 122...T/U
data file. Basic configuration of the present invention Fig. 1

Claims (1)

[Scope of Claims] In a discrete wire wiring length determination method for determining the wiring length of discrete wires to be laid when wiring by discrete wires occurs in a photo printing circuit network, (a) circuit Margin value calculation means (11) for calculating a margin value indicating the difference between the expected value of the cumulative delay value and the actual cumulative delay value for each section point in each route connecting each input point and output point of the network; , (b) DW wiring data storage means (12) in which data regarding the discrete wire wiring target section and the wiring length of each discrete wire wired therein are stored; (c) margin value calculation means ( With reference to the data regarding the margin value in 11) and the data regarding the discrete wire wiring target section in the DW wiring data storage means (12), the margin value in each discrete wire wiring target section where discrete wire wiring is performed is determined. A method for determining the wiring length of a discrete wire, comprising: a discrete wire router (13) that determines the wiring length of the discrete wire within a range of .