JPH04329664A - Manufacture of semiconductor device using high resistance element - Google Patents
Manufacture of semiconductor device using high resistance elementInfo
- Publication number
- JPH04329664A JPH04329664A JP12856791A JP12856791A JPH04329664A JP H04329664 A JPH04329664 A JP H04329664A JP 12856791 A JP12856791 A JP 12856791A JP 12856791 A JP12856791 A JP 12856791A JP H04329664 A JPH04329664 A JP H04329664A
- Authority
- JP
- Japan
- Prior art keywords
- film
- polycrystalline silicon
- resistance element
- high resistance
- entire surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 42
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 35
- 238000000034 method Methods 0.000 claims abstract description 13
- 239000012535 impurity Substances 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims description 14
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 7
- 150000002500 ions Chemical class 0.000 claims description 5
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims description 4
- 239000007788 liquid Substances 0.000 claims description 4
- 229910017604 nitric acid Inorganic materials 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 2
- 239000002184 metal Substances 0.000 abstract description 16
- 150000004767 nitrides Chemical class 0.000 description 16
- 238000005468 ion implantation Methods 0.000 description 8
- 238000007796 conventional method Methods 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 5
- 239000010410 layer Substances 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000005360 phosphosilicate glass Substances 0.000 description 1
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は半導体基板上に高抵抗素
子を設け、配線領域の抵抗値を低下させる高抵抗素子を
有する半導体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a high resistance element provided on a semiconductor substrate to reduce the resistance value of a wiring region.
【０００２】0002
【従来の技術】図４乃至図６は従来の高抵抗素子を有す
る半導体装置の製造方法を工程順に示す断面図である。2. Description of the Related Art FIGS. 4 to 6 are cross-sectional views showing a conventional method of manufacturing a semiconductor device having a high resistance element in order of steps.
【０００３】先ず、図４に示すように、半導体基板１の
表面にＮ型拡散層２及び酸化膜３を選択的に形成し、こ
のＮ型拡散層２及び酸化膜３を含む半導体基板１上に多
結晶シリコン膜４を選択的に形成する。このようにして
下地デバイスを形成した後、全面に膜厚が例えば約２０
００Åの酸化膜５を成長させる。次に、Ｎ型拡散層２の
直上域の酸化膜５を選択的に除去した後、全面に膜厚が
例えば約１０００Åの多結晶シリコン膜６を成長させる
。次いで、この多結晶シリコン膜６上にフォトリソグラ
フィ技術を使用してフォトレジスト膜（図示せず）をパ
ターン形成し、このフォトレジスト膜をマスクとして多
結晶シリコン膜６をエッチングした後、このフォトレジ
スト膜を除去する。First, as shown in FIG. 4, an N-type diffusion layer 2 and an oxide film 3 are selectively formed on the surface of a semiconductor substrate 1. A polycrystalline silicon film 4 is selectively formed. After forming the base device in this way, the film thickness is about 20 mm over the entire surface, for example.
An oxide film 5 with a thickness of 0.00 Å is grown. Next, after selectively removing the oxide film 5 directly above the N-type diffusion layer 2, a polycrystalline silicon film 6 having a thickness of, for example, about 1000 Å is grown over the entire surface. Next, a photoresist film (not shown) is patterned on this polycrystalline silicon film 6 using photolithography technology, and the polycrystalline silicon film 6 is etched using this photoresist film as a mask. Remove membrane.
【０００４】次に、図５に示すように、全面に膜厚が例
えば約１５００Åの窒化膜１１を成長させる。次いで、
この窒化膜１１上にフォトリソグラフィ技術を使用して
フォトレジスト膜（図示せず）をパターン形成し、この
フォトレジスト膜をマスクとして窒化膜１１をエッチン
グした後、このフォトレジスト膜を除去する。これによ
り、多結晶シリコン膜６の高抵抗素子形成予定領域上に
窒化膜１１をパターン形成する。次に、窒化膜１１をマ
スクとして、イオン注入量が例えば約１０１５ｃｍ−３
の条件にて全面にリンをイオン注入することにより、多
結晶シリコン膜６の配線領域の抵抗値を低下させる。次
いで、全面に膜厚が例えば約５０００ÅのＢＰＳＧ（ホ
ウ素−リン珪酸ガラス）膜を成長させた後、窒素雰囲気
中で約 ８５０℃の温度で３０分間熱処理する。Next, as shown in FIG. 5, a nitride film 11 having a thickness of, for example, about 1500 Å is grown over the entire surface. Then,
A photoresist film (not shown) is patterned on this nitride film 11 using photolithography technology, the nitride film 11 is etched using this photoresist film as a mask, and then this photoresist film is removed. As a result, a nitride film 11 is patterned on a region of the polycrystalline silicon film 6 where a high resistance element is to be formed. Next, using the nitride film 11 as a mask, the ion implantation amount is, for example, about 1015 cm-3.
By ion-implanting phosphorus over the entire surface under these conditions, the resistance value of the wiring region of the polycrystalline silicon film 6 is lowered. Next, a BPSG (boron-phosphosilicate glass) film having a thickness of, for example, about 5000 Å is grown on the entire surface, and then heat-treated at a temperature of about 850° C. for 30 minutes in a nitrogen atmosphere.
【０００５】次に、図６に示すように、多結晶シリコン
膜６に到達するコンタクト穴（図示せず）を形成した後
、全面に厚さが例えば約 １．０μｍの金属配線１０を
被着する。次に、この金属配線１０上にフォトレジスト
膜（図示せず）をパターン形成し、このフォトレジスト
膜をマスクとして金属配線１０をエッチングした後、こ
のフォトレジスト膜を除去する。このようにして高抵抗
素子を有する半導体装置を製造することができる。Next, as shown in FIG. 6, after forming a contact hole (not shown) reaching the polycrystalline silicon film 6, a metal wiring 10 having a thickness of, for example, about 1.0 μm is deposited on the entire surface. do. Next, a photoresist film (not shown) is patterned on the metal wiring 10, the metal wiring 10 is etched using the photoresist film as a mask, and then the photoresist film is removed. In this way, a semiconductor device having a high resistance element can be manufactured.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、上述し
た従来の高抵抗素子を有する半導体装置の製造方法にお
いては、窒化膜１１をエッチングする際にオーバーエッ
チングとなるため、エッチングの選択比が２：１と小さ
い多結晶シリコン膜６の配線領域もエッチングされてし
まう。このため、低抵抗であるべき配線領域の多結晶シ
リコン膜６は、その膜厚が薄くなって高抵抗になってし
まうという問題点がある。However, in the above-described conventional method for manufacturing a semiconductor device having a high resistance element, over-etching occurs when etching the nitride film 11, so that the etching selection ratio is 2:1. The small wiring area of the polycrystalline silicon film 6 is also etched. Therefore, there is a problem in that the polycrystalline silicon film 6 in the wiring region, which should have low resistance, becomes thin and has high resistance.
【０００７】また、イオン注入時のマスクとして使用し
た窒化膜１１をそのまま層間絶縁膜として使用すると共
に、窒化膜１１のオーバーエッチングにより下地絶縁膜
もエッチングされるため、層間絶縁膜の段差が大きくな
り、この段差部で金属配線１０が断線しやすいという問
題点がある。Furthermore, since the nitride film 11 used as a mask during ion implantation is used as it is as an interlayer insulating film, and the underlying insulating film is also etched due to over-etching of the nitride film 11, the level difference in the interlayer insulating film becomes large. However, there is a problem in that the metal wiring 10 is easily disconnected at this stepped portion.
【０００８】本発明はかかる問題点に鑑みてなされたも
のであって、配線領域となる多結晶シリコン膜の抵抗値
を十分に低減できると共に、金属配線の断線を防止でき
る高抵抗素子を有する半導体装置の製造方法を提供する
ことを目的とする。The present invention has been made in view of these problems, and provides a semiconductor having a high resistance element that can sufficiently reduce the resistance value of a polycrystalline silicon film serving as a wiring region and prevent disconnection of metal wiring. The purpose is to provide a method for manufacturing the device.
【０００９】[0009]
【課題を解決するための手段】本発明に係る高抵抗素子
を有する半導体装置の製造方法は、半導体基板に下地デ
バイスを形成した後全面に第１の絶縁膜を成長させる工
程と、この第１の絶縁膜上に多結晶シリコン膜を成長さ
せる工程と、この多結晶シリコン膜を選択的にエッチン
グする工程と、前記多結晶シリコン膜の少なくとも高抵
抗素子形成予定領域上にフォトレジスト膜をパターン形
成しこのフォトレジスト膜をマスクとして全面に不純物
をイオン注入する工程と、前記フォトレジスト膜を除去
した後全面に第２の絶縁膜を成長させる工程とを有する
ことを特徴とする。[Means for Solving the Problems] A method of manufacturing a semiconductor device having a high resistance element according to the present invention includes the steps of forming a base device on a semiconductor substrate and then growing a first insulating film on the entire surface; a step of growing a polycrystalline silicon film on the insulating film, a step of selectively etching the polycrystalline silicon film, and a patterning of a photoresist film on at least a region where a high resistance element is to be formed on the polycrystalline silicon film. The method is characterized by comprising a step of implanting impurity ions into the entire surface using the photoresist film as a mask, and a step of growing a second insulating film over the entire surface after removing the photoresist film.
【００１０】0010
【作用】本発明においては、下地デバイスを含む半導体
基板上に第１の絶縁膜を成長させた後、この第１の絶縁
膜上に多結晶シリコン膜を成長させ、この多結晶シリコ
ン膜を選択的にエッチングする。そして、前記多結晶シ
リコン膜の少なくとも高抵抗素子形成予定領域上にフォ
トレジスト膜をパターン形成し、このフォトレジスト膜
をマスクとして全面に不純物をイオン注入することによ
り、前記多結晶シリコン膜の配線領域の抵抗値を低下さ
せる。従来法では、このイオン注入時のマスクとしてエ
ッチングによりパターン形成した窒化膜を使用している
が、本発明方法では上述のフォトレジスト膜をマスクと
して使用するため、窒化膜の形成工程及びそのエッチン
グ工程を削減できると共に、配線領域となる前記多結晶
シリコン膜がエッチングされてしまうことを防止できる
。このため、配線領域の多結晶シリコン膜の抵抗値を十
分に低減することができる。一方、エッチング工程の削
減に伴って前記多結晶シリコン膜６を薄膜化することが
できるので、高抵抗素子をより一層高抵抗化することが
できる。[Operation] In the present invention, after a first insulating film is grown on a semiconductor substrate including an underlying device, a polycrystalline silicon film is grown on this first insulating film, and this polycrystalline silicon film is selected. etching. Then, a photoresist film is patterned on at least a region where a high resistance element is to be formed in the polycrystalline silicon film, and impurity ions are implanted into the entire surface using this photoresist film as a mask, thereby forming a wiring region of the polycrystalline silicon film. decreases the resistance value of In the conventional method, a nitride film patterned by etching is used as a mask during this ion implantation, but in the method of the present invention, the above-mentioned photoresist film is used as a mask, so the nitride film formation process and its etching process are In addition, it is possible to prevent the polycrystalline silicon film that will become the wiring region from being etched. Therefore, the resistance value of the polycrystalline silicon film in the wiring region can be sufficiently reduced. On the other hand, since the polycrystalline silicon film 6 can be made thinner due to the reduction in the number of etching steps, the resistance of the high resistance element can be further increased.
【００１１】次に、前記フォトレジスト膜を除去した後
、全面に第２の絶縁膜を成長させる。このようにイオン
注入時のマスクを除去した後に新たに第２の絶縁膜を設
けるため、この第２の絶縁膜を平坦化することができ、
この第２の絶縁膜に段差が形成されることを防止できる
。従って、前記第２の絶縁膜上に金属配線を形成しても
、この金属配線が断線することを防止できる。Next, after removing the photoresist film, a second insulating film is grown on the entire surface. In this way, since the second insulating film is newly provided after removing the mask during ion implantation, this second insulating film can be flattened.
It is possible to prevent a step from being formed in the second insulating film. Therefore, even if a metal wiring is formed on the second insulating film, the metal wiring can be prevented from being disconnected.
【００１２】なお、高濃度にイオン注入されたフォトレ
ジスト膜は通常のエッチング液で除去することが困難で
あるが、硝酸及び硫酸を主成分とする液体を使用するこ
とにより容易に除去することができる。このため、前記
フォトレジスト膜は硝酸及び硫酸を主成分とする液体を
使用して除去することが好ましい。[0012] Although it is difficult to remove a photoresist film into which ions have been implanted at a high concentration with a normal etching solution, it can be easily removed by using a liquid containing nitric acid and sulfuric acid as main components. can. Therefore, it is preferable to remove the photoresist film using a liquid containing nitric acid and sulfuric acid as main components.
【００１３】[0013]
【実施例】次に、本発明の実施例について添付の図面を
参照して説明する。Embodiments Next, embodiments of the present invention will be described with reference to the accompanying drawings.
【００１４】図１乃至図３は本発明の実施例に係る高抵
抗素子を有する半導体装置の製造方法を工程順に示す断
面図である。FIGS. 1 to 3 are cross-sectional views showing, in order of steps, a method for manufacturing a semiconductor device having a high resistance element according to an embodiment of the present invention.
【００１５】先ず、図１に示すように、半導体基板１の
表面にＮ型拡散層２及び酸化膜３を選択的に形成し、こ
のＮ型拡散層２及び酸化膜３を含む半導体基板１上に多
結晶シリコン膜４を選択的に形成する。このようにして
下地デバイスを形成した後、全面に膜厚が例えば約２０
００Åの酸化膜５を成長させる。次に、Ｎ型拡散層２の
直上域の酸化膜５を選択的に除去した後、全面に膜厚が
例えば約１０００Åの多結晶シリコン膜６を成長させる
。次いで、この多結晶シリコン膜６上にフォトリソグラ
フィ技術を使用してフォトレジスト膜（図示せず）をパ
ターン形成し、このフォトレジスト膜をマスクとして多
結晶シリコン膜６をエッチングした後、このフォトレジ
スト膜を除去する。First, as shown in FIG. 1, an N-type diffusion layer 2 and an oxide film 3 are selectively formed on the surface of a semiconductor substrate 1. A polycrystalline silicon film 4 is selectively formed. After forming the base device in this way, the film thickness is about 20 mm over the entire surface, for example.
An oxide film 5 with a thickness of 0.00 Å is grown. Next, after selectively removing the oxide film 5 directly above the N-type diffusion layer 2, a polycrystalline silicon film 6 having a thickness of, for example, about 1000 Å is grown over the entire surface. Next, a photoresist film (not shown) is patterned on this polycrystalline silicon film 6 using photolithography technology, and the polycrystalline silicon film 6 is etched using this photoresist film as a mask. Remove membrane.
【００１６】次に、図２に示すように、フォトリソグラ
フィ技術を使用して、多結晶シリコン膜６の少なくとも
高抵抗素子形成予定領域上に膜厚が例えば約 １．０μ
ｍのフォトレジスト膜７をパターン形成する。次に、フ
ォトレジスト膜７をマスクとして、イオン注入量が例え
ば約１０１５ｃｍ−３の条件にて全面にリンをイオン注
入することにより、多結晶シリコン膜６の配線領域の抵
抗値を高抵抗素子形成予定領域の抵抗値に比して十分に
低下させる。その後、硝酸及び硫酸を主成分とする液体
を使用してフォトレジスト膜７を除去する。Next, as shown in FIG. 2, using photolithography technology, at least the region where the high resistance element is to be formed of the polycrystalline silicon film 6 is coated with a film thickness of about 1.0 μm, for example.
A photoresist film 7 of m is patterned. Next, using the photoresist film 7 as a mask, phosphorus is ion-implanted into the entire surface at an ion implantation amount of, for example, about 1015 cm-3, thereby changing the resistance value of the wiring region of the polycrystalline silicon film 6 to form a high-resistance element. The resistance value is sufficiently lowered compared to the resistance value of the planned area. Thereafter, the photoresist film 7 is removed using a liquid containing nitric acid and sulfuric acid as main components.
【００１７】次に、図３に示すように、全面に膜厚が例
えば約２０００Åの酸化膜８を成長させ、この酸化膜８
上に膜厚が例えば約５０００ÅのＢＰＳＧ膜を成長させ
た後、窒素雰囲気中で約 ８５０℃の温度で３０分間熱
処理する。次に、多結晶シリコン膜６に到達するコンタ
クト穴（図示せず）を形成した後、全面に厚さが例えば
約 １．０μｍの金属配線１０を被着する。次に、この
金属配線１０上にフォトレジスト膜（図示せず）をパタ
ーン形成し、このフォトレジスト膜をマスクとして金属
配線１０をエッチングした後、このフォトレジスト膜を
除去する。このようにして高抵抗素子を有する半導体装
置を製造することができる。Next, as shown in FIG. 3, an oxide film 8 having a thickness of, for example, about 2000 Å is grown over the entire surface.
After a BPSG film having a thickness of, for example, about 5000 Å is grown thereon, heat treatment is performed at a temperature of about 850° C. for 30 minutes in a nitrogen atmosphere. Next, after forming a contact hole (not shown) reaching the polycrystalline silicon film 6, a metal wiring 10 having a thickness of, for example, about 1.0 μm is deposited over the entire surface. Next, a photoresist film (not shown) is patterned on the metal wiring 10, the metal wiring 10 is etched using the photoresist film as a mask, and then the photoresist film is removed. In this way, a semiconductor device having a high resistance element can be manufactured.
【００１８】本実施例によれば、多結晶シリコン膜６の
配線領域へのイオン注入時のマスクとして、従来の窒化
膜の替わりにフォトレジスト膜７を使用するので、窒化
膜の形成工程及びそのエッチング工程を削減することが
できる。このため、配線領域となる多結晶シリコン膜６
がエッチングされてしまうことを防止でき、多結晶シリ
コン膜６の配線領域の抵抗値を十分に低減することがで
きる。また、エッチング工程の削減に伴って多結晶シリ
コン膜６を薄膜化することができるので、高抵抗素子を
より一層高抵抗化することができる。更に、フォトレジ
スト膜７を除去した後、全面に酸化膜８を設けるため、
従来のようにイオン注入時のマスクとして使用した窒化
膜をそのまま層間絶縁膜として使用する場合とは異なっ
て、酸化膜８を平坦化することができ、この酸化膜８に
段差が形成されることを防止できる。従って、ＢＰＳＧ
膜９上に形成された金属配線１０が断線することを防止
できる。According to this embodiment, the photoresist film 7 is used instead of the conventional nitride film as a mask during ion implantation into the wiring region of the polycrystalline silicon film 6, so that the process of forming the nitride film and its Etching steps can be reduced. Therefore, the polycrystalline silicon film 6 which becomes the wiring region
It is possible to prevent the polycrystalline silicon film 6 from being etched, and the resistance value of the wiring region of the polycrystalline silicon film 6 can be sufficiently reduced. Further, since the polycrystalline silicon film 6 can be made thinner by reducing the number of etching steps, the high resistance element can be made to have even higher resistance. Furthermore, after removing the photoresist film 7, an oxide film 8 is provided on the entire surface.
Unlike the conventional case in which the nitride film used as a mask during ion implantation is directly used as an interlayer insulating film, the oxide film 8 can be flattened, and steps are not formed in the oxide film 8. can be prevented. Therefore, BPSG
It is possible to prevent the metal wiring 10 formed on the film 9 from being disconnected.
【００１９】[0019]
【発明の効果】以上説明したように本発明によれば、第
１の絶縁膜上に設けた多結晶シリコン膜の少なくとも高
抵抗素子形成予定領域上にフォトレジスト膜をパターン
形成し、このフォトレジスト膜をマスクとして全面に不
純物をイオン注入するから、従来法における窒化膜の形
成工程及びそのエッチング工程を削減できると共に、配
線領域となる多結晶シリコン膜がエッチングされること
を防止できる。このため、配線領域の多結晶シリコン膜
の抵抗値を十分に低減することができる。また、前記フ
ォトレジスト膜を除去した後、全面に第２の絶縁膜を設
けるから、従来のようにイオン注入時のマスクとして使
用した窒化膜をそのまま層間絶縁膜として使用する場合
とは異なって、前記第２の絶縁膜を平坦化することがで
き、この第２の絶縁膜に段差が形成されることを防止で
きる。従って、第２の絶縁膜上に金属配線を形成しても
、この金属配線が断線することを防止できる。As explained above, according to the present invention, a photoresist film is patterned on at least the region where a high resistance element is to be formed of a polycrystalline silicon film provided on a first insulating film, and the photoresist film is Since impurity ions are implanted into the entire surface using the film as a mask, it is possible to eliminate the nitride film formation step and its etching step in the conventional method, and to prevent the polycrystalline silicon film that will become the wiring region from being etched. Therefore, the resistance value of the polycrystalline silicon film in the wiring region can be sufficiently reduced. In addition, since the second insulating film is provided on the entire surface after removing the photoresist film, unlike the conventional case in which the nitride film used as a mask during ion implantation is directly used as an interlayer insulating film, The second insulating film can be planarized, and formation of a step on the second insulating film can be prevented. Therefore, even if a metal wiring is formed on the second insulating film, the metal wiring can be prevented from being disconnected.
【図１】本発明の実施例に係る高抵抗素子を有する半導
体装置の製造方法の一工程を示す断面図である。FIG. 1 is a cross-sectional view showing one step in a method for manufacturing a semiconductor device having a high resistance element according to an embodiment of the present invention.
【図２】本発明の実施例に係る高抵抗素子を有する半導
体装置の製造方法の一工程を示す断面図である。FIG. 2 is a cross-sectional view showing one step in a method for manufacturing a semiconductor device having a high resistance element according to an embodiment of the present invention.
【図３】本発明の実施例に係る高抵抗素子を有する半導
体装置の製造方法の一工程を示す断面図である。FIG. 3 is a cross-sectional view showing one step in a method for manufacturing a semiconductor device having a high resistance element according to an embodiment of the present invention.
【図４】従来の高抵抗素子を有する半導体装置の製造方
法の一工程を示す断面図である。FIG. 4 is a cross-sectional view showing one step in a conventional method for manufacturing a semiconductor device having a high resistance element.
【図５】従来の高抵抗素子を有する半導体装置の製造方
法の一工程を示す断面図である。FIG. 5 is a cross-sectional view showing one step in a conventional method for manufacturing a semiconductor device having a high resistance element.
【図６】従来の高抵抗素子を有する半導体装置の製造方
法の一工程を示す断面図である。FIG. 6 is a cross-sectional view showing one step in a conventional method for manufacturing a semiconductor device having a high resistance element.
１；半導体基板 ２；Ｎ型拡散層 ３，５，８；酸化膜 ４，６；多結晶シリコン膜 ７；フォトレジスト膜 ９；ＢＰＳＧ膜 １０；金属配線 １１；窒化膜 1; Semiconductor substrate 2; N type diffusion layer 3,5,8; Oxide film 4, 6; Polycrystalline silicon film 7; Photoresist film 9; BPSG film 10; Metal wiring 11; Nitride film
Claims (2)
後全面に第１の絶縁膜を成長させる工程と、この第１の
絶縁膜上に多結晶シリコン膜を成長させる工程と、この
多結晶シリコン膜を選択的にエッチングする工程と、前
記多結晶シリコン膜の少なくとも高抵抗素子形成予定領
域上にフォトレジスト膜をパターン形成しこのフォトレ
ジスト膜をマスクとして全面に不純物をイオン注入する
工程と、前記フォトレジスト膜を除去した後全面に第２
の絶縁膜を成長させる工程とを有することを特徴とする
高抵抗素子を有する半導体装置の製造方法。1. A step of growing a first insulating film on the entire surface after forming a base device on a semiconductor substrate, a step of growing a polycrystalline silicon film on the first insulating film, and a step of growing a polycrystalline silicon film on the first insulating film. a step of selectively etching the polycrystalline silicon film, a step of patterning a photoresist film on at least a region where a high resistance element is to be formed of the polycrystalline silicon film, and implanting impurity ions into the entire surface using the photoresist film as a mask; After removing the resist film, a second layer is applied to the entire surface.
1. A method for manufacturing a semiconductor device having a high resistance element, the method comprising: growing an insulating film.
を主成分とする液体を使用して除去することを特徴とす
る請求項１に記載の高抵抗素子を有する半導体装置の製
造方法。2. The method of manufacturing a semiconductor device having a high resistance element according to claim 1, wherein the photoresist film is removed using a liquid containing nitric acid and sulfuric acid as main components.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12856791A JPH04329664A (en) | 1991-04-30 | 1991-04-30 | Manufacture of semiconductor device using high resistance element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12856791A JPH04329664A (en) | 1991-04-30 | 1991-04-30 | Manufacture of semiconductor device using high resistance element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04329664A true JPH04329664A (en) | 1992-11-18 |
Family
ID=14987952
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12856791A Pending JPH04329664A (en) | 1991-04-30 | 1991-04-30 | Manufacture of semiconductor device using high resistance element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04329664A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5324290A (en) * | 1976-08-18 | 1978-03-06 | Nec Corp | Semiconductor device |
| JPS63222431A (en) * | 1987-03-11 | 1988-09-16 | Mitsubishi Electric Corp | Photoresist removing apparatus |
| JPS6445158A (en) * | 1987-07-31 | 1989-02-17 | Samsung Semiconductor Tele | Manufacture of high resistance polycrystalline silicon |
-
1991
- 1991-04-30 JP JP12856791A patent/JPH04329664A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5324290A (en) * | 1976-08-18 | 1978-03-06 | Nec Corp | Semiconductor device |
| JPS63222431A (en) * | 1987-03-11 | 1988-09-16 | Mitsubishi Electric Corp | Photoresist removing apparatus |
| JPS6445158A (en) * | 1987-07-31 | 1989-02-17 | Samsung Semiconductor Tele | Manufacture of high resistance polycrystalline silicon |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0076105A2 (en) | Method of producing a bipolar transistor | |
| JP3388590B2 (en) | Method of manufacturing diode or Schottky clamp transistor | |
| JPH0473296B2 (en) | ||
| JPS6252950B2 (en) | ||
| JPH04329664A (en) | Manufacture of semiconductor device using high resistance element | |
| JPS6220711B2 (en) | ||
| JPS60258964A (en) | Manufacture of semiconductor device | |
| KR0134858B1 (en) | Fabrication method of contact hole in semiconductor device | |
| JPS63275181A (en) | Manufacture of semiconductor device | |
| JPH07230968A (en) | Manufacture of semiconductor device | |
| JP2674964B2 (en) | Method for manufacturing semiconductor device | |
| JPH0554263B2 (en) | ||
| JPH0475346A (en) | Manufacture of semiconductor device | |
| JP2790514B2 (en) | Method for manufacturing semiconductor device | |
| JP2745946B2 (en) | Method for manufacturing semiconductor integrated circuit | |
| JP2659798B2 (en) | Semiconductor device | |
| JPH0319224A (en) | Manufacture of semiconductor device | |
| JPH0420256B2 (en) | ||
| JPH0136709B2 (en) | ||
| JPS5968950A (en) | Manufacture of semiconductor device | |
| JPH0314256A (en) | Manufacture of semiconductor device | |
| KR19980048967A (en) | Method for manufacturing field effect transistor | |
| JPH06188259A (en) | Manufacture of semiconductor device | |
| JPH01251658A (en) | Manufacture of semiconductor device | |
| JPS61147550A (en) | Manufacture of semiconductor device |