JPH04329474A - Method and device for checking logic circuit - Google Patents

Abstract

PURPOSE:To efficiently execute a trace information by providing priority to trace information while paying attention to a fact that the position of using a pin is different for a designer and there is the important pin to be surely inspected in the case of a circuit check. CONSTITUTION:Design data and inspection data such as the logical constitution of a circuit, trace pin information to the pins of respective equipments on a logical path to be checked, the priority of the pin and link information of each pin, etc., is inputted to a design standard check means 35 and based on those data, the equipment to be a standard is retrieved. Then, the check is started from the equipment, the circuit is checked by tracing a signal transmission network, which is prepared by connecting the input/output pins of respective equipments connecting the standard pin, to the objective pin, the number of times for using the pins of respective equipments existent on a signal transmission route from the standard equipment to the objective pin is counted, the link information of the pins is edited again while considering the number of times for using pins and the priority, and this re-edited link information is registered again.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit checking method for automatically tracking and confirming the connection state of logic elements during the logic circuit design stage of a computer.

0002

2. Description of the Related Art Recent developments in LSIs and printed circuit boards have led to higher integration, and it is essential to check design standards for the structure of printed boards, and there is also a demand for shorter processing times. A design standard check in the conventional logic circuit design stage is performed on an LSI (integrated circuit) 1 as shown in FIG.
This is a test to check whether each component 2 is in a specified connection state. As shown in FIG. 13, the design standard check system includes an LSI logical design data file 3 provided on a magnetic disk, etc., an LSI internal macro library 4,
A design standard data table 5, a design standard checking means 6, and an output means 7 for outputting the check results in a list format.
It consists of In this tracing process, a certain A
When focusing on part 2 (referred to as macro A), Fig. 14 (a
), backtrace information (information on input pins whose output pin side should be affected, see FIGS. 14(b) and (c)) is stored in trace table 4a in correspondence with output pins 09 and 10 of component A 2. , 4b. Based on the trace information of output pins 09 and 10, input pins 01 to 08
The connection state of components B or C, . . . located on each signal path leading to the target input pins 20, 21 (FIG. 16) of the LSI was checked. The backtrace information for output pins 09 and 10 of component 2 has the pin names trace table 4a and 4b.
Since they are arranged sequentially within the input pins, input pins 01,...,0
The method is to follow the net of 8. As shown in FIG. 15, in the backtrace process, LSI design data is loaded into the design standard checking means 6 (st1). Then, a design standard check process is executed (st2). In this process, as shown in FIG.
Search for ■Input information held by output pin 09 of macro A (
Read the backtrace information) from the macro library 4, search for the input pin 05 that connects to the output pin 09, determine the output pin 12 of macro C that connects to that input pin 05, and do the same from that output pin 12 to the input side. 1) Find the input pin 20 of the target LSI. Thereafter, after the design standard check process is completed, the output means 7 outputs the determination result (st3).

0003

[Problem to be Solved by the Invention] In the conventional design standard check described above, each macro A and B during actual LSI design
, C, ... are not used in order starting from input pin 01. For example, S designers often use input pin 04, but P
Designers often use input pin 05, and the pin positions of macros A, B, C, etc. often differ depending on the designer's preference, and even if the pins are used only a few times, it is difficult to check the circuit. There are also input pins that must be investigated. Furthermore, when macros are connected in multiple stages in the check path, many pin combinations can be considered until the target input pin 20 is reached, which takes a lot of processing time. When checking the signal path, input pins 01 to 08 are searched in order from the top, so a useless pin search is performed to find the connection with the necessary input pins 01,... or 08. Therefore, there was a problem in that the processing required a lot of time.

The present invention is intended to solve the above-mentioned problems in the conventional technology, and focuses on the fact that pin usage positions differ depending on the designer and that there are important pins that must be investigated when checking the circuit, and trace information An object of the present invention is to provide a logic circuit checking method and a logic circuit checking device that efficiently perform tracing processing by giving priority to the logic circuits.

[0005]

[Means for Solving the Problems] In order to enable efficient tracing processing, the present invention includes a method for checking a logic circuit, in which the design standard checking means 35 includes information on the logical configuration of the circuit, and each component on the logical path to be checked. Input design data and inspection data such as trace pin information for pins of a component, priority of that pin, link information of each pin, etc., search for standard components based on these data,
Starting from that component, trace the signal transmission network created by connecting the input/output pins of each component connected to the target input/output pin to check the circuit, and then check the circuit from the reference component to the above. Count the number of pin usages of each component that exists on the signal transmission path leading to the target input/output pin, re-edit the pin link information taking into account the number of pin usages and the priority mentioned above, and then re-edit the pin link information. The feature is that the edited link information is re-registered.

In addition, in the logic circuit checking device, as shown in FIG. 1, there is a logic design data file 31 that stores data on the logic design of the integrated circuit, and various files including pin information for each component in the integrated circuit. a component information library 32 that stores data on pin usage for each component in the integrated circuit; a design standard data file 33 that stores data necessary for design standard checking including pin usage priorities for each component in the integrated circuit; a component trace link data file 34 that stores link information for tracing the logic circuit according to a specified connection state of each component, a design criterion check means 35 that executes a design criterion check, and the design criterion. The present invention is characterized in that it includes an output means 36 for outputting the check results.

[0007]

[Operation] With this configuration, in the logic circuit checking method, during the design standard check, the logic configuration of the circuit, the trace pin information for the pins of each component on the logical path to be checked, and the priority of that pin. , design data such as link information for each pin and data necessary for inspection are input into the design standard checking means 35, and based on these data, starting from the standard component, the target input/output pin is reached. Check the circuit by tracing the signal transmission network created by connecting the input/output pins of each component to which the component connects, and check the signal from the reference component to the target input/output pin. Count the number of pin usages of each component on the transmission path, and after checking the circuit, re-edit the pin link information by taking into account the number of pin usages and the priority, and use this re-edited link information. By re-registering, the circuit will be checked based on the new link information from next time onwards. This allows traces to be searched in order of the most frequently used pins, making it possible to efficiently trace the signal transmission network and shorten processing time.

[0008] In addition, in the logic circuit checking device, data on the logic design of the integrated circuit is stored in advance in the logic design data file 31, and various data including pin information for each component in the integrated circuit are stored in the component information library 32. The design standard data file 33 contains the data necessary for the design standard check, including pin usage priorities for each component in the integrated circuit, and the component trace link data file 34
stores link information so that a prescribed logic circuit can be traced by the specified connection state of each component at the time of design standard checking, and inputs each information to the design standard checking means 35 at the time of design standard checking. The circuit is checked, new pin information obtained as a result of the circuit check is added to update the link information in an order that facilitates pin retrieval, and the result of the design standard check is outputted from the output means 36. This makes it easy to always search for pins in circuit checks, and allows design criteria checks to be processed in a short time.

[0009]

[Embodiment] In the following embodiment of the present invention, a case where a link data file is provided will be explained.

FIG. 2 is a diagram showing the configuration of one embodiment. Here, 41 is an LSI logical design data file, which is the same as the conventional one. Reference numeral 42 denotes a macro library within the LSI, which stores back trace information for output pins of each macro (component), pin code information for each pin, and the like. Reference numeral 43 is a design standard data file, which stores various design standard data, priorities for each pin code, and the like. A macro trace link data file 44 stores link data necessary for backtracing each macro. Design standard checking means 45 searches each signal path according to the contents of the macro trace link data file 44, outputs the results from the output means 46, and updates the contents of the macro trace link data file 44. The pin codes provided in the LSI macro library 42 are stored in the pin code table 42a in association with the pin name for each macro, as shown in FIG. 3(a). The design standard data file 43 includes, as shown in FIG. 3(b),
A priority table 43a is provided to store priorities corresponding to pin codes. The contents of the macro trace link data file 44 are summarized in the link table 44a as shown in FIG. 4 by putting together the link information for the output pins for each macro at the stage of checking the design standards, and by organizing the link information for the output pins for each macro in the stage of checking the design standards. The arrangement is changed according to the priority of each pin. This processing is executed only when the link file is initialized, and thereafter, when the macro appears, tracing processing is executed using the changed link information.

As shown in FIG. 5, the process flowchart according to the embodiment configured as described above is as follows: First, LSI design data is loaded into the design standard checking means 45 (st11).
). It is checked whether there is data in the macro trace link data file 44 (st12). If there is no data, Figure 6
Macro trace link data file 4 as shown in
The contents of step 4 initialize the link data at the output pin of the macro that checks the design criteria. For example, among the trace pin information and link table 44a for the output pin 09 of macro A, the table number of the trace table 44a is initialized by being linked as trace information in ascending order from the top (st13). If there is data in the macro trace link data file 44, its initialization step st
Jump over 13. Then, a design standard check process is executed. In this process, (1) macro A, which serves as a criterion, is searched. (2) Backtracing the signal path from the output pin 09 to the input side using the macro trace link data file 44 that has been changed according to the importance of the pin. For example, Figure 7
As shown in the figure, trace pin information 42b-09 at the time of backtracing of output pin 09 of macro A and a link table 44a-0 containing a serial number of the table corresponding to the trace pin information 42b-09 are shown.
9. Trace pin information and link table 44a-11 for macro B's output pins 11 and 12, trace pin information 42b-13 and link table 44a-13 for macro C's output pin 13, etc., for each macro. Assuming that backtrace information is included, as shown in Figure 8, when backtracing from output pin 09 of macro A, it is connected to output pin 12 of macro B via input pin 05, and input Output pin of macro C via pin 15... and traced back one after another to the LSI
to the input pin 20 of. Then, as a result of the backtrace, (1) the target input pin (input pin 20) is discovered. Then, count the number of pin uses in each macro passed through to find the desired input pin during the backtrace,
It is stored in the usage count table 44b. For example, as shown in FIG. 9, usage count tables 44b-A, 44b-B, 4 for each input pin such as macro A, macro B, macro C, etc.
4b-C, etc., the counted values are stored as shown. It is processed by following each step (st14
). Macro trace link data file 44 after processing
Determines the pin order in the backtrace of input pins for each macro based on the number of pin uses and importance (priority) of the pin, and relinks and reregisters the contents of the link data stored in . do. For example, considering the pin usage count of macro A shown in FIG. 9 and the pin priority of macro A shown in FIG. 3, the pin order in the input pin backtrace as shown in FIG. The one with the highest number of times is given a higher rank, and the pin order is determined in descending order of priority, and the links are re-attached and re-registered and updated in the link table 44a as shown in FIG. 11 (st15). . Then, the determination result is outputted by the output means 46 (st16).

[0012] In this embodiment, by providing the link table 44a in which each pin 01, . Trace processing time can be shortened and design standard checks can be made more efficient. Furthermore, the link table 44a stored in the macro trace link data file 44 can express the link status of the pins used by each macro, which vary depending on the designer. The state is searched and checks for the designer's preferred logic circuit can be executed efficiently in a short time.

[0013]

[Effects of the Invention] As described above, in the logic circuit checking method of the present invention, traces are searched in order from the most frequently used pins, so that the signal transmission network can be traced efficiently and the processing can be carried out. By making it possible to shorten the time, the processing at the time of checking the design standards can be shortened, and the efficiency of checking the design standards can be improved. In addition, since the pin usage status of each part is different depending on the designer, by inputting the link information, it is possible to trace the signal transmission network that matches the pin usage status of the designer's preference from the beginning.
Design standards can be checked efficiently in a short time for the circuit configuration of the designer's preference.

Further, in the logic circuit checking device, the design standard checking means 35 efficiently checks the circuit according to the link information based on the data prepared in advance, including the link information of the component trace link data file 34, and performs the circuit check. By taking into account the new pin usage information obtained as a result, the link information can be updated in an order that makes it easier to search for pins, making it easier to always search for input/output pins of signal transmission networks during circuit checks. but,
Since the design standard check can be easily performed starting from the pins that are used frequently, the design standard check can be processed in a short time. Further, by setting the link information according to the pin usage state desired by the designer and storing it in the component trace link data file 34, it is possible to efficiently check the design standards of the circuit configuration desired by the designer in a short time.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle configuration of the present invention.

FIG. 2 is a system configuration diagram of the embodiment.

FIG. 3 is a storage area explanatory diagram showing importance (priority) in the embodiment.

FIG. 4 is an explanatory diagram of stored contents showing changes in the contents of a link table in the embodiment.

FIG. 5 is a flowchart of backtrace processing in the embodiment.

FIG. 6 is a storage area explanatory diagram showing the initial state of the contents of each file in the embodiment.

FIG. 7 is a trace information explanatory diagram showing backtrace link data in the embodiment.

FIG. 8 is a trace explanatory diagram showing an example of back tracing in the embodiment.

FIG. 9 is a storage area explanatory diagram showing a usage count table of each macro in the embodiment.

[Fig. 10] Pin order after processing in the example (macro A
) is an explanatory diagram of link processing.

FIG. 11 is an explanatory diagram of link processing showing the link order (macro A) after re-registration in the embodiment.

FIG. 12 is a configuration explanatory diagram showing an LSI used for circuit checking.

FIG. 13 is a configuration diagram of a conventional design standard checking system.

FIG. 14 is a configuration explanatory diagram showing input/output pins and trace information during a conventional circuit check.

FIG. 15 is a conventional backtrace processing flowchart.

FIG. 16 is a process explanatory diagram showing a conventional backtrace.

[Explanation of symbols]

31 Logical design data file 32 Part information library 33 Design standard data file 34 Part trace link data file 35 Design standard checking means 36 Output means

Claims (2)

[Claims] 1. Design standard checking means (35) includes design data such as the logical configuration of the circuit, trace pin information for pins of each component on the logical path to be checked, priority of the pin, link information of each pin, etc. and inspection data, search for standard parts based on those data, start from that part, and create a signal transmission network by connecting the input/output pins of each part to which that part connects. Check the circuit by tracing all the way to the desired input/output pin, count the number of pin usages of each component on the signal transmission path from the reference component to the target input/output pin, and A method for checking a logic circuit, comprising re-editing link information of a pin in consideration of the number of pin uses and the priority, and re-registering the re-edited link information. 2. A logic design data file (31) that stores data on the logic design of an integrated circuit, and a component information library (32) that stores various data including pin information for each component in the integrated circuit. A design criteria data file (
33), a component trace link data file (34) that stores link information to enable the specified logic circuit to be traced by the specified connection state of each component during design standard checking, and execution of design standard check. A logic circuit checking device comprising a design standard checking means (35) for checking the design standard and an output means (36) for outputting the result of the design standard check.