JPH0432923A - Sequence circuit - Google Patents

Abstract

PURPOSE:To put this sequence circuit in operation in an optional state by providing a selector at the input of a state storing flip-flop group and providing a selector control circuit which switches the selection of a selector with a sate loading pulse. CONSTITUTION:When the sequence circuit in an optional state is put in opera tion, state values p1 - pq are set and the state loading pulse pl is generated. The selector control circuit 4 selects signals inputted to input terminals b1 - pq, i.e. state values p1 - pq as selector switching signals inputted to a terminal S before and after the latch pulse of an oscillator 1 by the generation of the state load pulse pl. Consequently, the state values p1 - pq of the state storage D flip-flop group 2 are loaded at the next rise of the oscillator 1 right after the generation of the state load pulse pl, and the sequence circuit starts operat ing in the state. Consequently, the sequence circuit can be put in operation in the optional state.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a sequential circuit that can operate from any state.

[Conventional technology]

FIG. 3 is a bronch system diagram showing a conventional sequential circuit. In the figure, 1 is an oscillator, 2 is a state memory D that uses the output of oscillator 1 as a clock input, and stores the state of the sequential circuit.
Flip-flop 7 group, 3 is state memory 97971707
Outputs Q1 to Qq of group 1 and 2 and various input signals x1 to xn
This is a decoder which inputs the following state signals w1 to wq as outputs to the input terminals of the state memory D flip-flop group 2, and outputs various output signals z1 to zm.

Next, the operation will be explained. Sequential circuit uses reset signal R
The operation starts from the time when level 3 changes from level rLJ to rHJ. When the reset signal changes from rLJ to rHJ, the output signals Ql, Q2 .
..., Qq are all rLJ, so the inputs vl, v2, ..., vq of the decoder 3 are all rLJ. Various input signals xi, x2. ..., xn, the next state signals wl, w are sent from the decoder 3.
2 .・
..., zm is output. In this manner, the next state is latched in the state storage D flip-flop group 2 by various input signals by the launch pulse of the oscillator 1, and output signals are generated one after another, thereby operating as a sequential circuit.

[Problem to be solved by the invention]

Since the conventional sequential circuit is configured as described above, the outputs Q1, Q2 .
..., there was a problem in that all Qq had to be operated from the rLJ state, and it was impossible to operate from any arbitrary state.

The present invention has been made in view of these points, and its purpose is to obtain a sequential circuit that can be operated from any state.

[Means to solve the problem]

In order to achieve this object, the sequential circuit according to the present invention is provided with a selector at the input of the state memory D flip-flop, and a selector control circuit for controlling the selection signal of the selector.

[Effect]

In the sequential circuit according to the present invention, the state record +! When an arbitrary state is loaded into the selector provided at the input of the iD flip-flop group, the selector is switched by the selector control circuit, the arbitrary state is latched in the state memory 079777071 group, and operation starts from the arbitrary state.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a sequential circuit according to the present invention. In the same figure, ■ is an oscillator that generates pulses, 2 is a state memory 0797770 that uses the output of oscillator 1 as the input of the latch pulse, and stores the state of the sequential circuit.
71 group, 3 is state memory 079777071 output Q of group 2
1, Q2゜..., Qq, and various input signals x1 to xn as inputs, and outputs the next state signal wlxwq and various output signals zl to zm. A decoder 4 is connected to the oscillator 1 and outputs the state load pulse pf. A selector control circuit 5 which generates a selector switching signal before and after the latch pulse of the oscillator 1 immediately after the occurrence of the latching pulse of the oscillator 1 inputs the output of the selector control circuit 4 as a switching signal and outputs the next state signal W1-. ．． This is a selector that inputs wq and state values p1 to pq and selects either the next state signal or state value.

Next, the operation will be explained. Sequential circuit beam cent signal R
The operation starts when 3 changes from rLJ to rHJ.

When the reset signal R3 changes from rLJ to "H", Ql, Q2 . ...
, Qq are all rLJ, so the input V of the decoder 3
LVL...vq is all rLJ. Various input signals x1x2. . . , xn, the decoder 3 outputs the next state signals wl, w2 . ...,
When wq is output and the state load pulse p1 is not generated, the output of the selector control circuit 4 is the terminal a of the selector 5.
lla2. ..., input signal to aq, that is, Wl
, W2. ..., wq are selected, and at the rising edge of oscillator 1, the next state signals wl, w2 . ..., wq are stored, and at the same time, the decoder 3 outputs various output signals 21, 22 . ...
, zn are output.

In this way, when the state load pulse is not generated, the launch pulse of the oscillator l is used to store the state 0797770.
The next state signal is latched in the 71 group 2 by various input signals, output signals are generated one after another, and the circuit operates as a sequential circuit.

When operating a sequential circuit from an arbitrary state, the state value p1.
p2. ..., set pq, state load pulse p
generate l. Due to the generation of the state load pulse pl,
By the selector control circuit 4, the selector switching signal input to the terminal S before and after the latch pulse of the oscillator 1 is changed to the state values pi, p2 . ..., to select pq, the state value pt is stored in the state memory 079772071 group 2 at the rising edge of the oscillator 1 next to the generation of the state load pulse p1.

P2. ..., pq are loaded, and the sequential circuit operates from that state.

Note that the state value p1. of the above embodiment. p2. ...pq
and state load pulse p! ! may be generated by the CPU. The block system is shown in FIG. 2 as a second embodiment. In the figure, reference numerals 6 indicate input terminals bl, b2 . ...bq to terminal D1. D2.
..., CPU connected to the Dq-connected data bus, 7
are terminals AI, A2 . of CPU6. ..., Ar-connected address bus and 10. Memory space division is signal terminal I
A decoder connected to the O/M and assigning a sequential circuit to a certain space of the CPU 6, 8 is a write pulse terminal W of the CPU 6
R and decoder 7, state load pulse pI
! This is a state load pulse generation circuit that generates.

Next, the operation when operating the sequential circuit from an arbitrary state will be explained. The CPU 6 sends an arbitrary state value pi to the data bus.
, p2. ..., when pq is set and a write command is executed to the allocated space, the state load pulse p1 is generated from the state load pulse p1 generation circuit 8 by the output of the decoder 7, and the latch pulse of the oscillator 1 is generated. Before and after input terminals bl, b2 . ..., bq is selected, the state values p1, p2 are stored in the state memory 079772071 group 2 at the next rising edge of the oscillator 1 after the state load pulse p1 is generated.
．． ..., pq are loaded, and the sequential circuit operates from that state.

In the above embodiment, a D flip-flop was used for state storage, but the same effect can be obtained by using other flip-flops.

〔Effect of the invention〕

As explained above, the present invention provides a selector at the input of the state memory clip-flop group, and a selector control circuit that switches the selection of the selector using a state load pulse, so that an arbitrary state can be transferred to the state memory flip-flop group. Since it can be memorized, it has the effect of providing a sequential circuit that can operate from any state.

[Brief explanation of drawings]

FIG. 1 is a block system diagram showing one embodiment of a sequential circuit according to the present invention, FIG. 2 is a block system diagram showing another embodiment of the invention, and FIG. 3 is a block system diagram showing a conventional sequential circuit. be. 1... Oscillator, 2... State memory 079772071
group, 3... decoder, 4... selector control circuit,
5...Selector. Figure 1

Claims (1)

[Claims] An oscillator that generates pulses, a state memory flip-flop group that uses the output of this oscillator as a clock input, and receives the output of this state memory flip-flop group and various input signals as input, and outputs the next state signal and various output signals. a decoder, a selector control circuit connected to the oscillator and generating a selector switching signal before and after a latch pulse of the oscillator immediately after the generation of a state load pulse; and inputting the output of the selector control circuit as a switching signal. A sequential circuit comprising: a selector for selecting either a next state signal or a state value of the decoder.