JPH04324430A - Semiconductor device, production of semiconductor device, insulator substrate for mounting semiconductor device, and liquid crystal display device - Google Patents
Semiconductor device, production of semiconductor device, insulator substrate for mounting semiconductor device, and liquid crystal display deviceInfo
- Publication number
- JPH04324430A JPH04324430A JP3095279A JP9527991A JPH04324430A JP H04324430 A JPH04324430 A JP H04324430A JP 3095279 A JP3095279 A JP 3095279A JP 9527991 A JP9527991 A JP 9527991A JP H04324430 A JPH04324430 A JP H04324430A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- insulating substrate
- semiconductor device
- conductive film
- resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 107
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000012212 insulator Substances 0.000 title claims abstract description 16
- 239000004065 semiconductor Substances 0.000 title claims description 29
- TXUICONDJPYNPY-UHFFFAOYSA-N (1,10,13-trimethyl-3-oxo-4,5,6,7,8,9,11,12,14,15,16,17-dodecahydrocyclopenta[a]phenanthren-17-yl) heptanoate Chemical compound C1CC2CC(=O)C=C(C)C2(C)C2C1C1CCC(OC(=O)CCCCCC)C1(C)CC2 TXUICONDJPYNPY-UHFFFAOYSA-N 0.000 claims description 15
- 229910021626 Tin(II) chloride Inorganic materials 0.000 claims description 15
- 235000011150 stannous chloride Nutrition 0.000 claims description 15
- 239000001119 stannous chloride Substances 0.000 claims description 15
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 8
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 8
- 235000019441 ethanol Nutrition 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 claims description 4
- 239000010408 film Substances 0.000 abstract description 70
- 239000011521 glass Substances 0.000 abstract description 18
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 abstract description 17
- 229910001887 tin oxide Inorganic materials 0.000 abstract description 17
- 239000010409 thin film Substances 0.000 abstract description 16
- 239000000428 dust Substances 0.000 abstract description 2
- 229910052738 indium Inorganic materials 0.000 abstract description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 abstract description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 6
- 230000005611 electricity Effects 0.000 description 6
- 230000003068 static effect Effects 0.000 description 6
- 239000011651 chromium Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000006460 hydrolysis reaction Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000007598 dipping method Methods 0.000 description 2
- RHZWSUVWRRXEJF-UHFFFAOYSA-N indium tin Chemical compound [In].[Sn] RHZWSUVWRRXEJF-UHFFFAOYSA-N 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229920000742 Cotton Polymers 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 230000007062 hydrolysis Effects 0.000 description 1
- 230000003301 hydrolyzing effect Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
- Elimination Of Static Electricity (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、半導体装置，半導体装
置の製造方法及び半導体装置を搭載するための絶縁体基
板に関し、特に帯電を防止した絶縁体基板を用いた半導
体装置，半導体装置の製造方法，半導体装置を搭載する
ための絶縁体基板及び液晶表示装置に関する。[Field of Industrial Application] The present invention relates to a semiconductor device, a method for manufacturing a semiconductor device, and an insulating substrate for mounting a semiconductor device, and particularly to a semiconductor device and the manufacturing of a semiconductor device using an insulating substrate that prevents charging. The present invention relates to a method, an insulator substrate for mounting a semiconductor device, and a liquid crystal display device.
【０００２】0002
【従来の技術】絶縁物基板を用いた半導体装置の代表的
なものとしては、アクティブマトリクス液晶ディスプレ
イに用いられる薄膜トランジスタアレイ基板があり、以
下これを例にとって説明する。薄膜トランジスタアレイ
基板は、ディスプレイ表示動作のため可視光に対して透
明なガラス，石英等の基板に半導体膜，ゲート絶縁膜，
金属配線等を形成して、製造される。図５は、従来の薄
膜トランジスタアレイ基板の断面図である。ガラス基板
４１上にクロム（Ｃｒ）等によりゲート領域２３が形成
され、その後、ゲート絶縁膜２４，動作層となるアモル
ファスシリコン２５，ソース・ドレイン領域２６，表示
電極２７を形成することにより、薄膜トランジスタアレ
イがガラス基板４１上に形成されていた。2. Description of the Related Art A typical semiconductor device using an insulating substrate is a thin film transistor array substrate used in an active matrix liquid crystal display, which will be explained below as an example. A thin film transistor array substrate is a substrate made of glass, quartz, etc. that is transparent to visible light for display operation, and a semiconductor film, gate insulating film, etc.
It is manufactured by forming metal wiring and the like. FIG. 5 is a cross-sectional view of a conventional thin film transistor array substrate. A gate region 23 is formed of chromium (Cr) or the like on a glass substrate 41, and then a gate insulating film 24, an amorphous silicon 25 serving as an active layer, a source/drain region 26, and a display electrode 27 are formed, thereby forming a thin film transistor array. was formed on the glass substrate 41.
【０００３】0003
【発明が解決しようとする課題】この従来の薄膜トラン
ジスタアレイ基板では、基板が絶縁体であるため種々の
工程によって発生する静電気により、ガラス基板４１が
帯電する。ガラス基板４１は帯電すると集塵効果をもつ
。従って、薄膜トランジスタアレイ基板は製造工程で基
板に種々の異物を吸着することになり、これが、製品歩
留りを低下させる、という問題点があった。In this conventional thin film transistor array substrate, since the substrate is an insulator, the glass substrate 41 is charged by static electricity generated in various steps. When the glass substrate 41 is charged, it has a dust collecting effect. Therefore, the thin film transistor array substrate has a problem in that various foreign substances are attracted to the substrate during the manufacturing process, which lowers the product yield.
【０００４】0004
【課題を解決するための手段】本発明によれば、絶縁体
基板の少なくとも片面にトランジスタを搭載する半導体
装置において、トランジスタと絶縁体基板の間に高抵抗
の導電膜が形成されている半導体装置が得られる。[Means for Solving the Problems] According to the present invention, in a semiconductor device in which a transistor is mounted on at least one side of an insulating substrate, a high-resistance conductive film is formed between the transistor and the insulating substrate. is obtained.
【０００５】また、本発明によれば、少なくとも片面に
トランジスタを搭載した絶縁体基板を有する液晶表示装
置において、トランジスタと絶縁体基板との間に高抵抗
の導電膜が形成されている液晶表示装置が得られる。Further, according to the present invention, there is provided a liquid crystal display device having an insulating substrate on which a transistor is mounted on at least one side, in which a high-resistance conductive film is formed between the transistor and the insulating substrate. is obtained.
【０００６】基板がガラス，樹脂等の絶縁体である場合
、静電気が発生し、帯電してしまうことが多い。帯電し
た基板は、製造工程において種々の異物を吸着し、製品
歩留りを低下させる。この帯電を防止するためには、導
電性のある膜で基板を覆えばよい。この時、導電性のあ
る膜の比抵抗が小さいと、導電性が高く、基板上に搭載
するトランジスタ間が短絡したり、隣接トランジスタ間
で信号が漏洩したりすることになるので、被覆する導電
性のある膜は高抵抗である必要がある。[0006] When the substrate is an insulator such as glass or resin, static electricity is generated and the substrate is often charged. Charged substrates attract various foreign substances during the manufacturing process, reducing product yield. In order to prevent this charging, the substrate may be covered with a conductive film. At this time, if the specific resistance of the conductive film is low, the conductivity is high and short circuits may occur between transistors mounted on the substrate or signal leakage between adjacent transistors. The membrane needs to have high resistance.
【０００７】また、基板の帯電を防止するためには、基
板全体を高抵抗被膜で覆うことが望ましいが、トランジ
スタ等を全く搭載しない部分に関しては異物を吸着して
も問題は無いので、基板の少なくともトランジスタ等を
搭載する部分が高抵抗被膜で覆われていればよい。In addition, in order to prevent the board from being charged, it is desirable to cover the entire board with a high-resistance film, but since there is no problem even if foreign matter is attracted to areas where no transistors or the like are mounted, It is only necessary that at least a portion where a transistor or the like is mounted is covered with a high-resistance film.
【０００８】更に本発明によれば上記絶縁体基板及び上
記高抵抗の導電膜が透明である半導体装置や液晶表示装
置が得られる。Further, according to the present invention, there can be obtained a semiconductor device or a liquid crystal display device in which the above-mentioned insulating substrate and the above-mentioned high-resistance conductive film are transparent.
【０００９】高抵抗の導電膜として、酸化スズや、酸化
スズにインジウムを混合して製造したもの等を用いた場
合、透明な被膜を得ることができる。絶縁体基板が透明
で、高抵抗の導電膜も透明であれば、全体として透明な
基板を得ることが出来、液晶ディスプレイ，イメージセ
ンサ等に有効である。[0009] When using tin oxide or a material prepared by mixing indium with tin oxide as a high-resistance conductive film, a transparent film can be obtained. If the insulating substrate is transparent and the high-resistance conductive film is also transparent, it is possible to obtain a transparent substrate as a whole, which is effective for liquid crystal displays, image sensors, etc.
【００１０】次に、本発明によれば、上記導電膜の面抵
抗の値が８０ＭΩ／□以上１０ＧΩ／□以下である半導
体装置や液晶表示装置が得られる。Next, according to the present invention, there can be obtained a semiconductor device or a liquid crystal display device in which the conductive film has a sheet resistance value of 80 MΩ/□ or more and 10 GΩ/□ or less.
【００１１】薄膜トランジスタアレイ基板等の場合、導
電膜上に形成されるゲートライン間のリークによる信号
の漏洩が問題となる。図４は薄膜トランジスタアレイ基
板におけるゲートドライバー，配線系の等価回路のモデ
ル図である。Ｍ番目とＭ＋１番目のゲートドライバーを
想定したものであり、ＲＨ は、本発明による高抵抗被
膜による抵抗値を表している。今、Ｍ番目のゲート配線
ＧＭ の電圧をＶＯＦＦ ，Ｍ＋１番目のゲート配線Ｇ
Ｍ＋１ の電圧をＶＯＮとすると、点Ａにおける内電圧
ＶＡ は、 ＶＡ ＝ＶＯＦＦ ＋（ＲＥ ＋ＲＧ
）・（ＶＯＮ−ＶＯＦＦ ） ／（２Ｒ
Ｅ ＋２ＲＧ ＋ＲＨ ）
…（１）となる。隣接
するゲート電圧ＶＯＮの影響をなくすには、ＲＥ ＋Ｒ
Ｇ ＜＜ＲＨ とすればよい。点Ａの電圧ＶＡ の誤差
は、小さい程好ましいが、通常０．５Ｖ程度迄は、悪影
響を及ぼすことはない。また、典型的にはＶＯＮ＝１５
Ｖ，ＶＯＦＦ ＝−５Ｖ程度である。点Ａの電圧ＶＡ
の誤差をＶＡ ′とすると（１）式より
ＶＡ ′＝（ＲＥ ＋ＲＧ ）・（ＶＯＮ−ＶＯＦ
Ｆ ） ／（２ＲＥ ＋２ＲＧ ＋ＲＨ
）
…（２）１０インチ級液晶ディスプレイに用
いられる薄膜トランジスタアレイでは、通常ＲＧ ＝１
０ＫΩ，ＲＥ ＝１ＫΩ程度である。（２）式にＶＯＮ
＝１５，ＶＯＦＦ ＝−５，ＲＧ ＝１０，ＲＥ ＝１
，ＶＡ ＜０．５を代入すると、 ＲＨ ＞４００Ｋ
Ω
…（３）抵
抗値ＲＨ は、面抵抗をρ，隣接するゲートの対向長を
Ｌ，隣接するゲートのスペース長をＷとすると、 Ｒ
Ｈ ＝ρ・Ｗ／Ｌ
…（４）と表わされる。一般にＷ＝１００μｍ，Ｌ
＝２０ｍｍであるから、（３），（４）式から、ρ＞８
０ＭΩ／□であれば、隣接ゲートライン間の信号の漏洩
は実用上問題のないものとなる。In the case of thin film transistor array substrates and the like, signal leakage due to leakage between gate lines formed on a conductive film poses a problem. FIG. 4 is a model diagram of an equivalent circuit of a gate driver and wiring system on a thin film transistor array substrate. This assumes Mth and M+1st gate drivers, and RH represents the resistance value due to the high resistance film according to the present invention. Now, turn the voltage of M-th gate wiring GM to VOFF, M+1st gate wiring G
If the voltage of M+1 is VON, the internal voltage VA at point A is VA = VOFF + (RE +RG
)・(VON-VOFF) /(2R
E +2RG +RH)
...(1). To eliminate the influence of the adjacent gate voltage VON, RE +R
It is sufficient to set G <<RH. It is preferable that the error in the voltage VA at point A be as small as possible, but normally up to about 0.5V will not have any adverse effect. Also, typically VON=15
V, VOFF = about -5V. Voltage VA at point A
Let VA' be the error of
F ) /(2RE +2RG +RH
)
...(2) In a thin film transistor array used in a 10-inch class liquid crystal display, RG = 1
0KΩ, RE = about 1KΩ. In equation (2), VON
=15, VOFF =-5, RG =10, RE =1
, VA <0.5, then RH >400K
Ω
...(3) The resistance value RH is as follows, where ρ is the sheet resistance, L is the opposing length of adjacent gates, and W is the space length of adjacent gates.
H = ρ・W/L
...It is expressed as (4). Generally W=100μm, L
= 20 mm, so from equations (3) and (4), ρ>8
If it is 0 MΩ/□, there will be no practical problem with signal leakage between adjacent gate lines.
【００１２】また、通常のガラス基板は１００ＧΩ／□
程度であり、ガラス基板に微小の水分が付着したものの
面抵抗が１０ＧΩ／□程度である。静電気の帯電を防止
するには、１０ＧΩ／□よりは小さい抵抗値の膜が望ま
しい。[0012] Also, a normal glass substrate has a resistance of 100GΩ/□
The surface resistance of a glass substrate with a small amount of water attached is about 10 GΩ/□. In order to prevent static electricity charging, a film with a resistance value smaller than 10 GΩ/□ is desirable.
【００１３】したがって、絶縁体基板に被着する導電膜
は、８０ＭΩ／□以上１０ＧΩ／□以下であることが望
ましい。静電気の帯電防止と、導電性によるトランジス
タへの悪影響との兼ね合いから、特に好ましくは、１０
０ＭΩ／□〜１０ＧΩ／□程度の導電膜が望ましい。[0013] Therefore, the conductive film deposited on the insulating substrate preferably has a resistance of 80 MΩ/□ or more and 10 GΩ/□ or less. Particularly preferably 10
A conductive film of about 0 MΩ/□ to 10 GΩ/□ is desirable.
【００１４】更に、本発明によれば、塩化第１スズ（Ｓ
ｎＣｌ２ ）を溶解した溶液に絶縁体基板を浸漬する工
程と、その後絶縁体基板を水蒸気を含む雰囲気で処理し
、加水分解する工程と、その後絶縁体基板の少なくとも
片面にトランジスタを搭載する工程とを含む半導体装置
の製造方法が得られる。塩化第１スズの加水分解により
、酸化スズの被膜を形成することができるものである。Furthermore, according to the present invention, stannous chloride (S
nCl2), a step of immersing the insulating substrate in a solution containing nCl2), a step of treating the insulating substrate in an atmosphere containing water vapor to hydrolyze it, and a step of mounting a transistor on at least one side of the insulating substrate. A method for manufacturing a semiconductor device including the method is obtained. A tin oxide film can be formed by hydrolyzing stannous chloride.
【００１５】更に、本発明によれば、エチルアルコール
に塩化第１スズ（ＳｎＣｌ２ ）を０．１ｇ／ｌ以上１
２．５ｇ／ｌ以下になるように溶解し、絶縁体基板を浸
漬する工程と、絶縁体基板を水蒸気を含む雰囲気で、１
００℃〜１５０℃で１時間〜１２時間熱処理し、加水分
解する工程と、絶縁体基板を更に２５０℃〜４００℃で
１時間〜３時間熱処理する工程と、絶縁体基板の少なく
とも片面にトランジスタを搭載する工程とを含む半導体
装置の製造方法がより好ましくは得られる。Furthermore, according to the present invention, stannous chloride (SnCl2) is added to ethyl alcohol in an amount of 0.1 g/l or more.
1 step of dissolving the insulating substrate to a concentration of 2.5 g/l or less and immersing the insulating substrate in an atmosphere containing water vapor.
A step of heat treating at 00° C. to 150° C. for 1 hour to 12 hours and hydrolysis, a step of further heat treating the insulating substrate at 250° C. to 400° C. for 1 hour to 3 hours, and forming a transistor on at least one side of the insulating substrate. More preferably, a method for manufacturing a semiconductor device including a step of mounting is obtained.
【００１６】エチルアルコールに塩化第１スズを溶解し
たものに基板を浸漬し、加水分解反応を起こさせると、
酸化スズ被膜が得られる。その後再び熱処理をするのは
、酸化スズ被膜の硬化性，密着性を高めるためである。
酸化スズ被膜の面抵抗は、エチルアルコールに溶解する
塩化第１スズの濃度に反比例する。１ｇ／ｌの濃度では
、１ＧΩ／□程度の酸化スズ被膜が得られ、５ｇ／ｌの
濃度では２００ＭΩ／□となる。したがって、前述の８
０ＭΩ／□〜１０ＧΩ／□の範囲の面抵抗の導電膜を得
るためには、エチルアルコール中の塩化第１スズの濃度
を０．１ｇ／ｌ以上１２．５ｇ／ｌ以下になるように設
定すれば良いことになる。また、導電膜としてより望ま
しい１ＧΩ／□程度の酸化スズ膜を得るためには、エチ
ルアルコール中の塩化第１スズの濃度を１ｇ／ｌ程度に
設定すれば良いことになる。When the substrate is immersed in a solution of stannous chloride in ethyl alcohol to cause a hydrolysis reaction,
A tin oxide film is obtained. The reason why heat treatment is performed again after that is to improve the hardenability and adhesion of the tin oxide film. The sheet resistance of a tin oxide film is inversely proportional to the concentration of stannous chloride dissolved in ethyl alcohol. At a concentration of 1 g/l, a tin oxide film of about 1 GΩ/□ is obtained, and at a concentration of 5 g/l, it is 200 MΩ/□. Therefore, the above 8
In order to obtain a conductive film with a sheet resistance in the range of 0 MΩ/□ to 10 GΩ/□, the concentration of stannous chloride in ethyl alcohol should be set to 0.1 g/l or more and 12.5 g/l or less. That's a good thing. Further, in order to obtain a tin oxide film having a thickness of about 1 GΩ/□, which is more desirable as a conductive film, the concentration of stannous chloride in ethyl alcohol should be set to about 1 g/l.
【００１７】更に、本発明によれば、少なくとも片面に
半導体装置を搭載するための絶縁体基板において、面抵
抗の値が８０ＭΩ／□以上１０ＧΩ／□以下である導電
膜で覆われている絶縁体基板が得られる。また、絶縁体
基板及び導電膜が透明である絶縁体基板が得られる。あ
らかじめ高抵抗の導電膜で覆われた絶縁体基板を製造し
ておけば、その後トランジスタ等を搭載して、半導体装
置を製造する際に有効である。また、その絶縁体基板及
び高抵抗の導電膜が透明であれば、液晶ディスプレイ，
イメージセンサ等の基板として有効である。絶縁体基板
の導電膜は、必らずしも全面が覆われている必要は無く
、絶縁体基板の側面（切断面）や角等、半導体装置を搭
載しない部分の絶縁体基板が露出していても何ら問題は
無い。Further, according to the present invention, in an insulating substrate for mounting a semiconductor device on at least one side, an insulator is covered with a conductive film having a sheet resistance value of 80 MΩ/□ or more and 10 GΩ/□ or less. A substrate is obtained. Moreover, an insulating substrate in which the insulating substrate and the conductive film are transparent can be obtained. If an insulating substrate covered with a high-resistance conductive film is manufactured in advance, it is effective when mounting transistors and the like thereon to manufacture a semiconductor device. In addition, if the insulating substrate and the high-resistance conductive film are transparent, the liquid crystal display
It is effective as a substrate for image sensors, etc. The conductive film on the insulator substrate does not necessarily have to cover the entire surface, and the parts of the insulator substrate where the semiconductor device is not mounted are exposed, such as the sides (cut surfaces) and corners of the insulator substrate. There is no problem with that.
【００１８】[0018]
【実施例】次に本発明について図面を参照して説明する
。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.
【００１９】図１は本発明による半導体装置を搭載する
ための絶縁体基板の一実施例を示す断面図である。FIG. 1 is a sectional view showing an embodiment of an insulating substrate for mounting a semiconductor device according to the present invention.
【００２０】ガラス基板１上に酸化スズ（ＳｎＯ）被膜
２を後に述べるディップ法によって形成し、しかる後に
薄膜トランジスタの製造工程をへて、薄膜トランジスタ
アレイ基板を製造する。A tin oxide (SnO) film 2 is formed on a glass substrate 1 by a dipping method, which will be described later, and then goes through a thin film transistor manufacturing process to manufacture a thin film transistor array substrate.
【００２１】酸化スズ被膜２は以下の手順で形成される
。エチルアルコール１ｌに塩化第一スズ（ＳｎＣｌ２
）を１ｇ溶解し、ガラス基板１を浸漬する。ガラス基板
１を引き上げた後、水蒸気（Ｈ２ Ｏ）を含んだ雰囲気
で１００℃で１時間の熱処理を行なうと（５）式に示す
加水分解反応がおこり、基板に酸化スズ被膜２が形成さ
れる。The tin oxide film 2 is formed by the following procedure. Stannous chloride (SnCl2) is added to 1 liter of ethyl alcohol.
) is dissolved and the glass substrate 1 is immersed in the solution. After pulling up the glass substrate 1, heat treatment is performed at 100° C. for 1 hour in an atmosphere containing water vapor (H2O), and a hydrolysis reaction shown in equation (5) occurs, forming a tin oxide film 2 on the substrate. .
【００２２】
ＳｎＣｌ２ ＋Ｈ２ Ｏ → ＳｎＯ＋２ＨＣ
ｌ …（５）
この後、３００℃でさらに２時間熱処理を行なうことに
より、酸化スズ被膜２をガラス基板１に焼き付け、膜の
硬化性・密着性を高める。酸化スズ被膜２の面抵抗は、
ディップ液の塩化第一スズ濃度によって制御でき、上述
した１ｇ／ｌの濃度では、１ＧΩ／□程度の面抵抗の被
膜となる。被膜面抵抗は上に形成される素子の動作に影
響を与えないためには、十分に大きい必要がある。[0022] SnCl2 +H2O → SnO+2HC
l...(5)
Thereafter, heat treatment is further performed at 300° C. for 2 hours to bake the tin oxide film 2 onto the glass substrate 1 and improve the hardenability and adhesion of the film. The sheet resistance of the tin oxide film 2 is
It can be controlled by the stannous chloride concentration of the dipping liquid, and at the above-mentioned concentration of 1 g/l, a film with a sheet resistance of about 1 GΩ/□ is obtained. The film surface resistance needs to be sufficiently large so as not to affect the operation of the elements formed thereon.
【００２３】薄膜トランジスタ（図２）はガラス基板１
１上に高抵抗被膜１２を形成した後、次の製造工程をへ
て製造される。第１にＣｒ膜厚１４００オングストロー
ムをスパッタリング法によって形成し、パターン化する
ことによりゲート電極３を形成する。次にゲート絶縁膜
４，動作層５，オーミックコンタクト層５′となる窒化
シリコン膜，ノンドープアモルファスシリコン膜，リン
ドープアモルファスシリコン膜をそれぞれ４００ｎｍ，
３００ｎｍ，５０ｎｍプラズマＣＶＤ法で成膜する。次
にトランジスタ以外の部分のアモルファスシリコン膜を
除去し、クロム（Ｃｒ）を２００ｎｍスパッタリングで
成膜し、パターン化してドレイン・ソース電極６を形成
する。次に透明導電膜ＩＴＯ（Ｉｎｄｉｕｍ Ｔｉｎ
Ｏｘｉｄｅ）を８００ｎｍスパッタリング法によって成
膜し、パターン化することにより、表示電極７を形成し
、トランジスタ不要部のリンドープアモルファスシリコ
ンをエッチング除去する。最後に素子保護膜９として、
窒化シリコン膜４００ｎｍをプラズマＣＶＤ法で成膜し
、接続端子部の窒化シリコン膜をエッチング除去するこ
とにより薄膜トランジスタが形成される。The thin film transistor (FIG. 2) has a glass substrate 1
After forming the high resistance coating 12 on the substrate 1, the next manufacturing process is performed. First, a Cr film having a thickness of 1400 angstroms is formed by sputtering and patterned to form the gate electrode 3. Next, a silicon nitride film, a non-doped amorphous silicon film, and a phosphorus-doped amorphous silicon film, which will become the gate insulating film 4, active layer 5, and ohmic contact layer 5', are each coated with a thickness of 400 nm.
Films of 300 nm and 50 nm are formed by plasma CVD. Next, the amorphous silicon film in areas other than the transistors is removed, and a 200 nm film of chromium (Cr) is formed by sputtering and patterned to form drain/source electrodes 6. Next, a transparent conductive film ITO (Indium Tin)
The display electrode 7 is formed by forming a film of 800 nm (800 nm thick oxide) by sputtering and patterning it, and the phosphorus-doped amorphous silicon in the unnecessary portion of the transistor is removed by etching. Finally, as the element protection film 9,
A thin film transistor is formed by depositing a silicon nitride film with a thickness of 400 nm by plasma CVD and etching away the silicon nitride film at the connection terminal portion.
【００２４】液晶表示装置（図３）は、以下の工程によ
って製造されるこの薄膜トランジスタが多数形成された
基板２１と、対向基板３１のおのおのに液晶分子を配向
させるためのポリイミド膜：１００ｎｍを印刷し、ラビ
ングとよばれる綿布等でポリイミド膜を特定の方向にす
る処理を行なう。次にガラスファイバー，ガラス球等を
スペーサとして、２つの基板を約５μｍの間隙をもって
貼り合わせ、その中に液晶１０を封入する。The liquid crystal display device (FIG. 3) is produced by printing a polyimide film (100 nm thick) for aligning liquid crystal molecules on each of the substrate 21 on which a large number of thin film transistors are formed and the counter substrate 31, which are manufactured by the following steps. , a process called rubbing is performed to align the polyimide film in a specific direction using cotton cloth or the like. Next, the two substrates are bonded together with a gap of about 5 μm using glass fibers, glass bulbs, etc. as spacers, and the liquid crystal 10 is sealed therein.
【００２５】このガラス基板の両側に偏光板１０１を貼
り付けることにより液晶表示装置が製造される。A liquid crystal display device is manufactured by pasting polarizing plates 101 on both sides of this glass substrate.
【００２６】[0026]
【発明の効果】以上説明したように、本発明は絶縁体基
板とトランジスタの間に高抵抗の導電膜が形成されてい
ることにより、基板の帯電を防止し、製造工程で基板に
種々の異物が吸着するのを防止し、製品歩留りを向上さ
せるという効果を有する。As explained above, the present invention prevents the substrate from being charged by forming a high-resistance conductive film between the insulating substrate and the transistor, and prevents various foreign substances from forming on the substrate during the manufacturing process. This has the effect of preventing adsorption of substances and improving product yield.
【００２７】更に、絶縁体基板及び導電膜を透明にする
ことにより、静電気の発生を防止した光を透過する絶縁
体基板が得られ、液晶ディスプレイ，センサー等に有効
である。Furthermore, by making the insulating substrate and the conductive film transparent, an insulating substrate that prevents generation of static electricity and transmits light can be obtained, which is effective for liquid crystal displays, sensors, and the like.
【００２８】また、導電膜の面抵抗を８０ＭΩ／□以上
１０ＧΩ／□以下に設定することにより、導電膜を介し
て絶縁体基板上に搭載したトランジスタに悪影響を及ぼ
すことなく基板上に静電気の帯電も防止出来るという効
果を有する。Furthermore, by setting the sheet resistance of the conductive film to 80 MΩ/□ or more and 10 GΩ/□ or less, static electricity can be charged on the substrate without adversely affecting the transistor mounted on the insulating substrate through the conductive film. It also has the effect of preventing
【００２９】更にまた、本発明の製造方法によれば、面
抵抗が有効に制御された導電膜を形成することが可能で
ある。Furthermore, according to the manufacturing method of the present invention, it is possible to form a conductive film whose sheet resistance is effectively controlled.
【００３０】更に８０ＭΩ／□以上１０ＧΩ／□以下の
導電膜で覆われた絶縁体基板を形成することにより、基
板上の静電気の帯電を防止し、半導体装置及び液晶表示
装置の製造等に有効である。Furthermore, by forming an insulating substrate covered with a conductive film of 80 MΩ/□ or more and 10 GΩ/□ or less, static electricity on the substrate can be prevented, which is effective for manufacturing semiconductor devices and liquid crystal display devices. be.
【図１】本発明による半導体装置を搭載するための絶縁
体基板の一実施例を示す断面図である。FIG. 1 is a sectional view showing an embodiment of an insulating substrate for mounting a semiconductor device according to the present invention.
【図２】本発明による半導体装置の一実施例を示す断面
図である。FIG. 2 is a sectional view showing an embodiment of a semiconductor device according to the present invention.
【図３】本発明による液晶表示装置の一実施例を示す断
面図である。FIG. 3 is a sectional view showing an embodiment of a liquid crystal display device according to the present invention.
【図４】ゲートドライバー，配線系の等価回路のモデル
図である。FIG. 4 is a model diagram of an equivalent circuit of a gate driver and wiring system.
【図５】従来の薄膜トランジスタアレイ基板の断面図で
ある。FIG. 5 is a cross-sectional view of a conventional thin film transistor array substrate.
１，１１，２１，３１，４１ ガラス基板２，１
２，２２ 酸化スズ膜
３，２３ ゲート領域
４，２４ ゲート絶縁膜
５，２５ アモルファスシリコン５′ オ
ーミックコンタクト層
６，２６ ソース・ドレイン領域７，２７
表示電極
８ 保護膜
９ ゲートドライバー
１０ 液晶
１１ 偏光板
ＧＭ Ｍ番目のゲート配線
ＧＭ＋１ Ｍ＋１番目のゲート配線ＲＥ
ドライバー出力インピーダンスＲＧ 配線
抵抗
ＲＨ 本発明による高抵抗被膜による抵抗値Ｌ
隣接するゲートの対向長1, 11, 21, 31, 41 Glass substrate 2, 1
2, 22 Tin oxide film 3, 23 Gate region 4, 24 Gate insulating film 5, 25 Amorphous silicon 5' Ohmic contact layer 6, 26 Source/drain region 7, 27
Display electrode 8 Protective film 9 Gate driver 10 Liquid crystal 11 Polarizing plate GM M-th gate wiring GM+1 M+1-th gate wiring RE
Driver output impedance RG Wiring resistance RH Resistance value L due to the high resistance coating according to the present invention
Opposing length of adjacent gates
Claims (10)
ジスタを搭載する半導体装置において、前記トランジス
タと前記絶縁体基板の間に高抵抗の導電膜が形成されて
いることを特徴とする半導体装置。1. A semiconductor device in which a transistor is mounted on at least one side of an insulating substrate, characterized in that a high-resistance conductive film is formed between the transistor and the insulating substrate.
であることを特徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the insulating substrate and the conductive film are transparent.
上１０ＧΩ／□以下であることを特徴とする請求項１記
載の半導体装置。3. The semiconductor device according to claim 1, wherein the conductive film has a sheet resistance of 80 MΩ/□ or more and 10 GΩ/□ or less.
縁体基板を浸漬する工程と、その後前記絶縁体基板を水
蒸気を含む雰囲気で処理し、加水分解する工程と、その
後前記絶縁体基板の少なくとも片面に前記トランジスタ
を搭載する工程とを含むことを特徴とする半導体装置の
製造方法。4. A step of immersing the insulating substrate in a solution containing stannous chloride, followed by treating the insulating substrate in an atmosphere containing water vapor to hydrolyze it, and then immersing the insulating substrate in a solution containing stannous chloride. A method of manufacturing a semiconductor device, comprising the step of mounting the transistor on at least one surface.
．１ｇ／ｌ以上１２．５ｇ／ｌ以下になるように溶解し
、前記絶縁体基板を浸漬する工程と、前記絶縁体基板を
水蒸気を含む雰囲気中で、１００℃〜１５０℃で熱処理
し、加水分解する工程と、前記絶縁体基板を更に２５０
℃〜４００℃で熱処理する工程と、前記絶縁体基板の少
なくとも片面に前記トランジスタを搭載する工程とを含
むことを特徴とする半導体装置の製造方法。Claim 5: Add 0 stannous chloride to ethyl alcohol.
．． A step of dissolving the insulating substrate to a concentration of 1 g/l to 12.5 g/l and immersing the insulating substrate, and heat-treating the insulating substrate at 100° C. to 150° C. in an atmosphere containing water vapor to hydrolyze the insulating substrate. The insulator substrate is further heated for 250 minutes.
A method for manufacturing a semiconductor device, comprising the steps of heat treatment at a temperature of .degree. C. to 400.degree. C., and mounting the transistor on at least one side of the insulating substrate.
るための絶縁体基板において、前記絶縁体基板の前記片
面には面抵抗の値が８０ＭΩ／□以上１０ＧΩ／□以下
である前記導電膜が設けられていることを特徴とする絶
縁体基板。6. In an insulating substrate for mounting a semiconductor device on at least one side, the conductive film having a sheet resistance value of 80 MΩ/□ or more and 10 GΩ/□ or less is provided on the one side of the insulating substrate. An insulator substrate characterized by:
であることを特徴とする請求項６記載の絶縁体基板。7. The insulator substrate according to claim 6, wherein the insulator substrate and the conductive film are transparent.
した絶縁体基板を有する液晶表示装置において、前記ト
ランジスタと前記絶縁体基板との間に高抵抗の導電膜が
形成されていることを特徴とする液晶表示装置。8. A liquid crystal display device having an insulating substrate with a transistor mounted on at least one side, characterized in that a high-resistance conductive film is formed between the transistor and the insulating substrate. Device.
であることを特徴とする請求項８記載の液晶表示装置。9. The liquid crystal display device according to claim 8, wherein the insulating substrate and the conductive film are transparent.
以上１０ＧΩ／□以下であることを特徴とする請求項８
記載の液晶表示装置。10. The conductive film has a sheet resistance of 80 MΩ/□.
Claim 8 characterized in that it is greater than or equal to 10 GΩ/□ or less.
The liquid crystal display device described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3095279A JPH04324430A (en) | 1991-04-25 | 1991-04-25 | Semiconductor device, production of semiconductor device, insulator substrate for mounting semiconductor device, and liquid crystal display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3095279A JPH04324430A (en) | 1991-04-25 | 1991-04-25 | Semiconductor device, production of semiconductor device, insulator substrate for mounting semiconductor device, and liquid crystal display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04324430A true JPH04324430A (en) | 1992-11-13 |
Family
ID=14133340
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3095279A Pending JPH04324430A (en) | 1991-04-25 | 1991-04-25 | Semiconductor device, production of semiconductor device, insulator substrate for mounting semiconductor device, and liquid crystal display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04324430A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003279942A (en) * | 2002-03-19 | 2003-10-02 | Seiko Epson Corp | Optoelectronic device, electronic apparatus and projection type display device |
| US7508033B2 (en) | 1998-04-24 | 2009-03-24 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device with diamond-like carbon film on backside of substrate |
-
1991
- 1991-04-25 JP JP3095279A patent/JPH04324430A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7508033B2 (en) | 1998-04-24 | 2009-03-24 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device with diamond-like carbon film on backside of substrate |
| JP2003279942A (en) * | 2002-03-19 | 2003-10-02 | Seiko Epson Corp | Optoelectronic device, electronic apparatus and projection type display device |
| US7209202B2 (en) | 2002-03-19 | 2007-04-24 | Seiko Epson Corporation | Electro-optic device, electronic instrument, and projection display |
| US7391491B2 (en) | 2002-03-19 | 2008-06-24 | Seiko Epson Corporation | Electro-optic device, electronic instrument, and projection display |
| US7911571B2 (en) | 2002-03-19 | 2011-03-22 | Seiko Epson Corporation | Electro-optic device, electronic instrument, and projection display |
| US8310635B2 (en) | 2002-03-19 | 2012-11-13 | Seiko Epson Corporation | Electro-optic device, electronic instrument, and projection display |
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