JPH043241A - Data processor - Google Patents

Abstract

PURPOSE:To restart the processing discontinued by an interruption at a high speed by inhibiting the substitution of a block of a process discontinued by an interruption in a shared cache memory. CONSTITUTION:The processor is provided with counters 104, 105 which are provided on each processor 2, 2', detect a sent interrupting signal and a return instruction from an interruption processing routine and inform them to a cache controller 107. Also, this processor is provided with the cache controller 107 having a table for storing the block number, the process number or the processor number of a process for using its block at every block of a shared cache memory 4. That is, the counters 104, 105 have a special value in the case the corresponding processors 2, 2' are executing an interruption processing, and the cache controller 107 refers to the process number or the processor number and limits the substitution to the corresponding block in the shared cache memory 4. In such a way, the processing discontinued by an interruption can be restarted at a high speed.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to a data processing system that performs high-speed processing using a plurality of processor modules, and particularly relates to a data processing system that performs high-speed processing that is interrupted by an interrupt. related to.

[Prior Art] FIG. 4 is a timing diagram when an interrupt occurs in a system equipped with four microprocessors.

Assume that an interrupt occurs at time tl. When an interrupt occurs, the microprocessor -1 that executes the interrupt process first is selected (P3 in FIG. 4). The process being executed by the next selected microprocessor (P3) (J3)
is interrupted and 2 interrupt processing (Ji) is executed. When the interrupt processing (Ji) is completed, the interrupted processing (J3) is resumed. Such a method is shown in 1, for example, Operating System Construction Method UIIIX Detailed Explanation - Structure Edition 1 (Akiaki Nakamura, 1986, pp, a+-64).

Further, FIG. 5 is a bronc diagram for a conventional data processing system. This figure is shown in Japanese Patent Application Laid-Open No. 51-IJ8349. In figure 7, (1) is a processor module (CPU l), (2) is a microprocessor (BPU), (501) is a table buffer,
(502) is an address array, (3) is a brave cache memory (buffer memory), (4) is a shared cache memory (common buffer memory), and (5) is a main memory.

Note that each processor module (1) has a main memory (5
) and shared canon - notes! /(4) are connected to both.

Next, the operation will be explained.

Memory addresses issued by the microprocessor (2) are converted from logical addresses to physical addresses in the table buffer (501). Each private cache memory (3) stores unique data for each corresponding microprocessor (2). The shared cache memory (4) stores areas commonly accessed by each processor module (1), such as a system management table. The microprocessor (2) sets the shared cache flag in the table buffer (501) to 1.
If the shared cache memory (4) is accessed, and if the shared cache and 2 flags are 0, the address array C50 is accessed.
2) to access the private memory (3) or main memory (5).

Interrupt processing will be explained using FIG. 6.

When an interrupt occurs in the system, a microprocessor that handles one interrupt is selected and a second interrupt signal is sent. The microprocessor that receives the interrupt signal
At the same time as the values of the program counter and stack pointer, the data and instructions in the private memory (3) are also saved to the main memory (5). It then uses the private cache memory to process the interrupt, and when the process is complete, writes the result to main memory. Then, in order to resume the processing that was interrupted by the second interrupt, the program columns and stack pointer values saved from the main memory, as well as the data and instructions in the private cache memory, are loaded into the private cache memory. In this system, the shared xenon memory (4) is configured to store data common to the processor modules, so it does not store data specific to interrupt processing.

If a higher-priority interrupt occurs during interrupt processing, the current state of the interrupt processing (program counter and stack pointer value, memory data and instructions) is stored in main memory. Then, the newly generated interrupt is processed.

[Problems to be Solved by the Invention] Since the conventional data processing/system is configured as described above, when one interrupt occurs, the contents of the private cache memory are replaced by the interrupt processing. There is a problem in that it takes time to read instructions and data from main memory when restoring a process that has been interrupted.

The present invention has been made to solve the above-mentioned problems, and aims to provide a data processing device that can quickly resume processing interrupted by one interrupt.1. I'm here.

Means for Solving the Problems The data processing device according to the present invention has a counter installed in each processor (which detects an incoming interrupt signal or a return command from an interrupt processing routine, and notifies it to a digital controller). The system is equipped with a Canon Yukon roller having a table for storing the block number and the process number or processor number of the process using the block for each block of memory.

1 action] In this invention, the counter is
However, if it is processing an interrupt, it has a special value,
Thereby, the controller refers to the process number or the processor number and limits replacement to the corresponding block in the shared cache memory.

:] Example 1 FIG. 1 is a block diagram showing one embodiment of the present invention.

This system Ii includes one or more processor modules, only two of which are shown (inside the dashed frame). Although FIG. 1 shows a case in which one processor module consists of two microprocessors, the same applies to a case in which it consists of three or more microprocessors. (1)-(5
) is the same as the conventional example. (2') and (3') are the same as (2) and (3), respectively. (+0
1) to (+03) are transnuvers, (104) and (1
05) is a counter, (106) is s5(-c, (1
07) is the cache controller, (1,08) is I1
0 controller (+09) is the system bus.

Note that the transceiver (101) is located between the bus that connects the private cache memory (3) and the shared memory (4), and the transceiver (102) connects the private cache memory (3') and the shared memory (4). Located between buses, transceivers (10
3) is shared cache memory (4) and system logs (
109) between the buses that connect them. Cache controller (10 → is 1 both counters (104), (1
05) Shared cache memory (4) and snooper (106)
) is connected. The snuba (106) is located between the system bus (109) and the bus connecting the shared cache memory (4). The 110 controller (10g) is connected to the system/N bus (+09).

As shown in Figure 2, the cache controller (10
7) consists of a data section, directory 1, microprocessor bus interface, and system bus interface. The data portion consists of data blocks held in the cache memory. The directory is 2
Consists of two identical address tags, valid bits, and process number. One of the two address tags is used for microprocessor cache access (called the processor address array), and the other is used for the system bus (1
09) It is used for the above invalidation signal and data access request (referred to as shadow address array). The shadow address array sends a signal to the processor address array only when the system bus (109) h is invalidated (No. 8) or a data access request is cached. A valid bit is provided for each cache block and determines the validity (set) of the block. The block number is a new part of this patent.

It shows which process each block is used by.

Next, the operation will be explained.

Each microprocessor accesses a corresponding private cache memory to perform processing (microprocessor (2) accesses private cache memory (3), microprocessor (2') accesses private cache memory (3')).

The private cache memory uses a write-through type, so the private cache memory (3)
, (3') and the shared cache memory (4) is maintained. Private cache memory (3) with write-through method.

When the shared cache memory (4) is updated at the same time as (3') or when data is transferred from the main memory (5) or another shared cache memory, the cache controller (107) is updated at the same time as the data is written. Write the table process number inside.

The case where an interrupt request is generated in the 7170 controller (+08) in the above state will be explained using FIG. 3. When an interrupt occurs, a microprocessor that executes the interrupt process is selected as in the conventional example, and an interrupt signal is sent to the counter corresponding to the microprocessor. Here, a case will be explained in which microbrosé y −++ (2) is selected. Microprocessor (2) is 1
When an interrupt signal is received, the values of the stack pointer and program counter are saved in the main memory (5). In this patent, since it is a write-through type, there is no need to evict data and instructions from the private cache memory (3) to the main memory (5). Interrupt processing is performed using a private cache memory (3). Since the private cache memory (3) employs a write-through type, data during one interrupt processing is also stored in the shared cache memory (4). When the interrupt processing is completed, the processing result is written to the main memory (5). After loading the values of the program counter and stack pointer from the main memory (5), the shared xenosh memory (4) is accessed to resume the process that was interrupted by the interrupt process.

The counter is normally set to O and increments its value by 1 when it receives an interrupt signal sent from an interrupt source, and decrements its value by 1 when it detects a return instruction from the interrupt handling routine on the microprocessor bus. . The counter informs the cache controller (107) of the value each time it changes.

Next, the operation of the Canon Yu controller will be explained.

The cache controller determines whether the cache access sent from the microprocessor is a read request or a write request. In the case of a read request, it is checked whether the requested data exists in the cache memory, and if so, whether the data is valid. If the data is cached and the data is valid, the data is immediately passed to the microprocessor and processing is completed. In case of cache miss (including invalid data)
A read request is issued on the system bus (109), and the data to be transferred is read into the cache memory and sent to the microprocessor at the same time.

In the case of a write request, if it is cached and the data is valid, the cache memory is updated immediately;
After issuing an invalidation signal to Basuhi and invalidating all copies on other cache memories, the process is completed. When a cache miss occurs, a read request is issued on the system bus (+09) in the same way as when a cache miss occurs. When the data is transferred,
Import and write into Canon 2 memory. A data read/write miss occurs in the shared cache memory (4
) if there is no space, replacement will occur. In the prior art, private cache memory holds only data specific to that microprocessor, so replacement can be performed freely. Furthermore, since the shared cache memory holds only data common to processor modules, it is not replaced by process-specific data. In this patent, since the shared cache memory holds data for multiple microprocessors, Cannon block replacement is limited by the value of the counter in the processor module and the process number in the directory. In the following, cases will be explained based on the values of both counters.

a The value of both counters is 0. In other words, if there is no interrupt processing in both microprocessors,
Process numbers are compared and blocks with different process numbers are allowed to be replaced.

b Either one of the counters (for example, counter (104)
)l is non-zero, then the cache controller (
107) is executed by both microprocessors (2) for the interrupt processing performed by microprocessor (2).
Replacement of blocks with process numbers of and (2') is prohibited. For the process being executed by microprocessor (2'), replacement of the block having the process number of microprocessor (2) is prohibited.

If the values of both counters are not O (for example, a new interrupt occurs while microprocessor (2) is processing an interrupt, and microprocessor (2') is selected) 9. Both interrupt handlers cannot replace blocks that are already in use. When one of the microprocessors finishes interrupt processing, the block having the process number of the microprocessor currently executing the interrupt processing cannot be replaced.

If an interrupt with a higher priority than that interrupt occurs while the 60 interrupt processing is being executed, and a microprocessor that is already processing the interrupt is selected, the interrupt processing that is being executed is interrupted. In this case, as in normal processing, the values of the program counter and stack pointer are saved to the main memory (5), and a new interrupt processing is executed. When the new interrupt processing is completed, the interrupt result is stored, the program counter and stack pointer values are loaded from the main memory, and the interrupted interrupt is processed using the data in the shared cache memory. Then, the interrupted interrupt is processed, and in this case, until the counter value becomes 0, that is, until the interrupt processing is completed, replacement of the block used in the microprocessor is prohibited.

The snuba (106) monitors data read/write requests on the system bus (109) and determines whether the data in the shared cache memory (4) is invalidated by another microprocessor or a read request is issued. In the event that a request is made, the microbrosse will be notified of the request. This maintains the integrity of data that is prohibited from being replaced and other data.

When the interrupt processing is finished and normal processing is resumed as described above, the private cache is disabled, so the microprocessor obtains data from the shared cache and resumes processing.

In the above embodiment, the blocks of the shared cache memory are identified by the process number of the process processed by the microprocessor, but a number may be provided for each microprocessor and the block may be identified by that number. Alternatively, the counter may be operated by instructions from a microprocessor.

[Effects of the Invention] As described above, according to the present invention, there is a counter provided for each processor that notifies the cache controller of the interrupt status, and a counter provided in the cache controller that uses the counter for each block of the shared cache memory. By providing a table that stores the process number or processor number of the process that is being interrupted, and by prohibiting the replacement of the block of the process interrupted by an interrupt in the shared cache memory, the block before the interrupt is saved in the shared cache memory. This has the effect that processing interrupted by one interrupt can be resumed at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a block diagram showing one embodiment of the cache controller.
Figure 3 is a flowchart of interrupt processing in the present invention, Figure 4 is a timing diagram when an interrupt occurs in a system with four microprocessors in the prior art, and Figure 5 is a block diagram showing a conventional data processing system. figure. FIG. 6 is a flowchart of interrupt processing in the prior art. In the figure, (1) is a processor module, (2) and (2') are microprocessors, (3) and (3') are private cache memory, (4) is shared cache memory, (5) is main memory, (101) ~ (103
) is a transceiver. (104) and (105) are counters, (106) is a snubber, (107) is a cache controller, (1
0g) is the I10 controller, and (109) is the system bus. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] A plurality of processors each having a corresponding private cache memory, a shared cache memory shared by the processors, a counter that detects and holds interrupt instructions and return instructions, and a block number of the shared cache memory and its block. 1. A data processing device comprising: a table for storing processes or processor numbers in use.