JPH04322190A - Method of operating speed control system - Google Patents

Abstract

PURPOSE:To materialize high-speed and high-performance speed control, using a digital processor at relatively low speed. CONSTITUTION:In the past, the operation control of an ACR loop was performed several times during one time of the control operation of an ADR loop, but the control operation of an ASR loop is performed one time during one time of the control operation of the ASR loop as A and B show, and in this period, the speed control operation is completed, whereby speed control of high response becomes possible even with a low-speed digital processor.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] This invention relates to a method for calculating a speed control system in a variable speed control device such as a VVVF inverter;
Especially regarding its improvement.

0002

2. Description of the Related Art Conventionally, when speed control is performed using a digital processing device, it is common to use fixed-period sampling control in which one calculation is performed within the interval of a fixed-period interrupt signal INT, as shown in FIG. It is true. The figure (a) shows the interrupt period INT, the figure (b) shows the current loop (ACR loop) calculation time, and the figure (c) shows the speed loop (
(ASR loop) calculation time, and (d) of the same figure shows other calculation times. That is, although sampling control is a discrete system, by setting the sampling period to about 10 times the response period required by the system, it can be regarded as a continuous system, and conventional classical control theory can be applied.

In addition, in order to perform high-speed, high-precision speed control, it is necessary to control the torque of the motor 4 as shown in FIG. 3, for example, and in the case of a servo motor control system based on a DC machine control model, , it is common to construct a speed control loop that has a current control loop as a minor loop that controls a current equivalent to torque. In addition, the code|symbol 1 of FIG. 3 is a speed regulator (ASR), 2 is a current regulator (ACR), and 3 is a power amplifier (AMP) including a power converter.

By the way, the response of the minor loop is normally required to be several times faster than the response of the major loop. For this reason, in FIG. 3, the calculation period of the ASR loop, which is a major loop, is set to 5×Ts1, for example, with respect to the calculation period Ts1 of the ACR loop, which is a minor loop, and the calculation is completed in each loop.

[0005]

However, in such a system, it is necessary to perform the ACR loop calculation several times during one ASR loop calculation, and when a high-speed speed control response is required, the DSP ( Digital Sign
There is a problem in that a high-speed and expensive processing device such as a processor (Al Processor) is required, resulting in an increase in cost. Therefore, an object of the present invention is to enable high-speed, high-performance speed control to be realized using a relatively low-speed digital processing device.

[0006]

[Means for Solving the Problems] In order to solve these problems, the present invention digitally performs relatively high-speed current control calculations and relatively low-speed speed control calculations in a speed control loop that has a current control loop as a minor loop. When carried out using a processing device, each calculation process of the current control calculation and speed control calculation is completed within the same cycle.

[0007]

[Operation] Since the control target required in speed control is speed, it is not necessarily necessary for the ACR loop to have ideal response characteristics; rather, the operation period of the ASR loop largely controls its response characteristics. From this, if each calculation process of current control calculation and speed control calculation is completed within the same cycle, the amount of calculations for the ASR loop can be reduced and the calculation cycle can be shortened, and low-speed digital processing equipment can be High-speed and high-performance speed control is possible even when used.

[0008]

Embodiment FIG. 1 is an explanatory diagram for explaining an embodiment of the present invention. As is clear from the figure, each calculation process of current control calculation and speed control calculation is performed at the same period T.
It is designed to be completed within s2. Assuming that the calculation times of the ACR loop and the ASR loop are equal in FIGS. 1 and 2, 5×Ts1>Ts2, and the calculation period of the ASR loop becomes shorter. This means that the load factor of the digital processing device becomes lighter, and if the same level of digital processing device is used in FIG. 1 and FIG. 2, the response in the case of FIG. 1 will be faster and the performance will be lower. It becomes possible to aim for improvement. Furthermore, if the required response of the speed control system is the same, a low-speed digital processing device can be used, and since low-speed devices are generally inexpensive, costs can be reduced. In other words, Figure 1
(a) shows the interrupt cycle INT, which is longer than that in Figure 2 (Ts2>Ts1)
The feature is that the ASR loop calculation is completed during this period as shown in FIG. Note that (b) in the same figure shows the current loop (ACR loop) calculation time, and (d) in the same figure shows the other calculation times.

[0009]

[Effects of the Invention] According to this invention, by simply changing the calculation cycle of speed control, it is possible to use a low-speed digital processing device for the same specifications as before, and it is possible to reduce costs. Benefits can be obtained.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram for explaining an embodiment of the present invention.

FIG. 2 is an explanatory diagram for explaining a conventional calculation method.

FIG. 3 is a block diagram illustrating a general example of a speed control loop with a current minor loop.

[Explanation of symbols]

1 Speed regulator (ASR) 2 Current regulator (ACR) 3 Power amplifier 4 Motor

Claims (1)

[Claims] 1. When performing relatively high-speed current control calculations and relatively low-speed speed control calculations in a speed control loop having a current control loop as a minor loop using a digital processing device, the current control calculation and speed control calculation are performed using a digital processing device. A speed control system calculation method characterized by completing each calculation process within the same cycle.