JPH09149654A - Ac controller of motor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the electromagnetic noise of a motor by a method wherein a DC power is converted into an AC power and supplied to the motor in accordance with a modulated signal which is generated by a modulation signal having a predetermined frequency exceeding an audible range. SOLUTION: A current is applied to an imaginary load circuit 2 by a control computer 1 in accordance with a PWM signal (a) which is arithmetically generated from the frequency and voltage of an AC power to be supplied to a motor. As a reactance and an inductance are built in the imaginery load circuit 2, an analog voltage signal (b) is outputted. The analog voltage signal (b) is inputted to a comparator 4 and compared with a carrier wave (c) which is also inputted to the comparator 4 from a carrier wave oscillator 3 to output a PWM signal (d) which is inputted to an inverter 7 through a protective circuit 5 and an amplifier 6. The power semiconductor device of the inverter 7 is turned on and off with a frequency which is increased to exceed an audible range and an AC voltage which has an approximately sinusoidal waveform in accordance with an acceleration value is supplied to the motor. With this constitution, the magnetic noise can be avoided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an AC control device for an electric motor, which converts DC power into AC power based on a modulated signal obtained by pulse width modulating a sine waveform and supplies the AC power to the motor. The present invention relates to a technique for increasing the frequency of a modulated signal.

[0002]

2. Description of the Related Art Conventionally, a PWM (Pulse Width Modulation) method has been adopted in which one cycle of an alternating current is divided into constant segments and the energization time ratio of each segment is set according to the load. An AC control device for an electric motor is known (see Japanese Patent Laid-Open No. 6-296395).

The operation of this device will be described with reference to FIG. Times t ₁ and t ₂ are respectively for the segments SM1 to SM8.
Is an on-time for energization and an off-time for interruption, and is a ratio of energization time for each segment obtained by dividing the ratio of times t ₁ and t ₂ . This energization time ratio is adjusted by the load, and the AC power supplied to the electric motor is controlled.

The digital PWM type device is extremely excellent in that it can obtain an effective voltage that faithfully reflects the setting of the frequency and the accelerator value, but the audible frequency in order to operate the motor quietly. There is a limit in terms of speed when it comes to realizing a high-frequency carrier wave that exceeds. The human ear cannot hear low-frequency sounds, but it is also difficult to hear high-frequency sounds. Therefore, electromagnetic noise is generated due to harmonics that are inevitably generated due to the pulse-like current fragmentation, which is a drawback of the PWM method. It is a thing. The electromagnetic noise is generated because the field coil or the like is deformed and vibrates inside the electric motor under the influence of a chopped current. Ideally, such a problem will not occur if AC power with a clean sine curve is obtained, but a problem that can not be avoided by the PWM method that AC power is obtained as an effective value by dividing the DC current into smaller sections. Is. By increasing the frequency of the carrier wave inside the electric motor, the amount of distortion is reduced, and not only the audible frequency is exceeded, but also the sound source is reduced. At present, the target in this field is 15 to 20 kHz, which is the standard level in the industry.

[0005]

By the way, in the prior art, C
The frequency of the carrier wave that can be realized by using the clock of 8 MHz to drive the PU is about 2 kHz. 20K
It may be possible to calculate it by adopting a clock of 80 MHz to obtain the carrier wave of Hz, but considering noise, unstable power supply, severe weather resistance, vibration and dust on the car, The 80MHz clock, which is difficult to realize with a stationary computer, cannot be realized at this time. As described above, the method provided with a CPU called digital PWM exerts an outstanding power in controlling an accurate frequency and a strict effective voltage, but has a limitation in reducing noise by increasing the frequency of a carrier wave. The higher frequency carrier wave is usually realized by analog PWM, but this is also unsuitable for control of an electric vehicle that requires accurate frequency and effective voltage.

The present invention has been made in view of such conventional problems, and an object thereof is to provide an AC control device for an electric motor capable of reducing electromagnetic noise of the electric motor by increasing the frequency of a PWM signal. .

[0007]

Therefore, the apparatus according to the invention of claim 1 converts DC power into AC power based on a modulated signal in which a sine waveform is pulse-width modulated, and the AC power is converted into an electric motor. In the AC control device for the electric motor to be supplied to the motor, the frequency of the AC power supplied to the electric motor and the output voltage are calculated, and based on the calculated frequency and the output voltage, the data for generating the first modulated signal is generated. A first modulated signal for generating a first modulated signal in which the sine waveform is pulse-width modulated based on the data for calculating the data and the data for the first modulated signal calculated by the data calculating means. Generating means, analog signal converting means for converting the generated first modulated signal into an analog signal having a waveform similar to the AC power waveform supplied to the electric motor, and a modulation signal having a predetermined frequency exceeding the audible range. And a pulse width modulation of the analog signal by the generated modulation signal to generate a pulse width modulated second modulated signal for AC power conversion. And a means for converting the DC power into AC power based on the second modulated signal and supplying the AC power to the electric motor.

According to this structure, even if the first modulated signal generated by the first modulated signal generating means has a frequency in the audible range, the analog signal converting means generates the first modulated signal.
The modulated signal of is converted into an analog signal, and the second modulated signal is generated again by the modulated signal generating means based on the modulated signal of the predetermined frequency exceeding the audible range. Therefore, the second modulated signal is Since the frequency becomes high, there is no electromagnetic noise that can be heard by the human ear.

According to a second aspect of the present invention, while a plurality of writable / readable storage means are provided between the data operation means and the first modulated signal generation means,
The data calculation means writes the data to the storage means that has not been read by the first modulated signal generation means,
The first modulated signal generation means is configured to read data from the storage means which has not been written by the data calculation means.

According to this structure, the first modulated signal is continuously output without any pause even if the data amount is large. In the apparatus according to the third aspect of the present invention, the data calculation means divides the data necessary for generating the first modulated signal into predetermined unit angles of a sine wave for pulse width modulation, and continuously divides the first data. Of the modulated signal generating means.

According to this structure, the first modulated signal generating means continuously transmits the data divided by the predetermined unit angle of the sine wave for pulse width modulation.
In the modulated signal generating means, the first modulated signal is only generated for each predetermined unit angle, and the processing speed can be increased. In the device according to the invention of claim 4, the analog signal conversion means includes a virtual load circuit having a load similar in shape to the electric motor, and the virtual load circuit is energized based on the first modulated signal, The first modulated signal is configured to be converted into an analog signal having a waveform similar to the AC power waveform supplied to the electric motor.

According to this structure, an analog voltage signal having a waveform similar to the AC power waveform can be obtained from the first modulated signal.

[0013]

FIG. 1 is a block diagram showing an embodiment of the present invention.
This will be described with reference to FIG. First, in the embodiment of the present invention, the following points will be considered in order to reduce the noise of the electric motor. (1) Higher frequency of PWM signal (2) Higher speed of data processing First, (1) and (2) will be described. (1) Increasing frequency of PWM signal In order to generate a high frequency PWM signal, its frequency and output voltage are determined by a digital circuit equipped with a CPU, a PWM signal is generated by a carrier wave, and this is used as an actual load. The analog load signal is energized to generate an analog voltage signal, and the analog signal is analog-processed by using a high-frequency carrier wave exceeding the audible range.

In order to increase the frequency of this carrier wave, the analog method is often more convenient than the digital method. In order to reduce the cost of the device and achieve higher frequencies even if the accuracy is sacrificed, the PWM signal generation circuit is divided into a front stage and a rear stage, and the front stage is configured by a digital circuit using a CPU, and the rear stage is It is preferable to use an analog circuit that facilitates higher frequencies.

A control computer handling a digital signal can realize the generation of a carrier wave of about 2 kHz. As described above, the carrier wave is a modulation signal for pulse-width modulating an analog signal. In this way, it is convenient to consider a virtual load circuit in order to obtain a signal voltage equivalent to or intended for an actual three-phase induction motor.

Since the resistance value of the virtual load circuit is the sum of the reactance and the inductance, the relationship between the energizing current and the voltage generated at both ends is obtained by the following equation. Voltage = Resistance x Current (1) As can be seen from this equation (1), the current supplied based on the PWM signal is converted into an analog voltage signal. can do.

The period of this PWM signal and the effective voltage are CP
Since it is controlled by U, it has the accuracy of the digital system itself. The analog circuit in the latter stage uses this signal as an input signal and applies a carrier wave, which is a triangular wave or a sawtooth wave exceeding the audible frequency, to the comparator, and when the signal wave exceeds the level of the carrier wave, the power control semiconductor is turned on, and vice versa. When the level of the carrier wave exceeds the level of the signal wave, the cutoff state is set.

With this structure, the technology already developed can be used in the former stage, and only the latter stage can be developed. High-frequency P is used to avoid high-frequency in digital circuits that require high technology
It is suitable for realizing the WM at a low price. (2) Acceleration of arithmetic processing In order to accelerate the arithmetic processing, for example, two CPUs are provided, one CPU performs sampling and arithmetic of the signal amount of each part of the automobile, and then calculates necessary output specifications. Then, the data is transmitted to the block for the next processing, and the other CPU executes the output of the specifications transmitted from the previous block.

A large number of signals such as the rotation speed of the motor and the amount of depression of the accelerator are sampled, and then the calculation is performed while collating with the data to determine the frequency and voltage value to be output, and the kick signal is generated based on the determined frequency and voltage values. Outputs a controlled rectangular wave signal, but if these are executed by one CPU, a carrier wave of a required speed cannot be realized due to an enormous load.

In the above process, the process up to "determining the frequency and voltage value to be output" in the first half is very complicated, but the allowable time is about 100 ms, which is relatively slow. When the frequency of the wave is increased, the load on the CPU becomes the largest in the latter part of "outputting a controlled rectangular wave signal". Therefore, the processing is divided in the serial direction, and specialized CPUs are provided in the first half and the second half respectively. The CPU in the first stage passes the necessary data to the CPU in the second half, and after passing the data, instead of sampling the data instead of the first process. repeat. The CPU in charge of the latter stage does not perform various processes such as data sampling and calculation, and simply outputs a rectangular wave controlled by the data given from the preceding CPU.

With such a configuration, it is possible to realize a carrier wave of a considerably high frequency by using a clock that is normally feasible, even though it is digital PWM. Also, in order to apply to an electric vehicle having a plurality of electric motors, the C
By adding PU blocks in parallel, it becomes possible to individually control the rotational speed, generated torque, etc. of each electric motor. When you need more advanced processing,
Divide the process flow into three parts, and divide them into three Cs like front, middle, and rear.
It is also effective to process by PU.

Nowadays, the CPU is not a special LSI, and the price is reasonable. Although it is technically a difficult technique in terms of both hardware and software, it is preferable to use a plurality of CPUs if there is a possibility that a large problem can be solved by using a plurality of CPUs. In order to realize such a serial CPU, the following technologies are required. The derived contents will be sequentially described. (2-1) Memory (RA that can be written / read at any time
M) is independently provided with 2 blocks, and a CPU for post-processing
Causes the CPU for pre-processing to take out data from the RAM on the side not being written, and the CPU for pre-processing to write to the RAM on the side not being taken out.

Normally, when a plurality of CPUs are linked in series, a shake hand flag is used, and the post-processing waits until the execution is completed while the pre-processing is being executed, and vice versa. The method waits for writing in the preprocessing while the data is being referenced. However, this method cannot be applied to the purpose of increasing the frequency of carrier waves, which is a problem in this embodiment. Power transmission to the electric motor cannot be stopped at any time, and the above method has a problem in "what to do while waiting" and cannot be solved.

Therefore, two sets of RAM are prepared so that there is no need to wait at all. The pre-processing CPU and the post-processing CPU are respectively R
It is connected to the AM but not to the same RAM at the same time. That is, the preceding CPU is one RAM
When connected to the other RAM, the latter CPU is connected to the other RAM, and when the latter CPU is connected to the one RAM, the former CPU is connected to the other RAM. When executing the process,
The other parties confirm whether or not the other party is in use, and execute using the RAM on the side not in use. However, as a general rule, if a RAM that was not used immediately before is available, that RAM will be used for the next processing. Switching of the address bus and the data bus is performed by a semiconductor switch or the like.

With this configuration, when the rear-stage CPU is reading one RAM, the front-stage CPU transfers data to the other RAM, and the rear-stage CPU transfers one R
When reading the AM data, the previous CPU
Will write data to the other RAM.
As a result, the controlled electric signal can be continuously output without any pause. (2-2) In a PWM device including a plurality of CPUs, a byte string having the PWM waveform itself is transmitted to a CPU that outputs a controlled PWM waveform.

A conventional control computer has a type in which four CPUs are provided and data is transmitted serially, one of which determines the frequency to be output from the sampling of data and the accelerator value, that is, the output. Responsible for the determination of the effective voltage value, and the remaining three determine the width and duty ratio of the segment to be output for each phase of U, V, W based on the data given from the previous CPU. However, I was in charge of the process of actually outputting the on / off signal. However, in this method, the calculation of the segment output to each phase of U, V, W and the duty ratio is wasteful to perform the same calculation in each phase, and in addition, in an electric vehicle equipped with a plurality of electric motors, Since it cannot be expected that the respective electric motors will operate at a constant speed, it is necessary to increase the number of CPUs by three for each electric motor in order to supply appropriate electric power to each electric motor. In addition, although it is faster than processing the whole with one CPU, it does not reach the target frequency to reach the target frequency, so improvement is needed.

In order to obtain a carrier wave of 20 kHz, 50 segments are the minimum control unit in digital PWM.
Must be set in microsecond intervals. 8 CPU
When driven by the MHZ clock, one segment requires 400 clocks, and one instruction requires an average of 6 clocks, so that only 60 to 70 instructions can be executed. That is,
It is possible to decompose the on / off into 60 steps of duty ratio, and it is the best to control the energization amount of the segment to about 60 steps. If the terminal voltage of the storage battery is set to 240V, it will be controlled in steps of about 4V in terms of voltage.

In other words, this is the CP in charge of the final stage.
U is in a state of being full because it outputs an ON / OFF signal unless a technical environment that enables high-speed execution is prepared, such as a dramatic increase in clock speed or a reduction in the number of clocks required for instructions. On the other hand, the refresh interval of the data supplied to the final stage CPU is practically about 100 ms (1/10 sec). This is because the rotation speed and accelerator value of the electric motor are sufficiently faster than the actual change speed if refreshed at such intervals, so that the driver feels as if they were completely continuous quantities, which is a practical problem. Because it is unlikely to be. This means that 120,000 instructions are allowed, and even if it cannot be said that the load is small because the allowable number is large, the processing is advanced to the final data form in the previous stage as much as possible, and the final It is advisable to configure the stage to focus exclusively on its output. In other words, a slight margin may be created in the processing of the previous stage by slightly relaxing the reference of the refresh interval or by speeding up the clock to about 10 MHz, whereas in the processing of the latter stage, other than the output. It is difficult to make room to include extra processing.

Based on the above contents, what kind of data should be passed from the previous stage to the latter stage?
The problem is coming to the fore. As a policy, it is appropriate to proceed with processing at the front stage as much as possible and reduce the load on the rear stage. In the latter stage, if the given data can be output as it is without any processing, it may have the highest potential for speedup.

Therefore, if each bit of 1 byte is properly used as follows, it is possible to output ON / OFF signals for three phases at one time, and it is possible to realize high speed and one CPU.
, And a 16- or 32-bit CPU can cover two to four sets of three phases, which is an appropriate data structure at the processing boundary. An example of the data structure is shown below.

Bit Control object D7 Aki D6 Error bit (optional setting) 0 when normal; 1 when abnormal; D5 W phase independent arm control 0 when interrupted; 1 when energized; D4 W phase cooperative arm control Same as above D3 V phase independent arm Control Same as above D2 V phase common arm control Same as above D1 U phase single arm control Same as above D0 U phase coordinating arm control Same as above As mentioned above, necessary carrier wave, for example 20 kHz
In that case, if the byte string containing such contents is transmitted from the preceding stage to the succeeding stage as a result of editing by dividing it into segments of 50 microseconds, up to the effective number of bytes given by the first two bytes of the byte sequence, Then, just output the given byte string.

The use of the above bits is an example,
If it is 8 bits, 6 channels essential for arm control of each phase may be appropriately allocated and used. Also, for example, when the CPU is for 16 bits, one C
The PU can control the electric motors for two units. Of course, with 32 bits, the control data for four units can be output at a stretch.

However, in terms of price, it is better to use a plurality of 16-bit CPUs in parallel.
As a result of applying a load to the preprocessing, if the execution speed of the preprocessing is too slow, it is also effective to subdivide the preprocessing block by electric motor or function and let a plurality of CPUs take charge. Next, the configuration of the embodiment of the present invention will be described based on this consideration.

FIG. 1 shows a configuration example for realizing the contents of the above (1). In FIG. 1, the control computer 1 includes a CPU, a RAM, a ROM, and the like, calculates an AC frequency and a voltage output to the electric motor, and generates a PWM signal. The virtual load circuit 2 is connected to the control computer 1 and has a built-in reactance and inductance so that an analog signal voltage proportional to the voltage supplied to the actual three-phase induction motor can be obtained. The virtual load circuit 2 corresponds to the analog signal converting means.

The carrier wave oscillator 3 is a modulation signal generating means for generating a carrier wave of, for example, a triangular wave or a sawtooth wave whose frequency is increased to a level higher than the audible frequency. The virtual load circuit 2 and the carrier wave oscillator 3 are connected to the comparator 4. The comparator 4 is a second modulated signal generation means for generating a high frequency PWM signal by comparing the signal level of the carrier wave oscillator 3 with the signal level of the virtual load circuit 2.

The inverter 7 is connected to the comparator 4 via the protection circuit 5 and the amplifier 6, inputs the PWM signal from the comparator 4, and when the motor 8 is operated as a prime mover, the storage battery 9 is based on this PWM signal. The DC power from is converted to AC and supplied to the electric motor 8. Incidentally, FIG. 3 shows an inverter 7 disclosed in Japanese Patent Laid-Open No. 6-296395.
2 shows a circuit configuration example.

In FIG. 3, the transistors Q _{1 to} Q
₆ is constituted by a for example IGBT, etc. can handle a large current, the transistor Q ₁ to Q ₃ is a single arm transistors, the transistor Q ₄ to Q ₆ is common arm transistors. Next, the configuration of the first embodiment for realizing the contents of (2-1) will be described with reference to FIG. In the first and second embodiments, the case where the device according to the present invention is applied to, for example, an electric motor mounted in an electric vehicle will be described, but the present invention is not limited to this.

The control computer 1 includes CPUs 11 and 12
RAMs 13 and 14, change-over switches 15 and 16, and flag units 17 and 18 are incorporated. The CPU 11 inputs a sensor signal sampled by a number of sensors such as the rotation speed of the electric motor 8 and the amount of depression of the accelerator, and matches various data based on the sensor signal,
It is a data calculation means for calculating and determining the cycle data and the accelerator value regarding the frequency to be output.

The cycle data is data representing one wavelength of AC power and regulates the AC frequency. However, the actual data is not the data for one wavelength but is given as the number of clocks less than one wavelength. This cycle data is calculated based on the reciprocal of the target rotation speed. The accelerator value is output as voltage data for adjusting the average value of the output voltage mainly for controlling the output current. In an ordinary vehicle, the torque increases when the accelerator is stepped on, and in the electric vehicle, the output voltage increases when the accelerator is stepped on, and the current supplied to the drive motor increases to increase the drive torque.

The CPU 12 is a first modulated signal generating means for generating a kick signal based on the outputted cycle data and accelerator value and outputting a PWM signal which is a controlled rectangular wave signal. The RAMs 13 and 14 are storage means having similar memory capacities, and are both connected to the CPU 1 via the changeover switch 15 and connected to the CPU 12 via the changeover switch 16.

The flag units 17, 18 store the shake hand flag 1 for read notification and the shake hand flag 2 for write notification, respectively, and are connected between the changeover switches 15, 16. Next, FIG. 4 shows an example of the data structure when data is transferred between the CPUs 11 and 12 in the present embodiment.

In the above (2-2), the example of the data structure in the case of controlling one electric motor has been described, but in the present embodiment, the structure is such that two electric motors can be controlled. In FIG. 4, the number of valid data n is set to the head data. Also, divide the data into each segment,
The data for each segment is set in the data a _{1 to} a _n of 16-bit data. Then, each bit D0~D8 data a ₁ ~a _n as one of the motor data for data, and for the other motor data bits D9～D15.

[0043] At the time bit control object D15 autumn D14 error bit D13 W ₂ phase alone arm control cutoff 0; and at turn 1; D12 W ₂ 'phase common arm control ditto D11 V ₂ phase alone arm control ditto D10 V _2' phase common arm control ditto D9 U ₂ phase alone arm control ditto D8 U ₂ 'phase common arm control ibid D7 Aki (ibid) D6 on error bit D5 W _1-phase alone arm control cutoff 0; 1 when energized; D4 W _1' phase common arm control Id D3 V ₁ phase alone arm control ibid D2 V ₁ 'phase common arm control ibid D1 U ₁ phase alone arm control ibid D0 U _1' phase common arm control ibid Although a bit D15 Ha-out bit, during driving, This bit D15 is used as required for forward rotation, reverse rotation, etc.

Although the error bit of the bit D14 is arbitrarily set, for example, the bit D14 is set to 0 when normal and 1 when abnormal. The error bit of bit D6 is also optional, but when outputting 16-bit data to one electric motor, for example, set bit D6 to 1 and to output it to the other electric motor, set it to 0. To do so.

Next, the operation of the first embodiment will be described.
First, the CPU 11 samples a large number of sensor signals such as the rotation speed of the electric motor 8 and the accelerator depression amount, and calculates the cycle data and the accelerator value based on these sensor signals. The calculated data is set in the data structure as shown in FIG. 4 and written in the RAM 13 or 14.

When the cycle data and the accelerator value are written from the CPU 11 to the RAM 13, the flag value of the read notification shake hand flag 1 stored in the flag unit 17 is confirmed. When the shake hand flag 1 is set to 1, writing to the RAM 13 is possible. At this time, the CPU 11 connects the changeover switch 15 to the RAM 13 and writes the cycle data and the accelerator value in the RAM 13 based on the flowchart of FIG.

That is, in step (denoted as "S" in the drawing, the same applies hereinafter) 1, the count value of the counter CNT is reset. The counter CNT is a counter that counts the number of data. In step 2, the number of valid data n, which is the leading data, is input. Step 3
Then, 16-bit data is sequentially output from a ₁ .

The period data and the voltage data written in the RAM 13 or RAM 14 are input to the CPU 12 from the RAM 13 or RAM 14 via the changeover switch 16 for each segment. In step 4, the count value of the counter CNT is added. This process is repeated for CNT ≦ n, and when CNT> n (step 5), this routine is ended.

When all the data writing is completed, the shake hand flag 2 for writing notification is set to 0. This flag value is stored in the flag unit 18. RAM13
When reading the data written in, the value of the shake hand flag 2 stored in the flag unit 18 is confirmed. When the shake hand flag 2 is set to 0, reading from the RAM 13 becomes possible, the shake hand flag 1 is set to 0, and the changeover switch 16 is set to R.
Connect to AM13. As a result, the flag value of the shake hand flag 2 is stored in the flag device 17, and the CPU 12 reads out the data based on the flowchart of FIG. The cycle data and the accelerator value written in the RAM 13 are read from the RAM 13 for each segment and output to the CPU 12 via the changeover switch 16.

Similarly, data is transferred from the CPU 11 to the RAM 14
When writing to, make sure that the shake hand flag 1 is set to 0 and set the selector switch 15 to RA.
When connected to M14 and all data writing is completed,
Shake hand flag 2 is set to 1. Also, RA
When reading the data written in M14, make sure that the shake hand flag 2 is set to 1,
The shake hand flag 1 is set to 1, and the changeover switch 16 is connected to the RAM 14.

Next, the CPU 11 generates a carrier wave of about 2 KHz based on the cycle data and the accelerator value, and the carrier wave generates a P wave having a waveform as shown in FIG.
The WM signal a is generated. This PWM signal a corresponds to the first modulated signal. Then, the virtual load circuit 2 is energized based on the PWM signal a. As described above, since the virtual load circuit 2 has a built-in reactance and inductance, when a current is applied to the virtual load circuit 2, the analog voltage signal b having a waveform as shown in FIG. It is output from the circuit 2. The voltage of the analog voltage signal b is proportional to the voltage output to the electric motor 8 as calculated from the above equation (1).

The analog voltage signal b can be directly supplied to the inverter 7 to perform the AC conversion in an analog manner. However, since this causes a large power loss, the analog voltage signal b is converted into the PWM signal d and digitally converted. AC conversion is performed. That is, the analog voltage signal b is input to the comparator 4 and compared with the carrier wave c from the carrier wave oscillator 3 that is also input to the comparator 4. The carrier wave c has a high frequency until it exceeds the audible range.

It becomes high level when the analog voltage signal b exceeds the level of the carrier wave c, and conversely becomes low level when the level of the carrier wave exceeds the level of the analog signal. As a result, the comparator 4 outputs the PWM signal d having the waveform shown in FIG. This PW
Since the M signal d is high frequency until the carrier wave c exceeds the audible range, it becomes high level and low level in a cycle shorter than the PWM signal a generated by the control computer 1. This PWM signal d corresponds to the second modulated signal.

The PWM signal d is input to the inverter 7 via the protection circuit 5 and the amplifier 6. Then, the power control semiconductor of the inverter 7 is in a conducting state when the PWM signal d is at a high level, and is in a shutoff state when the PWM signal is at a low level. Therefore, the power control semiconductor of the inverter 7 is driven on / off at a frequency increased to a frequency exceeding the audible range, and the AC power having a waveform approximate to a sine waveform is controlled by the inverter 7 based on the accelerator value. Is supplied to.

According to this structure, by using the digital circuit and the analog circuit in common even though it is a digital PWM device, it is possible to easily increase the frequency to a frequency exceeding the audible range with a clock frequency that can be normally realized.
The frequency of the PWM signal can be increased. Therefore, it is possible to prevent the electromagnetic noise that is harsh to the ear. Further, in the control computer 1, by distributing the data processing by the two CPUs 11 and 12, the load on the CPU can be reduced, and even if the data amount is large, the data can be continued without any pause. It is possible to output, and it is possible to cope with higher frequency of the PWM signal.

Furthermore, since it is only necessary to add an analog circuit to the conventional digital circuit in the former stage in the latter stage, it is possible to avoid high frequency in the digital circuit which requires high technology,
The price can be reduced, and when individually controlling the rotation speed and the generated torque of the electric motors, the CPU blocks can be easily added in parallel and can be easily expanded.

In the present embodiment, the processing flow is divided into three, but the present invention is not limited to this, and three CPUs are used, and the processing flow is divided into three, such as front, middle, and rear. can do. If the number of divisions is increased in this way, more sophisticated processing can be performed, which is effective. Next, a second embodiment will be described.

This is the C in the control computer.
By making the number of PUs three and making the CPU in the output stage a dedicated output CPU, the speed of data transfer is further increased. FIG. 8 is a schematic diagram showing the second embodiment. In FIG. 8, a CPU 21 is a CPU that calculates cycle data and an accelerator value.

The CPU 22 is a CPU which generates a byte string including a pattern of generated alternating current, specifies the length of the byte string, and specifies the section of the written RAM.
The CPU 22 performs processing such as calculation and output of a program counter, reading of software, code analysis, and address output. Also, to allow the collapse of the signal square wave,
An appropriate time lag is provided between each of the above actions in order to cover differences in characteristics of the CPU itself and integrated circuits used as peripheral circuits.

The CPU 23 has a function of simply outputting the byte string on the RAM. That is, by implanting a simple procedure in the hardware itself, C
Run PU23 with simple software. Only the operation specified by the hardware is executed, but it does not depend on the software, so ultra-high speed operation is possible. As described above, the CPU 23 does not have a function that can be called a CPU, but can be called a pseudo CPU.

Next, the configuration of the second embodiment will be described with reference to FIG. 9, which is a detailed view of FIG. The same elements as those in the first embodiment are designated by the same reference numerals and the description thereof will be omitted. The CPUs 22 and 23 are driven by the clock oscillators 21 and 22, respectively. The data bus 41 connected to the data input port of the CPU 21 has a RO
M26, latch circuits 27 and 29, a buffer 29, and a flag device 17 are connected.

Software and data executed by the CPU 22 are written in the ROM 26. Buffer 29 is C
It holds the device switch data output from the PU 21. The device switch is an electric motor, for example, a driving electric motor, a cooling DC electric motor, or the like.
When a plurality of electric motors are mounted, it is a switch for designating the control target, and is attached to the interface board provided for each electric motor. This device switch is usually constituted by an on / off pattern of, for example, about 8 bits, although it depends on the number of electric motors to be mounted, and is set to a different bit pattern for each board.
The setting of the device switch is done by the control computer 1.
It is done at the time of assembling.

Control data is output from the CPU 21 to the comparator 30 at a predetermined timing. The control data includes, for example, an 8-bit signal corresponding to a bit pattern set for each electric motor by a device switch, together with accelerator value and cycle data.

The comparator 30 compares the control data output from the CPU 21 with the device switch data of the buffer 29, and when they match, the latch circuit 27,
The latch signal is output to 28. The latch circuits 27 and 28 respectively latch the accelerator value and the cycle data output from the CPU 21 at the timing when the latch signal is output from the comparator 30.

The RAM 31 is a CPU via the data bus 41.
It is connected to the data input port of 22 and is connected to the data output port of the CPU 22 via the data bus 42. The RAM 31 functions as a work RAM, and when the software of the CPU 22 is executed, the contents of the ROM 26 are written from the output port of the CPU 22 via the data bus 41. The changeover switch 15, the flag device 18, and the changeover switch 51 described above are connected to the data bus 42, and the changeover switch 51 is further connected to RAMs 32 and 33 for storing the number data.

In the second embodiment, the effective data number n shown in the above data structure example is separately output to the RAM 32 or the RAM 33. Changeover switches 52 and 53 for changing address values are connected to the address buses 43 and 44 connected to the CPUs 22 and 23, respectively. The data bus 45 connected to the data input port of the CPU 23 is connected to the change-over switch 16, the flag device 18, and the change-over switch 54 for changing the number of usages.

On the data bus 46 connected to the output port of the CPU 23, the above-mentioned flag device 17, changeover switch 16,
52 to 54 are connected. The virtual load circuit 2 described above is connected to the data bus 46. Next, the operation of the second embodiment will be described. In CPU22, after power is turned on, CP
After ensuring the function of U22, the software and data stored in ROM26 are read from ROM26, and RAM31
Is copied to

When the copy of the contents of the ROM 26 to the RAM 31 is completed, the CPU 22 starts the specified operation by the software and the data on the RAM 31, and thereafter the contents of the ROM 26 are not referred to in principle. Next, CPU
The operation of 22 will be described based on the flowchart of FIG. At step 11, the data of the device switch is read.

At step 12, the accelerator value is input.
That is, as described above, the control data includes, for example, an 8-bit signal corresponding to the bit pattern set for each electric motor by the device switch, and the control data pattern and the device switch pattern are included. When and match, a latch signal is output from the comparator 30 to the latch circuits 27 and 28, and the accelerator value is latched by the latch circuit 27 at this timing. The latched accelerator value is input via the data bus 41.

In step 13, the cycle data latched by the latch circuit 28 is input in the same manner. Thus, C
PU21 informs which motor is targeted by the accelerator value and the cycle data to be transmitted as hardware control data, and the latch is transmitted immediately after the same control data as the device switch is issued. Accelerator value and cycle data are sent to CPU22 or CP
It is mechanically executed without the control of U23 and always latches the latest value.

In step 14, the value of the shake hand flag 1 is input from the flag unit 17, and the RAM 13 or 14 which is not outputting is detected. Either RAM can be used in the first cycle. In step 15, this flag value is compared with the immediately preceding input value. When the value of the shake hand flag 1 matches the immediately preceding input value, it is determined that the CPU 23 is in the process of reading data, and the process returns to step 12.

When the reading of data from the RAM 13 or RAM 14 by the CPU 23 is completed, the flag value of the shake hand flag 1 is switched, so that the value of the shake hand flag 1 does not match the immediately preceding input value.
At this time, it is determined that the reading of the data from the RAM 13 or RAM 14 is completed, and the process proceeds to steps 15 → 16. In step 16, a bit pattern of a byte string to be output is generated based on the cycle data and the accelerator value, and this bit pattern is used as data a ₁ -a _{1 having} a data structure as shown in FIG.
It is set to a _n and this byte string is output. This byte string is written in the RAM 13 or RAM 14 when the changeover switch 15 is changed.

As described above, since which of the RAM 13 and the RAM 14 is written is controlled by the CPU 23, the CPU
22 confirms that the shake hand fract 1 is different from the previous contents, and executes the write operation to the RAM 13 or RAM 14. In step 17, the length of the output byte string is output as “number data”. Step 18
Then, a shake hand flag signal is generated as a write completion signal in the shake hand flag 2. That is, when the value of the shake hand flag is 1, it is set to 0, and when it is 0, it is set to 1. In this way, the shake hand flag signal is generated.

The shake hand flag 2 may be output by inverting the contents of the shake hand flag 1. However, the value of the flag indicates the following contents. Shake hand flag 1 Meaning 0 CPU 23 is reading from RAM 13 (outputting) 1 CPU 23 is reading from RAM 14 (outputting) Shake hand flag 2 0 CPU 22 has been written to RAM 13 1 CPU 22 has been written to RAM 14 It can be set arbitrarily, but in that case, it is necessary to change the determination content accordingly.

In step 19, the generated shake hand flag 2 is output to the flag unit 17. The above loop is repeated until the power is cut off. In addition, step 12,
The input timing of the accelerator value and the cycle data in 13 may be in the determination loop of the shake hand flag 1 or may be executed after the determination.

When the RAM 31 has a large capacity,
As shown in the flowchart of FIG. 11, an output bit pattern is generated in the RAM 31 (step 21), and when writing this output bit pattern, the RAM 31 to the RAM 13 or RA is used.
You may make it write in M14 (step 22). Next, the operation of the CPU 23 will be described.

The data output function of the CPU 23 is mainly composed of the following four blocks. (1) RAM switching signal generation function (2) Pseudo address value generation and cycle determination function (3) Data retrieval function from RAM (4) Shake hand flag 1 writing function (1) RAM Regarding Function of Generating Switching Signal RAM 13 and RAM 14 are data writing memories for CPU 22 and reading memories for CPU 23. Thus, when the same memory is used for different purposes, it is necessary to switch it according to the timing.

In the present embodiment, the final output is the CPU
The changeover switches 15 and 16 are controlled by the CPU 23 in order to prevent the changeover from being performed in the middle of output and to continuously execute the output. While the CPU 23 is outputting the contents of RAM 13 or RAM 14, the target RAM
Is separated from the control of the CPU 22 and is controlled / controlled by the CPU 23.

The CPU 23, which has determined the read RAM by referring to the shake hand flag 2, first reads R for read.
The AM select signal is output to the changeover switches 16 and 54. This activates the changeover switches 15, 51-54. A shake hand signal is output to notify the shake hand flag 1 which RAM to use. During this period, the PWM signal outputs the off signal for both the single arm and the common arm. (2) Function of generating pseudo address value and determining cycle The CPU 22 controls the changeover switches 52 and 53 to issue the address value of the target RAM 13 or RAM 14, and R
Although the structure is such that a specific position such as the AM 13 or the RAM 14 is accessed, the CPU 23 must generate the address value by itself when referring to the RAM 13 or the RAM 14. The CPU 23 has an independent clock, is connected to a counter that counts a rectangular wave generated by the clock, and is configured to use the value of the counter as an address value in a pseudo manner. The counter is from 0 to RAM
The value is counted up to 13 or the value of the number-of-uses data of the RAM 14 to specify the cycle of one AC waveform of the comparator 4, but at the same time, the value is accessed to the RAM 13
Alternatively, the address value of the RAM 14 is generated. It is not possible to access any address, but R in ascending or descending order
It can be used when reading or writing data from the AM 13 or RAM 14. (3) Regarding the function of fetching data from RAM The data fetch from RAM13 or RAM14 is shown in FIG.
It operates based on the flowchart of. In addition, it is configured to set the address value, take out the contents of the specified address to the buffer via the interface, and connect to the subsequent device via a high-speed photocoupler, for example, to prevent noise from the outside. There is. (4) Function for writing to shake hand flag 1 When all data reading is completed, the shake hand flag 1 is set to the above-mentioned flag value, and this flag value is stored in the flag unit 17.

Both shake hand flags 1 and 2 are applied to a predetermined 1 bit. Regarding other bits, any data is not related to the hardware when the input or output instruction is executed. Although it is possible to use a configuration if necessary, one bit is sufficient here. As described above, although the CPU 23 is limited in what it can do, it is almost directly accessed by the RAM 13 or the RAM 14 rather than being accessed after the software is read and various kinds of determination and preparation processing are performed.
Because it accesses to, very high speed is possible.

According to the configuration of the second embodiment,
By using the output stage CPU 23 as an output-only CPU, it is possible to further speed up data transfer. That is, the CPU 23 executes only the operation specified by hardware, but does not depend on software, so that it can operate at an extremely high speed. Moreover, since it can be designed as a specific device, it is not necessary to consider various measures,
Therefore, the idle time can be reduced according to the peripheral integrated circuits.

[0082]

As described above, according to the device of the invention of claim 1, the second modulated signal has a high frequency,
There is no electromagnetic noise that can be heard by humans. According to the apparatus of the second aspect of the present invention, even if the amount of data is large,
The first modulated signal can be continuously output without any pause.

According to the third aspect of the present invention, the processing speed of the first modulated signal generating means can be increased. According to the apparatus of the invention of claim 4,
An analog voltage signal having a waveform similar to the AC power waveform can be obtained from the modulated signal of.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing the internal configuration of the control computer shown in FIG.

FIG. 3 is a circuit diagram showing the configuration of the inverter shown in FIG.

FIG. 4 is an explanatory diagram of a frame for data transmission between CPUs in FIG.

5 is a flowchart showing the operation of the CPU of FIG.

FIG. 6 is a signal waveform diagram of FIG.

FIG. 7 is an explanatory diagram of PWM.

FIG. 8 is a block diagram showing an outline of a second embodiment of the present invention.

9 is a block circuit diagram showing details of FIG. 8;

FIG. 10 is a flowchart showing the operation of the CPU of FIGS. 8 and 9.

11 is a flowchart showing an application example of the operation of FIG.

[Explanation of symbols]

 1 Control computer 2 Virtual load 3 Carrier wave oscillator 4 Comparator 11, 12, 21-23 CPU

Claims (4)

[Claims] Claim: What is claimed is: 1. An AC controller for a motor, wherein DC power is converted to AC power based on a modulated signal obtained by pulse-width-modulating a sine waveform, and the AC power is supplied to the motor. Of the frequency and the output voltage, and data calculating means for calculating the data for generating the first modulated signal based on the calculated frequency and the output voltage, and the first data calculated by the data calculating means. A pulse-width modulated sine waveform based on the data for the modulated signal of
A first modulated signal generating means for generating a modulated signal, and an analog signal converter for converting the generated first modulated signal into an analog signal having a waveform approximate to the AC power waveform supplied to the electric motor. Means, a modulation signal generating means for generating a modulation signal of a predetermined frequency exceeding the audible range, and a pulse width modulation of the analog signal by the generated modulation signal, and a pulse width modulated second power conversion AC power converter. Second modulated signal generating means for generating a modulated signal, and based on the second modulated signal, converts DC power into AC power and supplies the AC power to an electric motor. An AC control device for an electric motor. 2. A plurality of writable / readable storage means are provided between the data calculation means and the first modulated signal generation means, while the data calculation means is composed of the first modulated signal generation means. Write data to the memory that has not been read,
2. The AC control device for an electric motor according to claim 1, wherein the first modulated signal generation means is configured to read data from the storage means that has not been written by the data calculation means. 3. The data calculating means divides data required for generating the first modulated signal into predetermined unit angles of a sine wave for pulse width modulation, and continuously generates the first modulated signal. The AC control device for an electric motor according to claim 1 or 2, wherein the AC control device is configured to be transmitted to the means. 4. The analog signal converting means comprises a virtual load circuit having a load similar in shape to a motor, and the first modulated signal is supplied by energizing the virtual load circuit based on a first modulated signal. The AC control of the electric motor according to any one of claims 1 to 3, wherein the signal is configured to be converted into an analog signal having a waveform similar to an AC power waveform supplied to the electric motor. apparatus.