JPH04321996A - Multiplex circuit and semiconductor integrated circuit device using same - Google Patents

Abstract

PURPOSE:To divide wiring resistance and wiring capacity and to reduce wiring delay in data bus lines by dividing the data bus lines and multiplexing them to realize a high-speed and highly integrated memory LSI. CONSTITUTION:The multiplex circuit is constituted as such that the collectors of plural bipolar transistors Q11, Q12 are connected to a high potential power source VCC, and emitter is connected to a low potential power source via a current source circuit, and a base is connected to input terminals IN1, IN2 respectively; that, by switching on MOS transistors M11, M12 at the time of a selection and switching them off at the time of a non-selection, a base potential is controlled; and that multiplexed signals are outputted to output terminals OUT which are taken out been the emitter and the current source circuit. Consequently, the highly integrated and high-speed memories and micro-processors with the power source voltage less than 3.3V are realized.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit that operates at high speed and is highly integrated.

0002

2. Description of the Related Art High performance computers have been achieved by increasing the speed and capacity of memory LSIs. However, in recent years, memory capacity has exceeded M bits,
The increase in chip area has become an impediment to high speed performance. As the memory capacity increases, the first
The output signals of the sense amplifiers PS1 and PS2 in the second stage are several meters long.
The signal is propagated through the m data bus lines CC1 and CC2. The higher the degree of integration, the longer the data bus line becomes, and the further the miniaturization progresses, the thinner the line width becomes. This increases the resistance of the data bus line wiring. Similarly, as the data bus line pitch becomes smaller, the capacitance between wirings also increases. As described above, wiring resistance and wiring capacitance increase. As a result, the signal line delay increases, making it impossible to achieve high integration and high-speed performance at the same time. Conventionally, as a method to solve this problem, the data bus line is divided by a data multiplexer using multi-emitters as shown in Japanese Patent Application No. 1-63749, and the resistance and capacitance are divided, resulting in high integration and high speed. There are examples of performance being achieved at the same time.

0003

[Problems to be Solved by the Invention] The data multiplexer using the multi-emitter of the prior art has a power supply voltage of 3.3
If the voltage is below V, normal operation cannot be obtained. The reason for this will be explained using FIG. 19. In the circuit of FIG. 19, the voltage drop between MP1 and MP2, which also serves as a current source and selection logic, is about 1V in total.
The voltage drop at QP1 and QP2 is approximately 0.8V and Q
The voltage drop at ME1 and QME2 is also approximately 0.8V each.
, Furthermore, since there is a load resistance between the collectors of QME1 and QME2 and VCC1, an output voltage amplitude occurs at the collectors, resulting in a voltage drop of about 0.8V. Therefore, V.C.
The total voltage drop from the C1 terminal to the ground potential through QME1, QP2, MP1, and MP2 is 3.4V,
Conventional multiplex circuits cannot operate with a power supply voltage of 3.3V. Furthermore, in highly integrated LSI,
Furthermore, it is necessary to make the multiplex multi-layered, but this cannot be achieved with conventional multiplex circuits.

One of the objects of the present invention is to reduce the power supply voltage to 3.3V.
An object of the present invention is to provide a multiplex circuit that can operate normally even under the following conditions, and a semiconductor integrated circuit device using the multiplex circuit.

Another object of the present invention is to provide a multiplex circuit that can be implemented in multiple layers and a semiconductor integrated circuit device using the same.

Further objects of the present invention will become clear from the description of the embodiments.

[0007]

[Means for Solving the Problems] The basic idea of the present invention for achieving the above object is to connect a junction that causes a potential drop between a high potential power source and a low potential power source to a bipolar transistor.
The objective is to eliminate the load resistance between the collector of the bipolar transistor and the high potential power supply. Specifically, a plurality of emitter follower circuits are combined to form an emitter follower type multiplex circuit in which each base is used as an input and each emitter is connected to each other. This emitter follower type multiplex circuit realizes the non-selection/selection multiplex function by controlling the base potential. To control this base potential, a MOS transistor is provided between the base and a high potential power supply node via a resistance element, and the MOS transistor corresponding to the selected base is turned on and connected to the high potential power supply node. MOS corresponding to the base
The transistor is turned off and cut off, and the base potential is lowered using current extraction circuit means.
It is characterized by doing.

It is important to maintain the potential of the non-selected base above a set level so as not to lower it too much, and to quickly switch the base potential to the selected level. For this reason, a feature is that a second resistance element and a diode are provided in the forward direction in parallel to the MOS transistor provided between the base and the high potential power supply node via the first resistance element for clamping.

Furthermore, as a means for reducing the fluctuation (amplitude) of the base potential when selected/unselected, a MOS transistor and a third A resistive element is provided in series, and the MOS
A second resistance element is further provided in parallel with the series connection of the transistor and the third resistance element, and the effective load resistance value from the high potential power supply node to the base is set to a similar value when selected and when not selected. It also features

Further, as the current drawing circuit means, a drawing M is provided between at least the base and the low potential power supply node.
A circuit may be provided in which an OS transistor is provided, and the MOS transistor corresponding to the non-selected base is turned on to short-circuit it to a low potential power supply node, and the MOS transistor corresponding to the selected base is turned off and cut off. It is a characteristic.

Furthermore, as a means for reducing the steady current when drawing current, at least two or more current source means are connected in series, one being a constant current source and the other being a control signal (
It is also possible to use a circuit that switches (on/off) depending on the selection (non-selection/selection). Furthermore, as a means for eliminating a steady current when not selected when drawing current, at least two drawing MOS transistors are connected in series, and the output of the inverter circuit is connected to the gate of one of the MOS transistors. A control signal may be input to the gate of the other MOS transistor and the input of the inverter circuit, and the circuit may draw current only during the delay time of the inverter circuit at the moment of switching from the selected state to the non-selected state.

As a multiplexing means other than the emitter follower type multiplex circuit, there is a collector dot type multiplex circuit.

By combining the above-mentioned means for each application such as a memory LSI, a microprocessor, etc., it is possible to obtain appropriate effects corresponding to each application.

[0014]

[Operation] Explain how the technical means work. Since the emitter follower type multiplex circuit of the present invention has only one bipolar transistor and a current source circuit between the high potential power source and the low potential power source, the operating voltage is between the base and emitter of the bipolar transistor. This is the sum of the voltage drop (approximately 0.8V) at the current source circuit and the voltage drop (approximately 1V) at the current source circuit, and the power supply voltage is
．． Operation is possible even when the voltage drops to about 0 V. This point also applies to collector dot type multiplex circuits. Furthermore, in an emitter follower type multiplex circuit, the input voltage level is "Hi" and the output voltage level is "Lo".
”, and on the other hand, in the collector dot type multiplex circuit, the input voltage level is “Lo” and the output voltage level is “Hi”.
”, they can be used as other input circuits or output circuits, so a multiplex multi-layer configuration is possible.

Next, the operation of the base potential control circuit that realizes this emitter follower type multiplex circuit will be explained. Data selection is performed by controlling the base potential, and in the present invention, this base potential is controlled by providing a MOS transistor between the base and a high potential power supply node via a resistance element, and connecting a MOS transistor corresponding to the base to be selected. This is characterized in that the transistor is turned on to short-circuit it to a high-potential power supply node, the MOS transistor corresponding to the unselected base is turned off and cut off, and the base potential is further lowered by the current extraction circuit means. In this circuit, if the base potential is controlled by turning on the MOS transistor provided between the high potential power supply and the base and turning off the base potential extraction circuit, the input signal becomes the input voltage of the base, and that signal is applied to the emitter. Output. Also MO
When the S transistor is turned off and the base extraction circuit is turned on, the base potential is fixed at a low potential and the input signal is not output to the emitter. This operation enables data selection. This method is implemented by extracting the accumulated charge based on non-selection, so another feature is that it is possible to realize an emitter follower type multiplex circuit without flowing a steady current from a high potential power supply when non-selection.

[0016] If the base potential during non-selection drops too much,
When switching to the selection mode, the delay until the base potential rises to the selection level increases. It is necessary to maintain the base potential above a certain level and reduce the delay until the base potential rises to the selected level. For this reason, if a diode and a resistance element are provided in parallel with the MOS transistor,
When selected, the voltage applied to the diode is set below Vbe, so it does not operate, but when not selected, the high potential power supply and the base are cut off, the extraction circuit is turned on, and the voltage applied to the diode increases. , Vbe is reached. When a voltage of Vbe is applied to the diode, the diode turns on, and even if the base potential drops when not selected, it is clamped by the diode. Therefore, it will not fall below a certain level.

By reducing the variation in the base potential during selection and non-selection, the base potential can be quickly switched to a set level in response to switching between selection and non-selection. In order to reduce fluctuations in the base potential, the effective value of the load resistance from the high potential power supply node to the base is set to be larger when not selected than when selected, and by reducing the difference, the base potential Fluctuations can be reduced.

When the above-mentioned clamp diode or the like is used, the clamp diode operates when it is not selected, and a current flows through this diode and the current extraction circuit means. In order to reduce this current, the current drawing circuit means draws out the charge from the base at once at the moment of switching from the selected state to the non-selected state, bringing the base potential to the non-selected level at high speed, and then returns to the non-selected steady state. Now, in order to prevent current from flowing, two MOS transistors for extraction are connected in series, the output of the inverter circuit is connected to the gate of one of the MOS transistors, and the output of the inverter circuit is connected to the gate of one of the MOS transistors.
Since the configuration is such that a control signal is input to the gate of the OS transistor and the input of the inverter circuit, the two extraction MOS transistors are activated only during the delay time of the inverter circuit at the moment when the selected state is switched to the non-selected state. Both are in the on state and draw current, and in the non-selected steady state, the MOS transistor receiving the output of the inverter circuit is in the off state, so no steady current flows.

In order to control the base potential, in addition to providing a MOS transistor between the base and a high potential power supply node via a resistance element, it is also possible to connect the base to a high potential power supply node via a resistance element, According to this structure, by short-circuiting the base and the low potential level when not selected, the base potential when not selected is lower than the base potential when selected. Can be lowered and multiplexed.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A multiplex circuit according to the present invention and a semiconductor integrated circuit device using the same will be described below with reference to the drawings showing embodiments thereof.

[Embodiment 1] FIG. 1 shows an embodiment of the multiplex circuit of the present invention, which is the most basic emitter follower type multiplex circuit. First, the circuit configuration will be explained. BC1, BC2, . . . are a plurality of basic circuits forming a multiplex circuit, and each basic circuit has first power terminals T11, T12, . . . connected to a high potential power supply VCC.
, a second power supply terminal T21 connected to the low potential power supply VEE
, T22,..., input terminals IN1, IN2,..., select terminals SE1, SE2,..., the emitter is the second power supply terminal T
21, T22,..., the collector is connected to the first power supply terminal T11.
, T12,..., the bases are input terminals IN1, IN2,...
bipolar transistors Q11,
Q12,..., connected in series to the first power supply terminals T11, T1
MOS transistors M11, M12,... and resistor R1 connected between 2,... and input terminals IN1, IN2,...
1, R12,..., MOS transistors M11, M12,
Connection point between … and resistors R11, R12, … (control node)
NC1, NC2, ... and second power terminals T21, T22,
Current extraction means B1, B2,... connected between...
It consists of MOS transistors M21, M22, . . . The gates of the MOS transistors M11, M12, . . . and the gates of the MOS transistors M21, M22, . . . are connected to select terminals SE1, SE2, . The second power supply terminals T21, T22, . . . are connected to a low potential power supply VEE via a MOS transistor serving as a current source circuit SI, and an output terminal OUT is drawn out from a connection point with the current source circuit SI.

Next, the operation of this multiplex circuit will be explained. One of the input terminals IN1, IN2, ...IN1
Data to be selected in 1 is input. At this time, a select signal is input to the select terminal SE1, and the MOS transistor M
11 is turned on.

By turning on the MOS transistor M11, the control node NC1 is pulled up to the high potential power supply VCC,
A voltage obtained by subtracting the on-resistance of the MOS transistor M11 and the voltage drop due to the resistance element R11 from the high potential power supply VCC is applied to the base of the bipolar transistor Q11. On the other hand, unselected data is input to the remaining terminals IN12, ... of the input terminals IN1, IN2, ..., and at the same time, a non-selector signal is applied to the remaining selector terminals SE2, ..., and the MOS transistors M12, ... are held in the off state. do. As a result, the control nodes NC2, . . . are cut off from the high potential power supply VCC. By operating the current source circuit SI here, the base potential of the bipolar transistor Q12 becomes lower than the base potential of the bipolar transistor Q11. Since the output potential of the output terminal OUT is determined by the base at a higher potential, the base potential of the bipolar transistor Q11 becomes the output potential. In this way, the circuit in Figure 1 operates as a multiplex circuit because the base potential of the bipolar transistor to which non-selection data is input is lower than the base potential of the bipolar transistor to which selection data is input. do.

According to the multiplex circuit having such a configuration, only the bipolar transistor (Q11) and the current source circuit SI connected in series are interposed between the high potential power supply VCC and the low potential power supply VEE. From, Vbe (0.8V) of the bipolar transistor and current source circuit SI (
It has the advantage of operating at a low voltage that exceeds the sum of the voltage drop (1.0 V) of the MOS transistor.

[Embodiment 2] FIG. 2 shows a first modification of the emitter follower type multiplex circuit shown in FIG. This modification uses MOS transistors M31, M32, . . . instead of resistors R11, R12, . This M.O.
The S transistors are MOS transistors M11, M12,
It has the same conductivity type as... This has the advantage that the multiplex circuit can be made smaller when it is formed within a semiconductor integrated circuit.

[Embodiment 3] FIG. 3 shows a second modification of the emitter follower type multiplex circuit shown in FIG. In this modification, diodes D11, D12, . . . are connected in parallel to MOS transistors M11, M12, . In this way, the potentials of the control nodes NC1, NC2, ... will not become lower than the value obtained by subtracting the base-emitter voltages of the bipolar transistors Q11, Q12, ... from the potential of the high potential power supply VCC. [Embodiment 4] FIG. 4 shows a third modification of the emitter follower type multiplex circuit shown in FIG. 1. This modification example is shown in Figure 3.
The configuration is such that resistors R21, R22, . . . are interposed between MOS transistors M11, M12, . . . and control nodes NC1, NC2, . According to such a configuration,
In addition to the advantages that the circuit of FIG. 3 has, the control node NC1
, NC2,..., the bipolar transistor Q1
1, Q12, ... base-emitter voltage or less (0.2-
0.3V).

[Embodiment 5] FIG. 5 shows a third modification of the emitter follower type multiplex circuit shown in FIG. This modification uses resistors R31, R32, . . . in place of the diodes D11, D12, . . . in FIG. In this case, even if there is no current extraction means, the MOS transistor M1
1, M12,... are turned off to control nodes NC1, NC2.
,... has the effect of lowering the potential. Furthermore, this can be ensured by providing current extraction means.

[Embodiment 6] FIG. 6 shows a different embodiment of the current extraction means.

In (a), the MOS transistor M21 is connected in series with the MOS transistor M211 as a constant current source, and when the MOS transistor M11 has a bypass circuit, the through current can be suppressed to reduce power consumption. can.

(b) and (c) are modified examples of (a) with MO
An inverter is connected to the gate of either the S transistor M21 or M211, and the same gate signal is applied to both MOS transistors. With this configuration, when the MOS transistor M21 is turned on, the MOS transistor M211 shifts from on to off, but due to a time delay, there is a period in which both MOS transistors are on, making it possible to draw current in a short time. Even if a through current flows, it lasts for only a short time, so it is possible to reduce power consumption. The important thing is to design the inverter so that it can draw enough current.

(d) is a combination of (a) and (b), and ensures more reliable current extraction than (b) and (c).

(e) is a configuration in which the MOS transistor M21 is used in common in (d). (f) is an example in which a bipolar transistor is used instead of the MOS transistor M21.

[Embodiment 7] FIG. 7 shows another embodiment of the current source circuit SI.

(a) MOS transistor M71 for switching and MOS transistor M7 as a constant current source
2 is connected in series. In this example, MOS transistor M71 is used only when selected.
Since the circuit 72 is always on, it has the advantage of fast operation and low power consumption.

(b) is the MOS transistor M7 of (a)
A MOS transistor M73 is connected in parallel with MOS transistor M73. In this example, multiplex operation can be ensured by allowing a minute current to flow even when not selected.

(c) shows an example in which a bipolar transistor Q7 is used as a switching element.

(d) shows bipolar transistors Q7 and M
It is connected in series with the OS transistor M72.

[Embodiment 8] FIG. 8 shows a second embodiment of the present invention. This is a collector dot type multiplex circuit that receives the output from the multiplex circuit and further multiplexes the data. EO1 to EO4
is an input terminal that receives the output of the multiplex circuit at the previous stage. For example, if the common collector line extending in the long side direction of a memory chip is divided into four blocks, the output of multiplexing data from two blocks each in the left and right directions of the chip or in the top and bottom directions of the chip is
Let them be O1, EO2, EO3, and EO4. Collector of bipolar transistor QC1 with EO1 as input and EO
Due to the collector dot configuration that connects the collector of the bipolar transistor QC3 with input QC3, only the bipolar transistor whose base potential is the selected level (Hi level) operates, and the QC
1 or QC3, whichever has a higher base potential, the collector current of the bipolar transistor and the load resistance RC1.
The value obtained by subtracting the product with the resistance value from the high potential power supply VCC becomes the output of the collector, and input data can be multiplexed. In the example shown in FIG. 8, since a differential amplifier configuration is adopted, the output collector potential is passed through an emitter follower circuit EF composed of bipolar transistors QE1 and QE2 to the next stage, for example, a sense amplifier SA1.
, SA2 or the output buffer.

The circuit of this embodiment includes resistors (RC1 and RC2), bipolar transistors (QC1, QC2, . . . ) and MO
Since the S transistor is connected in series, it is higher than the sum of the voltage drop due to the resistor (0.05V), the Vbe of the bipolar transistor (0.8V), and the voltage drop of the MOS transistor (1.0V). That is, multiplex operation can be performed at low voltage.

In addition, in this embodiment, the common collector line is 4
Since it can be divided, it is possible to reduce signal delay in the common collector line and increase speed. 16Mbit BiCMOSSRA
According to the results of prototype M, it took 2.1 ns when the conventional common collector wire was divided, compared to 3.0 ns when the common collector wire was not divided.
The speed was significantly increased to ns.

Furthermore, the collector dot type multiplex circuit of this embodiment has an input voltage of "Lo" and an output voltage of "H".
i'' is the opposite of the emitter follower type multiplex circuit, so by combining it with an emitter follower type multiplex circuit, multiplexing at a higher level is possible.The details of the combination will be described in another embodiment.

[Embodiment 9] FIG. 9 shows a third embodiment of the present invention. This is an embodiment in which an emitter follower type multiplex circuit according to the present invention is combined with a pre-sense amplifier circuit in the preceding stage. CC1 and CC2 are so-called common collector lines that connect the output of the pre-sense amplifier composed of the differential voltage-to-differential current conversion circuit in the previous stage and the collectors of bipolar transistors Q1 and Q2 of the multiplex circuit, in other words, the multiplex circuit. This is the input terminal of Similarly to FIG. 1, R1 and R2 are load resistances for current-voltage conversion. When a block including CC1 and CC2 is selected, a "Lo level" signal is input to the select terminal DSA, MOS transistor M1 is turned on, and control node NCA changes from the high potential power supply VCC to the on-resistance of MOS transistor M1 and the load resistance. The voltage rises to the level after subtracting the voltage drop due to RA. MOS transistors M2 and M4 and diode DPA are in an off state. On the other hand, in a block including CC3 and CC4 that are in a non-selected state, a "Hi level" signal is input to the DSB, and the MOS transistor M6 is turned off. MOS transistor M7 is turned on, and terminal VIE
Since the MOS transistor M8 to which a constant voltage is applied is in the on state, current flows through the MOS transistors M7 and M8. The potential of NCB tries to fall, but when it falls to the value obtained by subtracting the base-emitter voltage Vbe of the bipolar transistor from the high potential power supply VCC, diode D2 turns on and current flows through diode D2 to NCB.
The potential does not fall below the level of VCC-Vbe. Here, when the MOS transistors M7 and M8 are not selected, current flows steadily, so considering power consumption, the MOS transistors M7 and M8 are
For example, by reducing the conductance of transistor M8,
It is necessary to take measures to suppress the current flowing through the MOS transistors M7 and M8. Further, the MOS transistor M9 is in the on state, but the MOS transistor M10 is in the off state by the inverter INV2 connected to its gate, so that no current flows steadily. However, at the moment when the selected state is switched to the non-selected state, that is, the DSB is “
The moment the level changes from "Lo level" to "Hi level",
During the delay time of inverter INV2, MOS transistors M9 and M10 are both turned on, and the potential of NCB tends to fall. Here, MOS transistors M9 and M1
If the conductance of NCB is made large enough, the potential of NCB will reach VCC within the delay time of inverter INV2.
−Vbe level. In the above state, bipolar transistors Q1 and Q2 are operated by the selected CC1 and CC2 signals, and EO1 and EO2 connected to the emitters of bipolar transistors Q1 and Q2 have Vbe from CC1 and CC2.
A lower level potential is output. Bipolar transistors Q3 and Q4 have an emitter-base voltage of Vbe.
It has a multiplex function because it does not work as follows. In addition, load resistors RA and RB are connected in series to the MOS transistors M1 and M6, and the potential at the time of selection is set to a value close to the potential at the time of non-selection.
The amplitude of the NCB and NCB are reduced to increase speed and save power. With the above operation, the common collector line with large wiring capacitance can be divided, so signal delay due to wiring resistance and wiring capacitance can be reduced, and 16 Mbit BiCMOS
As a result of prototyping SRAM, the common collector line is 2.0 ns compared to 3.0 ns when the common collector line is not divided.
When divided into two parts, the speed could be increased to 2.3 ns.

[Embodiment 10] FIG. 10 shows an embodiment in which the output signal of FIG. 8 is further multiplexed. PX1 is the emitter follower type multiplex circuit explained in FIG. PX2 is obtained by removing the emitter follower pair and the load resistor pair from the collector dot type multiplex circuit described with reference to FIG. 8, so that it can be further connected to the next stage emitter follower type multiplex circuit PX3. The combination of an emitter follower type multiplex circuit and a collector dot type multiplex circuit allows data bus lines to be divided into multiple stages. For example, the first stage emitter follower type multiplex circuit PX1 multiplexes the signals of two divided pairs of common collector lines, and the next stage collector dot type multiplex circuit P
At X2, the signals of the two pairs of outputs from the previous stage are multiplexed to perform differential voltage-to-differential current conversion, and are further output to the emitter follower type multiplex circuit PX3 at the next stage. Similar to PX1, PX3 multiplexes the input signals from the two paths and outputs the multiplexed signals to the collector dot type multiplex circuit PX4 at the next stage. PX4 further multiplexes the signals of the two pairs of outputs from the previous stage and connects them to an output buffer via an emitter follower circuit. In this example, two pairs of data are multiplexed in each of the four stages, so the common collector line can be divided into 16 blocks. Furthermore, by increasing the number of data pairs to be multiplexed at each stage to, for example, 4 or 8, the number of divisions of the common collector line can be further increased, and similarly, even if the number of division stages is increased to 2 or 3, the common collector The number of line divisions can be increased. By using this division method,
Since the data bus line hierarchy can be increased freely, data bus lines can be divided by optimizing the data bus hierarchy in consideration of signal delay time and layout. Since signal delay can be reduced, access time can be increased.

[Embodiment 11] FIG. 11 shows a base potential control circuit which is another embodiment of the present invention. MOS when not selected
By applying a "Hi" level non-selection signal to the gates of transistors MNB1 and MNB2, the base potential can be lowered to a non-selection level (a potential lower than the potential of the base connected to the selected data bus line). It becomes possible to control the base potential for plex. Here, the following measures can be taken to reduce power consumption and increase speed. In order to prevent the base potential from lowering more than necessary, a clamp diode DC1 is provided in parallel with each of the load resistors R1 and R2.

[Embodiment 12] FIG. 12 shows a base potential control circuit which is another embodiment of the present invention. This base potential control circuit includes clamp diodes DC1 and DC2 provided so that the base potential does not fall below a level obtained by subtracting Vbe from the high potential power supply, a MOS transistor MP1 and a load resistor for setting the base potential at the time of selection. RP1
and load resistors RB1 and RB2 for setting the base potential when RP2 is not selected.The operation is as follows. When selected, the MOS transistor MP1 is turned on, and the base potential is set to the selected level by the voltage drop caused by the on-resistance of the MOS transistor MP1 and the respective load resistors RP1 and RP2 connected in series with the MOS transistor MP1, and when not selected, the base potential is set to the selected level. M.O.S.
When transistor MP1 is turned off, a load resistor RP connected in series with the on-resistance of MOS transistor MP1
The base potential can be controlled by setting it to a level lower than the base potential in the selected state due to the voltage drop caused by the resistors RB1 and RB2 having a resistance value greater than the sum of the resistance values of 1.

[Embodiment 13] FIG. 13 shows an embodiment of a data bus division method using the multiplex circuit of the present invention. Data lines DL1 and DL2 that transmit data from memory cells are connected to common data lines CD1 and CD2 via transfer MOS transistors MY1 and MY2. Data on CD1 and CD2 is obtained by multiplexing signals from a plurality of data lines using a plurality of transfer MOS transistors. Next, a method of multiplexing data on the common data line will be explained. As a circuit that controls the potential of the common data line to "Hi" level when selected and to "Lo" level when not selected,
MOS transistors MPP1 and MPP for pull-up
2 and pull-down MOS transistors MNP1 and M
As shown in the figure, NP2 is connected to MPP1, MNP1 and MP
P2 and MNP2 are each connected in series to form two inverters, and the outputs of these inverters are connected to common data lines CD1 and CD2, respectively. With this configuration, the inverter selects the potential of the common data line by outputting the "Hi" level and "Lo" level, respectively, in response to the select signal that is "Lo" level when selected and "Hi" level when not selected. Sometimes “Hi”
level, and can be controlled to "Lo" level when not selected. Here, in order to suppress the potential difference between selection and non-selection,
By providing diodes DP1 and DP2 in parallel with the pull-up MOS transistor, the "Lo" level is prevented from falling below the level obtained by subtracting Vbe from the high potential power supply VCC. Each of the plurality of common data line pairs is connected to the respective bases of bipolar transistor pairs QF1 and QF2 of the same number as the common data line pairs, and the respective emitters of the bipolar transistor pairs QF1 and QF2 are connected to the common emitter line pairs CE1 and CE2.
is connected to. Common emitter line pair CE1 and CE2
By connecting MOS transistors ME1 and ME2, multiplexing in an emitter follower type can be achieved.

Furthermore, by using the collector dot type data multiplexer circuit as described in the eighth embodiment, it is possible to divide the common emitter line pair.

[Embodiment 14] FIG. 14 shows a case where the multiplex circuit of the present invention is applied to a BiCMOS SRAM which is an example of a semiconductor memory, taking as an example a sense system from a memory cell to an output pad. B1 is a memory array consisting of a plurality of memory cells connected to a pair of data lines, and corresponds to a (column) of the memory array. W1 and W2 are word lines for selecting (rows) from a group of memory arrays arranged in parallel. For example, when the word line W2 is selected, a pair of transfer MOS transistors MT2 in the same memory array is turned on, and the data in the memory cell CM2 is transferred to each transfer MOS transistor M2.
It is transmitted to data lines DL1 and DL2 via T2. MY1 and MY2 are transfer MOS transistors called Y switches, and these MOS transistors have Y switches.
A control signal for selecting (column) is input from S1. B2 is a data bus line called a common data line. A plurality of data lines are connected to the common data lines CD1 and CD2 via the aforementioned Y switch. The signals of data lines DL1 and DL2 are transferred to the common data line CD1 of the next stage.
In order to transmit the signal to Y switches MY1 and MY2, a "Lo" level signal for selecting a column is input to the gate YS1 of Y switches MY1 and MY2, and MY1 and MY2 are turned on, and DL1 and DL2, CD1 and CD2 are Just connect. By turning on the Y switch of only the selected (column) in this way, it becomes possible to multiplex signals from a plurality of data lines and transmit one signal to the common data line. B3 is a differential voltage-differential current conversion circuit called a pre-sense amplifier. QS1 and QS2 are bipolar transistors for level shifting within the pre-sense amplifier. These bipolar transistors QP1
A differential pair is formed by QP2 and MOS transistors MP1 and MP2 that serve as current sources. The collectors of bipolar transistors QP1 and QP2 are connected to data bus lines called common collector lines CC1 and CC2. A plurality of collectors, which are the outputs of the aforementioned pre-sense amplifiers, are connected to the common collector lines CC1 and CC2. In order to multiplex the outputs of the plurality of pre-sense amplifiers mentioned above, the current sources of the pre-sense amplifiers are controlled to be turned on or off. If the current source of the pre-sense amplifier that outputs the selected data is activated and current flows, and the other current sources are cut off, the differential pair will not operate, so multiplex operation can be performed. Of the MOS transistors MP1 and MP2, which are the current sources of the differential pair described above, MP2 is a constant current source, and MP1 is switched by the control signal YSP to realize multiplex operation. B4 is an emitter follower type multiplex circuit. Common collector lines CC1 and CC2 are input to the bases of bipolar transistors Q1 and Q2, respectively. B5 is a base potential control circuit. The operations of the emitter follower type multiplex circuit and the base potential control circuit have been described in the embodiment shown in FIG. 9, and will therefore be omitted. The output of the multiplex circuit of B4 is transmitted to EO1 and EO2, and is input to the collector dot type multiplex circuit of B6. The operation of B6 has been explained in the embodiment shown in FIG. 8, so it will be omitted here. The data multiplexed and amplified by B6 is input to the output buffer of B8 via the emitter follower circuit of B7. The data level-converted by the output buffer of B8 is output to the output pad.

[Embodiment 15] When the present invention is applied to a BiCMOS SRAM which is a semiconductor memory, a pre-sense amplifier (differential voltage-differential current conversion circuit) is connected from the data line.
Examples of the data buses up to now will be described. Figure 1
5, common data lines CD00 and CD01 are connected to transfer MOS transistors MY0 and MY1 called Y switches from a plurality of data lines DL00 and DL01, etc.
This is a data bus that multiplexes data by, etc. Common data lines CD00 and CD01 are connected to the bases of bipolar transistors QPE0 and QPE1, their collectors are connected to a high potential power supply, and their emitters are connected to common data lines CD00 and CD01, which are data bus lines of the next stage. Furthermore, the common data lines CE0 and CE1 connect to a control node NCO whose potential is controlled by a selection signal via pull-up MOS transistors MPU0 and MPU1.
The potential of the common data lines CD00 and CD01 is controlled by the potential of the control node.

FIG. 16 shows a potential control circuit. A selection signal, which is a decode signal, is input to YDS, and a power supply for a constant current source is connected to VIE. In the selected state, a low potential "Lo" level signal, which is a selection signal, is input to YDS, so P
type MOS transistor M1 is turned on, and the N type MOS transistor M1 is turned on.
The S transistor M2 is turned off and the control node NC is connected to the high potential power supply. On the other hand, in the non-selected state, YDS
Since a high potential “Hi” level signal is input to the P-type MO
The S transistor M1 is turned off, and the N-type MOS transistor M2 is turned on. Since the N-type MOS transistor M3 is always on, the potential of the control node NC is lowered by the N-type MOS transistors M2 and M3, but the potential of the control node NC is lower than the high potential power supply voltage by V.
When the voltage decreases by eb, the voltage of Veb is applied to the diode DP, which turns on the control node NC.
The potential does not fall below a potential that is Veb lower than the high potential power supply voltage. Further, the control node NC is connected to a low potential power supply via N-type MOS transistors M4 and M5, and a selection signal YDS is input to the gate of the N-type MOS transistor M4.
The inverted signal of YDS is input to the gate of 5. Therefore, no current normally flows through the N-type MOS transistors M4 and M5. The inversion signal is inverted by inputting the selection signal YDS to a CMOS inverter composed of a P-type MOS transistor IPM and an N-type MOS transistor INM. Here, by increasing the channel length or narrowing the channel width of the N-type MOS transistor INM, the threshold value of the N-type MOS transistor INM is set high, and the selection signal YDS is raised from the low potential "Lo" level. Potential “Hi”
``By increasing the delay when switching to the level, the N-type MOS transistor M4 is transiently activated during the inverter's delay time when switching from the selected state to the non-selected state.
and M5 are both turned on, and the potential of the control node NC quickly drops to a potential lower than the high potential power supply voltage by Veb. In this potential control circuit, an N-type MOS transistor M
The conductance of the control node NC is reduced to make the steady current in the non-selected state a minute current, and at the moment of switching from the selected state to the non-selected state, the potential of the control node NC is suddenly lowered by Veb than the high potential power supply voltage which is the non-selected level. By doing so, we aim to reduce power consumption.

FIG. 17 shows common emitter lines CE0 and CE1, which are data bus lines next to the common data line. Bipolar transistors QPE0 and QPE1 are prepared whose bases are connected to the common data lines CDOO and CDO1, their collectors are connected to a high potential power supply, and their emitters are connected to the common emitter line as an output. The potential of the common data line is controlled by the potential control circuit shown in Figure 16, by making the potential of the selected common data line higher than the potential of the unselected common data line. Only the data on the common data line with the selected potential is transmitted, allowing multiplex operation. The common emitter line becomes the input of the pre-sense amplifier.

The multiplex operation using the common emitter line shown in this embodiment is effective for high-speed access because the parasitic capacitance is smaller than the multiplex operation using collector dots in which collectors, which are the outputs of pre-sense amplifiers, are connected together. be.

[0053] The above description has been made by taking a typical embodiment of the present invention as an example, but the present invention is not limited thereto, and can be applied to a memory or an internal bus installed in a microprocessor.
Furthermore, it can be applied to large computers, LANs, etc.

[0054]

[Effects of the Invention] According to the multiplex circuit of the present invention, it is possible to operate up to a power supply voltage of about 2.0V, and data bus lines such as common collector lines can be divided, and delay time in these data bus lines is reduced. Therefore, the speed of semiconductor integrated circuit devices can be increased. Further, it has the effect of reducing power consumption in the multiplex circuit.

[Brief explanation of drawings]

FIG. 1 is a schematic circuit diagram showing an embodiment of an emitter follower type multiplex circuit of the present invention.

FIG. 2 is a schematic circuit diagram showing a modification of the emitter follower type multiplex circuit of the present invention.

FIG. 3 is a schematic circuit diagram showing another modification of the emitter follower type multiplex circuit of the present invention.

FIG. 4 is a schematic circuit diagram showing yet another modification of the emitter follower type multiplex circuit of the present invention.

FIG. 5 is a schematic circuit diagram showing different modifications of the emitter follower type multiplex circuit of the present invention.

FIG. 6 is a schematic circuit diagram showing different embodiments of current extraction means.

FIG. 7 is a schematic circuit diagram showing another embodiment of the current source circuit.

FIG. 8 is a schematic circuit diagram showing an embodiment of the collector dot type multiplex circuit of the present invention.

FIG. 9 is a schematic circuit diagram showing an embodiment in which an emitter follower type multiplex circuit and a pre-sense amplifier circuit of the present invention are combined.

FIG. 10 is a schematic circuit diagram showing an embodiment in which an emitter follower type multiplex circuit and a collector dot type multiplex circuit of the present invention are combined.

FIG. 11 is a schematic circuit diagram showing an embodiment of an emitter follower type multiplex circuit of the present invention having a base voltage control circuit.

FIG. 12 is a schematic circuit diagram showing a modification of the emitter follower type multiplex circuit of the present invention having a base voltage control circuit.

FIG. 13 is a schematic circuit diagram showing a data bus division method using the multiplex circuit of the present invention.

FIG. 14 is a schematic circuit diagram showing a sensing system from a memory cell to an output pad of a semiconductor memory using the multiplex circuit of the present invention.

FIG. 15 is a schematic circuit diagram showing a data line from a data line of a semiconductor memory to a pre-sense amplifier using the multiplex circuit of the present invention.

FIG. 16 is a schematic circuit diagram showing a data line from a data line of a semiconductor memory to a pre-sense amplifier using the multiplex circuit of the present invention.

FIG. 17 is a schematic circuit diagram showing a data line from a data line of a semiconductor memory to a pre-sense amplifier using the multiplex circuit of the present invention.

FIG. 18 is a schematic circuit diagram showing a memory to which the present invention is applied.

FIG. 19 is a schematic circuit diagram showing a conventional multiplex circuit.

[Explanation of symbols]

T11, T12...first power supply terminal, T21, T22...second power supply terminal, IN1, IN2...input terminal, OUT...output terminal, Q11, Q12...bipolar transistor, M
11, M12...MOS transistor, B1, B2...current extraction means, R11, R12...resistor, SI...current source circuit, VCC...high potential power supply, VEE...low potential power supply.

Claims (20)

[Claims] Claim 1: A first power terminal, a second power terminal, an input terminal, a select terminal, a collector as the first power terminal, an emitter as the second power terminal, and a base as the input terminal. bipolar transistors connected to each other, and a MOS whose source and drain are connected to a first power supply terminal and a control node, respectively, and whose gate is connected to a select terminal.
Each first power source includes a plurality of basic circuits each including a transistor, a resistance element connected between an input terminal and a control node, and a current drawing means for drawing current from the control node when the MOS transistor is in an off state. The terminals are connected to a first power supply, each second power supply terminal is connected to a second power supply having a lower voltage than the first power supply via a current source circuit, and each second power supply terminal is connected to a current source circuit. A multiplex circuit characterized in that a connection point of is used as an output point. 2. The multiplex circuit according to claim 1, wherein the resistance element of each basic circuit is a MOS transistor whose source and drain are respectively connected to the second power supply terminal and the control node. 3. According to claim 1, a diode is connected between the first power supply terminal of each basic circuit and the control node, the forward direction of which is from the first power supply terminal to the control node. multiplex circuit. 4. The multiplex circuit according to claim 1, wherein a resistor is connected between the first power supply terminal of each basic circuit and the control node. 5. The multiplex circuit according to claim 3, wherein a resistor is connected in series to the MOS transistor of each basic circuit. [Claim 6] Claim 1, Claim 2, Claim 3, Claim 4
Or the multiplex circuit according to claim 5, wherein the current extraction means is a MOS transistor. [Claim 7] Claim 1, Claim 2, Claim 3, Claim 4
6. The multiplex circuit according to claim 5, wherein the current drawing means is a series connection circuit of a first MOS transistor that is turned on and off by a signal from a select terminal and a second MOS transistor that is always on. [Claim 8] Claim 1, Claim 2, Claim 3, Claim 4
Alternatively, in claim 5, the circuit comprises a series connection circuit with a first MOS transistor, and the gate of the first MOS transistor is directly connected to the select terminal, and the gate of the second MOS transistor is connected to the select terminal via an inverter. Features a multiplex circuit. Claim 9: Claim 1, Claim 2, Claim 3, Claim 4
6. The multiplex circuit according to claim 5, wherein the current extraction means is a bipolar transistor. 10. In claim 1, claim 2, claim 3, claim 4, claim 5, claim 6, claim 7, claim 8 or claim 9, the current source circuit is a bipolar transistor. A multiplex circuit characterized by: 11. In claim 1, claim 2, claim 3, claim 4, claim 5, claim 6, claim 7, claim 8 or claim 9, the current source circuit is a MOS transistor. A multiplex circuit characterized by: 12. Claim 1, claim 2, claim 3, claim 4, claim 5, claim 6, claim 7, claim 8 or claim 9, wherein the current source circuit is connected to the select terminal. A multiplex circuit characterized in that it is a series connection circuit of a first MOS transistor that is turned on and off by a signal and a second MOS transistor that is always on. 13. At least a bipolar transistor;
Consisting of a MOS transistor and a resistance element, 2
A multiplexer for selecting one or more output signals less than the number of input signals from one or more inputs, the signal being input to the base of the first bipolar transistor;
One end of the resistance element is connected to the base of the first bipolar transistor, the other end is connected to the control node, the drain of the MOS transistor is connected to the control node, and the MOS transistor is connected to the control node.
The source of the S transistor is connected to the high potential power supply side, and includes four basic circuits each having current extraction means for extracting charge between at least a control node and the base of the first bipolar transistor, and each basic circuit The collector of the first bipolar transistor is connected to the high potential power supply side, the emitters of the first bipolar transistors are connected to each other by forming two basic circuits as a pair, and the emitter node where the emitters are connected is connected to the low potential power supply side. 1. A multiplex circuit, characterized in that current source circuit means for flowing a current to is connected between at least an emitter node and a low potential power supply node, and the emitter node is used as an output. 14. In claim 13, the first bipolar transistor input signals of the two unpaired basic circuits have their emitters connected to the low potential power supply node via the second current source circuit means. A multiplex circuit characterized in that the signal is from the collectors of two second bipolar transistors. 15. A first power terminal, a second power terminal,
An even number of input terminals, an even number of output terminals less than the number of input terminals, each collector is connected to a separate output terminal in pairs, each emitter is connected in common, and each base is connected to a separate output terminal. A number of bipolar transistors equal to the number of input terminals connected to the input terminals, a first MOS transistor connected between the commonly connected emitters of each bipolar transistor and a second power supply terminal, and each output terminal A multiplex circuit comprising: a resistance element connected between a first power supply terminal; and a second MOS transistor connected between each input terminal and a second power supply terminal. 16. A first power supply terminal, a second power supply terminal connected to a power supply lower than the first power supply terminal, an even number of input terminals, and an even number of output terminals less in number than the input terminals. ,
Each collector is connected in pairs to the first power supply terminal through a separate resistor, each emitter is connected in common, and each base is connected to a separate input terminal, as many as the number of input terminals. a first bipolar transistor, a first MOS transistor connected between the commonly connected emitters of each bipolar transistor and a second power supply terminal, and a first MOS transistor connected between each output terminal and the first power supply terminal. a second MOS transistor connected between each input terminal and the second power supply terminal; each collector connected to the first power supply terminal; and each emitter connected to each output terminal. , a number of second bipolar transistors equal in number to the number of output terminals, each base of which is connected to each collector of the paired first bipolar transistor, and each emitter of the second bipolar transistor connected to each collector of the second bipolar transistor and a second power terminal. and a third MOS transistor connected between the multiplex circuits. 17. A first power terminal, a second power terminal connected to a power source lower than the first power terminal, an even number of input terminals, an output terminal, and a base connected to the input terminal, a plurality of differential voltage-to-differential current conversion circuits each comprising a differential pair comprising two first bipolar transistors whose emitters are commonly connected; and a current source means connected to the emitters of the differential pair; , a data bus line pair to which a plurality of collector pairs of bipolar transistors, which are the outputs of the differential voltage-differential current conversion circuit, are connected, and two MOSs connected to each bus line in the intermediate part of the data bus line pair. transistor and
A resistor element connected between each bus line of the data bus line pair and a first power supply terminal between two MOS transistors, a collector connected to the first power supply terminal, and a base connected to the second power supply terminal.
The two MOS transistors are connected to each bus line of the data bus line pair between the two MOS transistors, and the emitters are connected to the output terminals.
A multiplex circuit comprising: a second bipolar transistor; and current source means connected between the emitter of the second bipolar transistor and a second power supply terminal. 18. A large number of memory arrays each having a plurality of memory cells are divided into a predetermined number of memory array groups, and selected data is extracted from each memory array group through the same number of pre-sense amplifiers. In the device in which selected data is further extracted from the data via a multiplex circuit, the multiplex circuit has a first power supply terminal, a second power supply terminal, an input terminal, a select terminal, and a collector. A bipolar transistor whose emitter is connected to a first power terminal, whose emitter is connected to a second power terminal, and whose base is connected to an input terminal, whose source and drain are connected to the first power terminal and a control node, and whose gate is connected to a select terminal. A plurality of basic circuits each including a MOS transistor connected to the MOS transistor, a resistance element connected between the input terminal and the control node, and a current drawing means for drawing current from the control node when the MOS transistor is in an off state, Each first power supply terminal is connected to the first power supply, each second power supply terminal is connected to a second power supply having a lower voltage than the first power supply through a current source circuit, and each second power supply terminal is connected to a second power supply having a lower voltage than the first power supply through a current source circuit. A semiconductor integrated circuit device characterized in that a connection point between the current source circuit and the current source circuit is used as an output point. 19. A large number of memory arrays each having a plurality of memory cells are divided into a predetermined number of memory array groups, and selected data is extracted from each memory array group through the same number of pre-sense amplifiers. In the device in which selected data is further extracted from the data via a multiplex circuit, the multiplex circuit connects a first power terminal, a second power terminal, an even number of input terminals, and an input terminal. A small number of even output terminals and a number of input terminals in which each collector is connected to a separate output terminal in pairs, each emitter is connected in common, and each base is connected to a separate input terminal. the same number of bipolar transistors, a first MOS transistor connected between the commonly connected emitters of each bipolar transistor and a second power supply terminal, and a first MOS transistor connected between each output terminal and the first power supply terminal. What is claimed is: 1. A semiconductor integrated circuit device comprising: a resistive element; and a second MOS transistor connected between each input terminal and a second power supply terminal. 20. A large number of memory arrays each having a plurality of memory cells are divided into a predetermined number of memory array groups, and selected data is extracted from each memory array group through the same number of pre-sense amplifiers. In the device for further extracting selected data from the data via a multiplex circuit, the multiplex circuit includes a first power supply terminal and a second power supply terminal connected to a power supply lower than the first power supply terminal. , an even number of input terminals, an even number of output terminals whose number is smaller than the number of input terminals, and each collector is connected to the first power supply terminal in pairs through a separate resistor, and each emitter is connected to the first power supply terminal through a separate resistor. a number of first bipolar transistors equal to the number of input terminals, each of which is connected in common and whose base is connected to a separate input terminal, and between the commonly connected emitter of each bipolar transistor and a second power supply terminal. a resistor element connected between each output terminal and the first power supply terminal, and a second MOS transistor connected between each input terminal and the second power supply terminal. and a number equal to the number of output terminals connected to each collector of the paired first bipolar transistors, each collector connected to the first power supply terminal, each emitter connected to each output terminal, and each base connected to each collector of the paired first bipolar transistor. A semiconductor integrated circuit device comprising a second bipolar transistor and a third MOS transistor connected between each emitter of the second bipolar transistor and a second power supply terminal.