JPH04321308A - Field effect transistor with internal matching circuit - Google Patents

Abstract

PURPOSE:To increase input and output impedance, to reduce a loss in an external matching circuit and to attain high output and broad band for the infernal matching circuit by providing metallized patterns to the circuit asymmetrically. CONSTITUTION:Two FET chips 2, an input side matching circuit ceramic board 3 and an output side matching circuit ceramic board 4 are mounted on a package 1. Matching circuit metallized patterns 5, 6 are formed on the ceramic boards 3, 4 and the metallized patterns 5, 6 are not horizontally symmetrical with respect to input and output axes A-B, but lambda/4 lines 7, 8 are added to one metallized pattern in comparison with the other metallized pattern. An RF signal applied to an input side external lead 10 is driven while being branched into the two chips and the signal inputted with a phase difference of 180 deg. by the lambda/4 line is subject to further phase difference of 180 deg. by the lambda/4 line of the output pattern 6 of the chip 2, resulting that the signal is in phase and then the RF signals are synthesized at an output side external lead 11.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor, and more particularly to a high output field effect transistor with an internal matching circuit for use in the microwave band.

0002

2. Description of the Related Art As shown in the plan view of FIG. 2, a field effect transistor (FET) for use in the microwave band has metallized patterns 5, Ceramic substrates 3 and 4 on which an internal matching circuit 6 is formed are built-in. The input/output impedance of the FET is made high (ideally 50Ω) to facilitate impedance matching using an external matching circuit, so that sufficient performance can be obtained.

[0003] Metallized patterns 5 and 6 for internal circuit matching
Both the input side and the output side are symmetrical with respect to the input/output axis. An even number of FET chips are electrically connected in parallel to achieve high output.

0004

[Problems to be Solved by the Invention] The metallization pattern on the ceramic substrate for the internal circuit matching circuit is symmetrical, and an even number of FET chips are electrically connected in parallel.

As the output becomes higher, the input/output impedance decreases, and the loss in the external matching circuit increases.
This impedes higher output and wider bandwidth.

[0006]

[Means for Solving the Problems] A field effect transistor with an internal matching circuit of the present invention includes an even number of field effect transistor chips and ceramic substrates for impedance matching on the input side and output side in a package. The output-side impedance matching metallization pattern has a configuration in which one metallization pattern has a λ/4 line added to the other metallization pattern with respect to the input/output axis.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the plan view of FIG.

Two FET chips 2, a ceramic substrate 3 for an input matching circuit, and a ceramic substrate 4 for an output matching circuit are mounted on a package 1.

Matching circuit metallized patterns 5 and 6 are formed on the ceramic substrates 3 and 4. Input/output axis A
-B, the metallized patterns 5 and 6 are not symmetrical, and one metallized pattern has λ/4 lines 7 and 8 added to the other metallized pattern.

The FET chip 2 and matching circuit metallized patterns 5 and 6 are connected by bonding wires 9.

The RF signal applied to the input external lead 10 is branched into two chips 2 and driven. The signal input with a 180° phase difference through the λ/4 line is sent to the FET.
1 more by the λ/4 line of output pattern 6 of chip 2
An 80° phase difference occurs, and eventually they become in phase, and the RF signals are synthesized at the output external lead 11.

0012

Effects of the Invention In the impedance matching metallized patterns on the input and output sides, one pattern has a structure in which a λ/4 line is added to the other pattern with respect to the input/output axis.

As a result, in RF operation, an even number of FEs
This is equivalent to T chips electrically connected in series,
Input/output side dynamic impedance increases. External matching becomes easier and matching loss is reduced. Output characteristics and broadband characteristics are significantly improved.

Furthermore, the addition of the λ/4 line has the effect of reducing interference between input and output.

[Brief explanation of drawings]

FIG. 1 is a plan view showing an embodiment of the present invention.

FIG. 2 is a plan view showing the internal structure of a field effect transistor according to the prior art.

[Explanation of symbols]

1 FET package 2 FET chip 3 Ceramic substrate for input side matching circuit 4
Ceramic substrate for output side matching circuit 5 Metallized pattern for input side matching circuit 6 Metallized pattern for output side matching circuit 7 Input side λ/4 line 8 Output side λ/4 line 9 Bonding wire 10 Input side external lead 11 Output side external lead

Claims (1)

[Claims] 1. A field effect transistor in which an even number of field effect transistor chips and ceramic substrates for input side and output side impedance matching are mounted on a ground plane inside a package, wherein the input side and output side impedance matching circuit The metallized pattern for impedance matching on the ceramic substrate for use is not plane symmetrical with respect to the input/output axis, and the metallized pattern on one side of the input/output axis has a configuration in which a λ/4 line is added to the metallized pattern on the other side. A field effect transistor characterized by: