JPH0432100A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To execute the read-out operation and the deciding operation without being subjected to undesirable influence even if a failure bit line exists by providing a fuse which can disable the operation of a sense amplifier, provided between each sense amplifier and driving signal lines for driving these sense amplifiers. CONSTITUTION:Each sense amplifier 51, 52 - has all a pair of pull-up transistors 514, 515 and a pair of pull-down transistors 516, 517. Also, between a connecting point of the pull-up transistors 514, 515 of each sense amplifier 51, 52 - and one driving signal line SEN, a fuse 513 is provided, respectively. Each sense amplifier 51, 52 is operated by receiving signals phi51, phi52 through the driving signal line SEN, the fuse 513 and a driving signal line SEN#, respectively. In such a way, even if the failure bit line exists, the read-out operation and the deciding operation can be executed without being subjected to undesirable influence by interrupting the fuse.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device that can perform operational tests at high speed.

[Conventional technology]

There has been remarkable progress in semiconductor memory devices in recent years, and RA
M (random access memory), ROM (read memory)
Only memory) and other types of memory have been steadily increasing their density by four times every three years. As a result, the time required to test the operation of devices is increasing, and there is a need to establish a faster test mode in order to efficiently perform shipping inspections on the manufacturer's side and acceptance inspections on the user side. Conventionally, in order to perform operational tests at high speed under such circumstances, a so-called parallel test mode in which a plurality of bit lines are tested in parallel has been adopted, for example, in DRAMs (dynamic random access memories). In this parallel test mode, the same data is written to multiple bits at the same time, and a signal representing the data written to each memory cell is transmitted to each pair of bit lines by a plurality of sense amplifiers provided for each pair of bit lines. Amplify on the bit line, output the amplified signal, and read each data in parallel. Then, the data is compared and if there is even one difference in data, it is determined that the product is defective.

[Problem to be solved by the invention]

However, the traditional parallel test mode is approximately IM
The reality is that the test time for x I DRAM is not exceeded. Therefore, the purpose of this invention is to be able to test one line (approximately 1024 bits or 2048 bits in practice) in parallel, and therefore to perform operation tests at high speed, and even if there is a defective bit line, Another object of the present invention is to provide a semiconductor memory device that can perform read operations and determination operations without being adversely affected.

[Means to solve the problem]

In order to achieve the above object, the semiconductor memory device of the first invention writes the same data in parallel to a plurality of memory cells via each pair of bit lines that operate complementary to each other, and writes the same data in parallel to each of the memory cells. A semiconductor memory capable of amplifying signals representing data on each pair of bit lines by a plurality of sense amplifiers provided for each pair of bit lines, outputting the amplified signals, and reading each data in parallel. The device includes a line data storage circuit that outputs an expected value signal representing data written in a specific memory cell via a bit line connected to the memory cell, and a line data storage circuit that receives the expected value signal from the line data storage circuit. a bit line selection circuit that selects one or the other bit line of a pair of bit lines of a memory cell other than the memory cell, depending on the level of the expected value signal; When the expected value signal is at a high level, the bit line selection circuit outputs a signal that is written to the memory cell of the above function in parallel with the above function, and when the expected value signal is at a high level, the signal that should represent the same data as the expected value signal written to the specific memory cell is When the expected value signal is at a low level, it is detected through the other bit line selected by the bit line selection circuit, and the signal and the expected value are detected via the other bit line selected by the bit line selection circuit. an output determination circuit that outputs a signal indicating coincidence or mismatch with the signal; and a drive signal line that drives each of the sense amplifiers and the sense amplifiers;
It is characterized by comprising a fuse that can disable the operation of the sense amplifier. Further, the semiconductor memory device of the second invention writes the same data in parallel to a plurality of memory cells via each pair of bit lines that operate in a complementary manner, and outputs a signal representing the data written to each of the memory cells. A semiconductor memory device capable of amplifying data on each pair of bit lines by a plurality of sense amplifiers provided for each pair of bit lines, outputting the amplified signals, and reading each data in parallel, a line data storage circuit that outputs an expected value signal representing data written in a memory cell via a bit line connected to the memory cell; and a line data storage circuit that receives the expected value signal from the line data storage circuit and processes the expected value signal. A bit line selection circuit that selects one or the other bit line of a pair of bit lines of a memory cell other than the above memory cell depending on the level of the above memory cell, and a bit line selection circuit that operates the above function in parallel with the above specific memory cell. A signal that is written in a memory cell and should represent the same data as the expected value signal written in the specific memory cell is selected by the bit line selection circuit when the expected value signal is at a high level. On the other hand, when the expected value signal is at a low level, it is detected through the other bit line selected by the bit line selection circuit to determine whether the signal matches or does not match the expected value signal. an output determination circuit that outputs a signal representing the output determination circuit; a transistor that can conduct or electrically separate the output terminal of the output determination circuit from the pair of human lines of the memory cell having the above-mentioned capacity; and the output determination circuit that outputs the signal representing the coincidence. A semiconductor memory device characterized by comprising: a division circuit that turns on the transistor when a signal is output, and turns off the transistor when the output determination circuit outputs a signal representing the mismatch.

[Operation] The semiconductor memory device of the first invention operates as follows. The data written to a specific memory cell has a logic level “
In the case of B, the expected value signal outputted by the line data storage circuit is at a high level. At this time, the output determination circuit detects a signal representing the same data as the data written in the other memory cell via one of the hit lines selected by the bit line selection circuit. The one bit line is at either high or low level representing the signal. The output determination circuit outputs a signal representing whether the signal matches or does not match the expected value signal to the output terminal, depending on whether the detected level is high or low. For example, if one of the above bit lines becomes low level when a memory cell with the above function is read normally, a signal indicating a match is output when the detected level is low, while a signal indicating a match is output when the detected level is low. A signal indicating a mismatch is output when the level is high. On the other hand, when the data written in a specific memory cell is at logic level "0", the expected value signal outputted by the line data storage circuit is at a low level. At this time, the output judgment circuit is
A signal representing the same data as the data written in another memory cell is detected via the other hint line selected by the bit line selection circuit. To explain in conjunction with the previous example, when the sense amplifier on the line connected to the memory cell of the above function operates normally and the read of the memory cell of the above function is performed normally, the above signal is inverted. Therefore, the other human line is at a low level. Here, the output determination circuit outputs a signal indicating a match when the detected level is a low level, and outputs a signal indicating a mismatch when the detected level is a high level. Therefore, the output determination circuit outputs a signal indicating a match when the other memory cell is read normally, and outputs a signal indicating a mismatch when the read is erroneous. In this way, the output determination circuit determines whether the same data simultaneously written to the specific memory cell and the other memory cell is at logic level "0" or "1". A signal indicating a match is output when the memory cell is read normally, and a signal indicating a mismatch is output when the read from the other memory cell is erroneous. Generally, one row of memory cells can be selected simultaneously by one word line. Therefore, while causing the bit line selection circuit to simultaneously select one or the other of each pair of bit lines of one row of memory cells in parallel,
By operating the output determination circuit simultaneously for each memory cell, one row of memory cells can be tested simultaneously. Therefore, operational tests can be performed quickly. Further, when the reading of the other memory cell is erroneous, the fuse between the sense amplifier that amplified the signal representing the data of the other memory cell and the drive signal line is cut. Then, the sense amplifier becomes inoperable, and from then on, the bit line (
(defective bit line) no longer participates in operation. therefore,
Even if there is a defective bit line, the read operation and determination operation will not be adversely affected. A semiconductor memory device according to a second aspect of the present invention is characterized in that, in place of the fuse of the semiconductor memory device according to the second aspect of the present invention, the pair of bit lines of the other memory cell and the output terminal of the output determination circuit are connected or electrically connected. a control circuit that turns on the transistor when the output judgment circuit outputs the signal representing the blasphemy, and turns off the transistor when the output judgment circuit outputs the signal representing the blasphemy. It is equipped with The other components have the same configuration as the semiconductor memory device of the first invention. Therefore, like the semiconductor memory device of the first aspect of the invention, this semiconductor memory device can simultaneously test one row of memory cells and perform operational tests at high speed. In this case, when the bit line connected to the other memory cell is a defective bit line, the transistor is turned off, thereby electrically separating the bit line and the output terminal. Therefore, even if there is a defective bit line, the read operation and determination operation will not be adversely affected.

【Example】

Hereinafter, the semiconductor memory device of the present invention will be explained in detail with reference to examples. FIG. 1 shows a DRAM according to an embodiment of the first invention. This DRAM includes a line data storage circuit 1, a bit line selection circuit 2, an output determination circuit 3, a memory cell array 4, and a sense amplifier array 5 consisting of sense amplifiers 51, 52, and so on. The memory cell array 4 includes one row of memory cells 41, 42, . . . that are simultaneously selected by one word line WL. ···have. memory cell 41
42 are each pair of human lines B, B# and BL that operate complementary to each other.
Data is written and read via BL#. It should be noted that only the bit lines B and BL of each pair of bit lines are actually connected to the memory cells 41 and 42. The sense amplifier array 5 includes sense amplifiers 51
,52. A pair of drive signal lines SEN, S that drive...
EN# is provided. Each sense amplifier 51, 52. ... have a pair of pull-up transistors 514 and 515 and a pair of pull-down transistors 516 and 517,
The connection point of the pull-up transistors 514, 515 of each sense amplifier 5], 52... and one drive signal line SEN
Fuses 513 are provided between the two. Each sense amplifier 5I52 is connected to the drive signal line SEN.
, fuse 513 and drive signal line SEN# to operate in response to signals φ51 and φ52. That is, the signal φ
51 is pulled up to the power supply level, and the signal φ52 is pulled up to GND.
When brought down to the level, Brua. By the functions of pull-down transistors 514, 5]5 and pull-down transistors 516, 517, the voltage between the hit lines B and B# and between BL and BL# is amplified. The line data storage circuit l is controlled by the signal φ11.
It includes an Mo5 transistor 11, inverters 12 and 13 connected in antiparallel, and NMO3 transistors 14 and 15 controlled simultaneously by a signal φ12. Then, the data represented by the input signal DIN is sent to the bit line B. It is possible to write into the memory cell 41 via B# and output the signal DIN#, which is an inverted version of the input signal DIN, to the bit line selection circuit 2. Further, the data written in the memory cell 41 is read out as an expected value signal E, and this signal E is inverted to produce a signal E#.
It can be outputted to the bit line selection circuit 2 as follows. The bit line selection circuit 2 includes AND circuits 21 and 22 that receive the signal φ21, and the AND circuit 2.
The inverter 23 is connected between the input terminals of 1.22. Then, the signal DIN# from the line data storage circuit 1 receives the expected value signal E#, and each signal DIN# receives the expected value signal E#.
A pair of selection signals S and S# for selecting bit line BL or BL# of the memory cell 42 is output depending on the level of IN# and E#. The output determination circuit 3 is 1/
PM connected between the power supply set to 2Vcc level and the output line DOUT and controlled on/off by signal φ32
It includes an OS transistor 32 and an NMO transistor 35 connected between the output line DOUT and ground. NMO9) The gate of the transistor 35 is connected in parallel to the human lines BL and BL# via the NMOS transistor 3334. The NMOS transistors 33 and 34 receive selection signals S and S from the hit line selection circuit 2, respectively.
Controlled by S#. Further, this output determination circuit 3 is connected between the gate of the NMOS transistor 35 and the ground, and is connected to a signal φ31.
The NMOS transistor 31 is controlled by the NMOS transistor 31. This DRAM operates as follows based on the operation timing shown in FIG. Note that the broken lines in FIG. 2 indicate the timing of the write operation, and the solid lines indicate the timing of the read operation. First, the write operation will be explained. In the precharge state (the leftmost state in the operation timing shown in FIG. 2), bit lines B, B#: BL, BL#,
... are all charged to the l/2Vcc level. Then, the signal φ21 is at the low (L) level, the outputs of the AND circuits 21 and 22 of the bit line selection circuit 2 are both at the L level, and therefore the NMOS transistors 33 and 34 of the output determination circuit 3 are both non-conductive. It is in a state. Further, the signal φ31 is at a high (H) level, and the signal φ32 is at an L level. PMOS transistor 32 is turned on in response to signal φ32, and output line DOUT is charged to 1/2vCC level. When the write operation begins, the human input signal DTH is given either an H or L level depending on the input data. and,
When signal φ11 rises, NMOS transistor 11 of line data storage circuit 1 becomes conductive, and input signal DIN is latched by inverters I2 and I3. After that, when the signal φ21 rises to the H state,
When input signal DIN is at H level, that is, when DIN# is at L level, selection signals S and S# are at L level and H level, respectively. Therefore, NMOS transistor 34 becomes conductive, and bit line BL# is pulled down to GND level. On the other hand, since the NMOS transistor 33 is in a non-conductive state, the hit line BL remains at the level of the original precharged state. On the other hand, input signal D
When IN is at L level, that is, signal DIN# is at H level, selection signals S and S# are at H level and L level, respectively. Therefore, the NMO9) runnostar 33 becomes conductive, and the bit line BL is pulled down to the GND level. On the other hand, since the NMOS transistor 34 is in a non-conductive state, the voltage line BL# remains at the level of the original precharged state. In parallel with this operation on the memory cell 42 side, the signal φ12 rises on the memory cell 41 side, the NMO9) transistors 14 and 15 of the line data storage circuit 1 become conductive, and the input data is transferred to the bit line B, Written to B#. Note that when the input signal DIN is at H level, the bit lines B and B# are at H level and L level, respectively, and when the input signal DIN is at L level, the bit lines B and B# are at L level and H level, respectively. Become. After the word line WL is raised, the sense amplifiers 51.52 of the sense amplifier array 5 output the signals φ51. Driven by φ52,
The levels of bit line pair B, B# and bit line pair BL, BL# are amplified to a level sufficient to be written into memory cells 41 and 42. Finally, the word line WL is brought down, and the memory cell 414
The write operation to 2 ends. In this way, the memory cells 41, 42 .・Identical data is written to simultaneously. Next, a read operation and a determination operation will be explained. When the read operation starts, the word line WL is raised and the sense amplifiers 51 and 52 output the signal φ, as shown in FIG.
51. Driven by φ52, memory cell 41.4
The data written to bit line pair B, B#: bit line pair BL, BL# is read out. moreover,
The signal φ12 is raised, and the expected value signal E representing the data written in the memory cell 41 is outputted to the bit line selection circuit 2 as an inverted signal E#. Then, when entering the determination operation, after the signal φ31 goes to L level and the signal φ32 goes to H level, the signal φ21 rises. Here, when the input data written to the memory cell 41 is logic "B", the expected value signal E is at H level, that is, the signal E
# becomes L level. At this time, selection signals S and S# become L level and H level, respectively. Therefore, the NMOS transistor 34 of the output determination circuit 3 becomes conductive, and the level of the bit line BL# is input to the gate of the NMO3) transistor 35. If reading from the memory cell 42 is performed normally, the data line BL# should be at L level. When data line BL# is at L level,
The L level is applied to the gate of the NMO9) transistor 35, and it remains non-conductive. Therefore, a 1/2 Vcc level indicating a match is output to the output line DOUT. On the other hand, when the reading of the memory cell 42 is erroneous, the data line BL# is at H level. Therefore, the NMOS transistor 35 becomes conductive, and a GND level representing a mismatch is output to the output line DOUT. On the other hand, the data written in the memory cell 4I is at logic “0”.
”, the expected value signal E becomes L level, that is, the signal E# becomes H level. At this time, the selection signals S and S# become H level and L level, respectively. Therefore, the NMo5 transistor 3 of the output determination circuit 3
3 becomes conductive, and the level of the bit line BL is input to the gate of the NMo5 transistor 35. If memory cell 42
If reading is performed normally, the data line BL should be at L level. When the data line BL is at the L level, the NMOS transistor 35 has its gate supplied with the L level and remains non-conductive. Therefore, the output line DOUT has 1/2Vc representing coincidence.
c level is output. On the other hand, memory cell 42
If the reading of the data is incorrect, the data line BL becomes H.
level. The NMOS transistor 35 becomes conductive, and a GND level indicating a mismatch is output to the output line DOUT. In this way, this DRAM has memory cells 41.4
The same human data written at the same time in 2 is at the logical level.
In either case, a signal indicating a match is output when the memory cell 42 is read normally, and a mismatch is output when the memory cell 42 is read incorrectly. Then, by providing the NMO9) random registers 33, 34 and 35 of the output determination circuit 3 for each of the other memory cells (not shown) that are simultaneously selected by the word line WL and operating them simultaneously, one row It is possible to test memory cells for 1 row at the same time. Therefore, the operation test can be performed at high speed. Also, in this DRAM, among the memory cells for one row, for example, the above-mentioned memory cell 42 was read incorrectly. When,
By cutting off the fuse 513 of the sense amplifier 52 that has amplified the signal of the memory cell 42, the sense amplifier 52 can be prevented from operating from now on. If you do this,
Even after the sensing operation is performed, the levels of the bit lines (defective bit lines) BL and BL# do not exceed the original precharge state level (1/2 Vce level). Here, since the power supply is set to the 1/2 Vcc level, the drain voltage of the NMO transistor 35 is below the 1/2 Vcc level. Therefore, the gate voltage and drain voltage become below the 1/2 Vcc level, and the NMOS transistor 35 will not turn on under any circumstances. That is, the defective bit lines BL, BL# and the output line DOUT are always electrically isolated. Therefore, if this DRAM has defective lines BL, B
Even if there is L#, read operations and determination operations can be performed without being adversely affected. It is assumed that the memory cells 41 and 42 are connected to only one bit line B, BL of each pair of bit lines B, B#, BL, BL# that operate complementary to each other. For example, as shown in FIG. 3, this corresponds to the case where the memory cell M is composed of a MOS transistor and a capacitor connected in series, and a cell plate voltage is applied to one terminal of the capacitor. However, the present invention is not limited to this.
As shown in the figure, it is also applicable to the case where the bit lines BL and BL# are connected to both (US Pat. No. 4,792,922). FIG. 6 and FIG. 7 show a DRAM of an embodiment of the second invention.
It shows. As shown in FIG. 6, this DRAM includes a line data storage circuit +01, a bit line selection circuit 102, an output determination circuit 103, a memory cell array 104, sense amplifiers 151, 152 . . . and a control circuit 106 as shown in FIG. The memory cell array 104 includes one row of memory cells 41, 42, . . . that are simultaneously selected by one word line WL.
have. Data is written into and read from the memory cells 41 and 42 via each pair of bit lines B, B#, BL, and BL# that operate complementary to each other. Note that, like the DRAM shown in FIG. 1, only the bit lines B and BL of each pair of bit lines are actually connected to the memory cells 41 and 42. Sense amplifiers 151 and 152 of sense amplifier array +05 are driven by drive signal lines (not shown), and between the bit lines B and B#, respectively;
Amplify the voltage between L and BL#. In addition, sense amplifier 1
51, 152 are the sense amplifiers 51.5 shown in FIG.
Unlike No. 2, this is a normal one that does not have a fuse 513. Line data storage circuit 101 includes an NMOS transistor 11 controlled by signal φ11, inverters 12 and 13 connected in antiparallel, and NMOS transistors 14 and 15 simultaneously controlled by signal φ12. Then, data represented by the input signal DIN is written into the memory cell 41 via the bit lines B and B#, and a signal DIN which is an inversion of the input signal DIN is written into the memory cell 41 via the bit lines B and B#.
# can be output to the bit line selection circuit 102. Further, the data written in the memory cell 41 can be read out as the expected value signal E, and this signal E can be inverted and outputted as the signal E# to the bit line selection circuit 102. The bit line selection circuit 102 receives the signal φ21
and an inverter 23 connected between the input terminals of the AND circuits 21 and 22. Then, the line data storage circuit 101
In response to the signal DIN# or the expected value signal E# from the respective signals D T N#. A pair of selection signals S and S# for selecting bit line BL or BL# of the memory cell 42 is output depending on the level of E#. The output determination circuit 103 is connected to a power source (H
level) and the output line DOUT, and the signal φ32
PMO3+/Runnostar 32 controlled on/off by
and NM connected between the output line DOUT and ground.
It includes an OS transistor 35. One terminal of an NMOS transistor 36 is connected to the gate of the NMOS transistor 35, and the other terminal of the NMOS transistor 36 is connected in parallel to bit lines BL and BL# via a pair of NMOS transistors 33 and 34. . Further, an NMOS transistor 31 is connected between the gate of the NMo5 transistor 35 and the ground. The NMOS transistors 33 and 34 are controlled by selection signals S and S# from the bit line selection circuit 102, respectively, and the NMOS transistor 31 is controlled by the signal φ31.
controlled by On the other hand, the NMOS transistor 35 is controlled by a signal φ36 from the control circuit 6 shown in FIG. The control circuit 6 includes a PMOS transistor 61 . connected in series between a power supply (H level) and ground. Fuse 63 and NMOS transistor 62, and this PM
It consists of an inverter 64 connected to a connection point between an OS transnoster 61 and a fuse 63. The PMOS transistor 61 and the NMOS transistor 63
It is controlled by the same signal φ61 which takes L level when AM is in a precharge state and takes H level when it starts operation. If the fuse 63 is not cut, the PMOS transistor 61 is turned on in the precharge state.
The NMOS transistor 62 is turned off and the inverter 6
4, the signal φ36 goes to L level, and when the operation starts, the PMOS transistor 61 is turned off.
) The run star 62 is turned on and the signal φ36 becomes H level. If fuse 63 is disconnected, signal φ3
6 is always kept at L level. Therefore, the NMOS transistor 36 shown in FIG. 6 is turned off in the precharge state when the fuse 63 is not cut, but turned on when the operation starts. On the other hand, when the fuse 63 is disconnected, it is always in an off state. This DRAM operates as follows based on the same operation timing as shown in FIG. First, the write operation will be explained. In the precharge state (the leftmost state *3 in the operation timing shown in Figure 2), bit lines B, B#, BL, BL#
; and are both charged to 1/2Vcc level. Then, the signal φ21 is at L level, and the bit line selection circuit 1
The outputs of the AND circuits 21 and 22 of 02 are both at the L level, so the NMOS transistors 3334 of the output determination circuit 103 are both non-conductive. Further, the signal φ31 is at H level, and the signal φ32 is at L level. In response to signal φ32, PMO5I-ransistor 3
2 is turned on, and the output line DOUT is charged to H level. Further, as described above, the signal φ36 is at the L level, and the NMOS transistor 36 is turned off. When the write operation begins, the input signal DIN is given an H or L level depending on the input data. and,
When the signal φ]1 rises, the line data storage circuit 10
One NMOS transistor II becomes conductive, and the input signal DIN is latched by inverters 12 and 13. Thereafter, when the signal φ2] rises to the H level, when the input signal DIN is at the H level, that is, when DIN# is at the LL novel, the selection signals S and S# go to the L level and H level, respectively. As a result, the NMOS transistor 34 becomes conductive. Therefore, bit line BL# is pulled down to GND level through NMOS transistor 36, which is turned on in response to signal φ36 at H level, and NMOS (Runnostar) 31, which is turned on since the precharge state. On the other hand, since the NMOS transistor 33 is in a non-conductive state, the bit line BL remains at the level of the original precharged state. On the other hand, input signal D
When IN is at L level, that is, signal DIN# is at H level, selection signals S and S# are at H level and L level, respectively. Therefore, the NMOS transistor 33 becomes conductive, and the focus line BL is pulled down to the GND level. On the other hand, since the NMOS transistor 34 is in a non-conductive state, the hit line BL# remains at the level of the original precharged state. In parallel with this operation on the memory cell 42 side, the signal φ12 is raised on the memory cell 41 side, the NMOS transistor 1415 of the line data storage circuit 1 becomes conductive, and the input data is transferred to the bit lines B and B#. written. Note that when the input signal DIN is at H level, the bit lines B and B# are at H level and L level, respectively, and when the input signal DIN is at L level, the bit lines B and B# are at L level and H level, respectively. Become. After the word line WL is activated, the sense amplifiers 151 and 152 of the sense amplifier array 105 are driven, and the bit line pairs B, B#,
The level of bit line pair BL, BL# is the same as that of memory cells 41, 4.
is amplified to a level sufficient to be written to 2. Finally, word line WL is brought down, and memory cell 41.
The write operation to 42 ends. In this way, the memory cells 41 42 . The same data is written simultaneously. Next, a read operation and a determination operation will be explained. When the read operation starts, as shown in FIG. 2, the word line WL is raised, the sense amplifiers 151 and 152 are driven, and the data written in the memory cells 41 and 42 is transferred to the pit line pair B and B#. , bit line pair BL, BL#, respectively. Further, the signal φ12 is raised, and the expected value signal E representing the data written in the memory cell 41 is outputted to the bit line selection circuit 2 as a signal E# obtained by inverting the expected value signal E. Then, when entering the judgment operation,
After the signal φ31 goes low and the signal φ32 goes high, the signal φ21 rises. Here, when the manual data written in the memory cell 41 is logic "1", the expected value signal E becomes H level, that is, signal E# or L level. At this time, selection signals S and S# are each at L level. , becomes H level. Therefore, the NMOS transistor 34 of the output determination circuit 103 becomes conductive.
The level of bit line BL# is input to the gate of NMOS transistor 35 through NMOS transistor 35 in the on state. If reading from the memory cell 42 is performed normally, the data line BL# should be at L level. When data line BL# is at L level, N
The L level is applied to the gate of the MOS transistor 35, and it remains non-conductive. Therefore, an H level indicating a match is output to the output line DOUT. On the other hand, when the reading of the memory cell 42 is erroneous, the data line BL# is at H level. Therefore, the NMOS transistor 35 becomes conductive, and an L level indicating a mismatch is output to the output line DOUT. On the other hand, the data written in the memory cell 41 is at logic “0”.
”, the expected value signal E becomes L level, that is, the signal E# becomes H level. At this time, the selection signals S and S# become H level and L level, respectively. Therefore, the NMo5 transistor 33 of the output determination circuit 103 is conductive and NMO3I-Runstar 3 is in the on state.
6, the level of the bit line BL is input to the gate of the NMOS transistor 35. If reading from the memory cell 42 was performed normally, the data line BL should be at L level. When the data line BL is at the L level, the NMOS transistor 35 receives the L level at its gate and remains non-conductive. Therefore, an H level indicating a match is output to the output line DOUT. On the other hand, when the reading of the memory cell 42 is erroneous, the data line BL is at H level. The NMOS) lannostar 35 becomes conductive, and an L level indicating a mismatch is output to the output line DOtJT. In this way, this DRAM has memory cells 41.4
The same human data written at the same time in 2 is at the logical level.
In either case, a signal indicating a match is output when the memory cell 42 is read normally, and a mismatch is output when the memory cell 42 is read incorrectly. Outputs a signal representing Then, by providing NMOS transistors 33, 34, 35 and 36 of the output determination circuit +03 for each of the other memory cells (not shown) that are simultaneously selected by the word line WL and operating them simultaneously, one row of memory cells can be simultaneously operated. Can be tested. Therefore, operation tests can be performed at high speed. In addition, this DRAM has an NM which transmits the signal of the memory cell 42 to the output line DOUT when, for example, the reading of the memory cell 42 is erroneous among the memory cells for one row.
The OS transistor 35 can be kept in an off state at all times. That is, by cutting off the fuse 63 of the control circuit 106 shown in FIG. 7 that controls the NMOS transistor 36, the NMOS transistor 36 can be kept in an off state and the NMOS transistor 35 can be prevented from being turned on. . Therefore, the above hint lines (defective focus lines BL, BL#) are connected to the output line DOU.
It can be separated from T. Therefore, even if a defective hint line exists, read operations and determination operations can be performed without being adversely affected. Note that, in place of the control circuit +06, a control circuit 107 may be provided as shown in FIG. This control circuit +0
7 includes a fuse 71 and an NMOS transistor 74 connected in series between a power supply (H level) and the ground, and a PMOS capacitor connected between the power supply (H level) and the gate of the NMOS transistor 74. It is equipped with 73. Fuse 71 and NMO8 above)
An inverter 75 is connected between a connection point 72 with the Ranjistaf 4 and a connection point 77 between the PMCIS capacitor 73 and the gate of the NMOS transistor 74, and an inverter 76 is connected to this connection point 77. The fuses 71 of this control circuit 107, like the fuses 61, are connected to the hit lines B, B#, BL, BL, #:...
If there is no defective bit line in the line, it will not be disconnected, but if there is a defective focus line, it will be disconnected. If fuse 7I is not disconnected, connection point 72 becomes H level after power is turned on, and signal φ36 goes to H level via inverters 75 and 76.
level, and the runnostar 36 is always on as shown in FIG. 6. On the other hand, if fuse 71 is disconnected, NMOS transistor 3 will be disconnected after power is turned on.
6 or always in the off state. Therefore, in the same way as when the DRAM is equipped with the control circuit 106, the bit lines B,
Even if there is a defective bit line among B#; BL and BL#;, read operations and determination operations can be performed without being adversely affected. Furthermore, it is assumed that the memory cells 41 and 42 are connected only to one bit line B and BL of each pair of bit lines E and B#+BL BL# which operate in a complementary manner. The invention is not limited to this, and can also be applied to a memory cell M connected to both bit lines BL and BL# as shown in FIG. 4 or 5.

【Effect of the invention】

As is clear from the above, the semiconductor memory device of the first invention writes the same data in parallel to a plurality of memory cells via each pair of bit lines that operate complementary to each other, and writes the same data in each memory cell in parallel. A semiconductor memory device capable of amplifying a signal representing this data on each pair of bit lines by a plurality of sense amplifiers provided for each pair of bit lines, outputting the amplified signal, and reading each data in parallel. a line data storage circuit that outputs an expected value signal representing data written in a specific memory cell via a human line connected to this memory cell; and a line data storage circuit that receives the expected value signal from the line data storage circuit. , a bit line selection circuit that selects one or the other of a pair of bit lines of a memory cell other than the memory cell, depending on the level of the expected value signal; In parallel, when the expected value signal is at a high level, a signal that is written to the other memory cells and should represent the same data as the expected value signal written to the specific memory cell is selected by the focus line selection circuit. The signal is detected through the selected one bit line, and when the expected value signal is at a low level, it is detected through the other bit line selected by the focus line selection circuit, and the signal and the expected value signal are detected. Since the output determination circuit outputs a signal indicating coincidence or mismatch, one row of memory cells can be tested in parallel, and therefore an operation test can be performed at high speed. In addition, it is equipped with a fuse that can disable the operation of the sense amplifier, so even if there is a defective bit line, reading and determining operations can be performed without any adverse effects by cutting this fuse. . Further, like the semiconductor memory device of the first invention, the semiconductor memory device of the second invention writes the same data in parallel to a plurality of memory cells via each pair of bit lines that operate complementary to each other. A signal representing the data written in each memory cell is amplified on each pair of bit lines by a plurality of sense amplifiers provided for each pair of bit lines, and the amplified signals are output to read each data in parallel. A readable semiconductor memory device comprising: a line data storage circuit that outputs an expected value signal representing data written in a specific memory cell via a bit line connected to the memory cell; a human line selection circuit that receives an expected value signal and selects one or the other of a pair of human lines of a memory cell other than the memory cell, depending on the level of the expected value signal; A signal that is written to the other memory cell in parallel with the specific memory cell and that should represent the same data as the expected value signal written to the specific memory cell, when the expected value signal is at a high level. The detection is performed through one bit line selected by the bit line selection circuit, and when the expected value signal is at a low level, the detection is performed through the other bit line selected by the bit line selection circuit. Since it is equipped with an output determination circuit that outputs a signal indicating whether the signal matches or does not match the expected value signal, one row of memory cells can be tested in parallel, and therefore, an operation test can be performed at high speed. . Further, a transistor capable of conducting or electrically separating the pair of hint lines of the other memory cell and the output terminal of the output determination circuit; On the other hand, the control circuit also includes a control circuit that turns off the transistor when the output determination circuit outputs a signal indicating the mismatch, so even if there is a defective bit line, the read operation can be performed without any adverse effect. A judgment operation can be performed.

[Brief explanation of drawings]

FIG. 1 shows the DR of an embodiment of the semiconductor memory device of the first invention.
FIG. 2 is a diagram showing the operation timing of the DRAM, FIGS. 3, 4, and 5 are diagrams showing the states in which memory cells are connected to bit lines, and FIGS. Figure 7 shows the DR of an embodiment of the semiconductor memory device of the second invention.
FIG. 8, which shows the AM, is a diagram showing a modification of the control circuit of the DRAM. 1.101...Line data storage circuit, 2.102...
・Bit line selection circuit, 3.103... Output determination circuit, 4104... Memory cell array, 5.105 Sense amplifier array, 36... NMOS transistor, 4142... Memory cell, 5] 52 151 152... Sense amplifier, 61
71 513 ・Fuse, B B# BL BL#...Bit line.

Claims (2)

[Claims] (1) The same data is written in parallel to multiple memory cells via each pair of bit lines that operate in a complementary manner, and a signal representing the data written to each memory cell is provided for each pair of bit lines. A semiconductor memory device capable of amplifying data on each pair of bit lines by a plurality of sense amplifiers and outputting the amplified signals to read each data in parallel, representing data written in a specific memory cell. a line data storage circuit that outputs an expected value signal via a bit line connected to the memory cell; and a line data storage circuit that receives the expected value signal from the line data storage circuit and stores the expected value signal in the memory cell according to the level of the expected value signal. a bit line selection circuit that selects one or the other bit line of a pair of bit lines of a memory cell other than the memory cell; A signal that should represent the same data as the expected value signal written in the memory cell is detected via one of the bit lines selected by the bit line selection circuit when the expected value signal is at a high level; an output determination circuit that detects when the expected value signal is at a low level through the other bit line selected by the bit line selection circuit and outputs a signal indicating whether the signal matches or does not match the expected value signal; . A semiconductor memory device, comprising a fuse that is provided between each of the sense amplifiers and a drive signal line for driving the sense amplifiers, and is capable of disabling the operation of the sense amplifier. (2) The same data is written in parallel to multiple memory cells via each pair of bit lines that operate in a complementary manner, and a signal representing the data written to each memory cell is provided for each pair of bit lines. A semiconductor memory device capable of amplifying data on each pair of bit lines by a plurality of sense amplifiers and outputting the amplified signals to read each data in parallel, representing data written in a specific memory cell. a line data storage circuit that outputs an expected value signal via a bit line connected to the memory cell; and a line data storage circuit that receives the expected value signal from the line data storage circuit and stores the expected value signal in the memory cell according to the level of the expected value signal. a bit line selection circuit that selects one or the other bit line of a pair of bit lines of a memory cell other than the memory cell; A signal that should represent the same data as the expected value signal written in the memory cell is detected via one of the bit lines selected by the bit line selection circuit when the expected value signal is at a high level; an output determination circuit that detects when the expected value signal is at a low level through the other bit line selected by the bit line selection circuit and outputs a signal indicating whether the signal matches or does not match the expected value signal; , a transistor capable of conducting or electrically separating the pair of bit lines of the other memory cell and the output terminal of the output determination circuit, and turning on the transistor when the output determination circuit outputs a signal indicating the coincidence. and a control circuit that turns off the transistor when the output determination circuit outputs a signal representing the mismatch.