JPH03260999A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To test memory cells simultaneously and in a short time by reading out a signal written on the memory cell via a bit line on the other side, outputting a signal representing coincidence/noncoincidence with an expected value, and separating a defective bit line. CONSTITUTION:An H level signal representing the coincidence with an expected value signal is outputted to an output line DOUT when the readout of memory 42 is performed normally even when the same input data written on the memory cells 41, 42 simultaneously are set at either a logic level 0 or 1. Also, when the readout of the memory 42 is performed erroneously, an L level signal representing the noncoincidence is outputted. Then, the cells of one row are tested simultaneously by operating an output decision circuit 3 simultaneously at every another memory cell selected by a word line WL simultaneously. Also, the bit line connected to a defective cell is separated from an output line by melting a fuse 36. In such a way, it is possible to test the memory cells of one row simultaneously and in a short time.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device that can perform operational tests at high speed.

<Conventional technology> There has been remarkable progress in semiconductor memory devices in recent years, and RA
M (random access memory), ROM (read memory)
Only memory) and other types of memory have been steadily increasing their density by four times every three years.

As a result, the time required to test the operation of devices is increasing, and there is a need to establish a faster test mode in order to efficiently perform shipping inspections on the manufacturer's side and acceptance inspections on the user side.

Conventionally, under such circumstances, in order to perform operation tests at high speed, for example, DRAM (dynamic random
Access memory) uses a so-called parallel test mode in which multiple bit lines are tested in parallel. In this parallel test mode, the same data is simultaneously written to a plurality of bits, the data at the time of reading ζ is compared, and if there is even one different data, it is determined that the bit is defective.

<Problem to be solved by the invention> However, the conventional parallel test mode
The reality is that the test time for xlDRAM is not exceeded.

Therefore, the purpose of this invention is to be able to test one line (approximately 1024 bits or 2048 bits in practice) in parallel, and therefore to be able to perform operational tests at a high speed of 3, while also eliminating the presence of defective bit lines. The object of the present invention is to provide a semiconductor memory device that can sometimes disconnect the defective bit line.

Means for Solving the Problems> In order to remotely achieve the above object, the semiconductor memory device of the present invention writes the same data in parallel to a plurality of memory cells via each pair of bit lines that operate complementary to each other. A readable semiconductor memory device comprising: a line data storage circuit that outputs an expected value signal representing data written in a specific memory cell via a bit line connected to the memory cell; a bit line selection circuit that receives an expected value signal and selects one or the other of a pair of bit lines of a memory cell other than the memory cell, depending on the level of the expected value signal; A signal that is written to the other memory cell in parallel with the specific memory cell and should represent the same data as the expected value signal written to the specific memory cell is transmitted when the expected value signal is at a high level. The signal is detected through one bit line selected by the bit line selection circuit, and when the expected value signal is at a low level, is detected through the other bit line selected by the bit line selection circuit. and (ii) an output determination circuit that outputs a signal representing coincidence or mismatch with the expected value signal to an output terminal connected to the output line, and a pair of bit lines of the other memory cell and the output terminal of the output determination circuit. It is characterized by having a phase that can be separated.

Effect〉 The data written to a specific memory cell has a logic level “
1", the expected value signal output by the line data storage circuit is at a high level. At this time, the output determination circuit selects a bit signal that should represent the same data as the above data written in other memory cells. Detection is performed via one bit line selected by the line selection circuit.The one bit line is at either a high or low level representing the output signal.The output determination circuit determines whether the detected level is high or low. A signal indicating whether the above-mentioned signal and the above-mentioned expected value match or do not match is output to the output terminal depending on the level of the above-mentioned expected value.For example, when the above-mentioned other memory cell is read normally, the above-mentioned one bit When the line becomes a low level, a signal indicating a match is output when the detected level is low, and a signal indicating a mismatch is output when the detected level is high.

On the other hand, when the data written in a specific memory cell is at logic level "0", the expected value signal outputted by the line data storage circuit is at a low level. At this time, the output judgment circuit is
A signal representing the same data as the data written in another memory cell is detected via the other bit line selected by the bit line selection circuit. To explain in conjunction with the previous example, when the other memory cell is read normally, the other bit line becomes low level because the signal is inverted. Here, the output determination circuit outputs a signal indicating a match when the detected level is a low level, and outputs a signal indicating a mismatch when the detected level is a high level. Therefore, the output determination circuit outputs a signal indicating a match when the memory cell in the upper half is read normally, and outputs a signal indicating a mismatch when the read is erroneous. In this way, the output determination circuit determines that the same data written simultaneously in the specific memory cell and the upper memory cell is at logic level "0".
In either case, a signal indicating a match is output when the memory cell on the upper muddy area is successfully read, and a mismatch is output when the reading of the memory cell on the muddy area is incorrect. Outputs a signal representing .

Generally, one row of memory cells can be selected simultaneously by one word line. Therefore, the bit line selection circuit (1) simultaneously selects one or the other of each pair of bit lines of one row of memory cells in parallel, and the output determination circuit operates simultaneously for each memory cell. This makes it possible to test the memory cells for one row at the same time. Therefore, operational tests can be performed quickly.

Further, by separating the bit line connected to the memory cell whose read was erroneous from the output terminal of the output determination circuit depending on the phase, data of the memory cell connected to the bit line can be prevented from being output. Therefore, even if a defective bit line exists, one row of memory cells can be simultaneously tested in a short time.

<Example> Hereinafter, the semiconductor memory device of the present invention will be explained in detail with reference to an example.

FIG. 1 shows a DRAM according to an embodiment of the present invention.

This DRAM includes a line data storage circuit 1, a bit line selection circuit 2, and an output determination circuit 3. 4 indicates a memory cell array, and 5 indicates a sense amplifier 51.52
It shows a sense amplifier array consisting of... The memory cell array 4 includes one row of memory cells 41, 42 . . . which are simultaneously selected by one word line WL. ·have. Data is written into and read from the memory cells 41 and 42 via each pair of bit lines B, B#; BL, BL# which operate complementary to each other. Note that only the bit lines B and BL of each pair of bit lines are actually connected to the memory cell 4142. The sense amplifiers 5152 of the sense amplifier array 5 amplify the voltage between the bit lines B and B#: BL and BL#. The line data storage circuit 1 includes an NMOS transistor 11 controlled by a signal φ11, inverters 12 and 13 connected in antiparallel, and an NMOS transistor 11 controlled simultaneously by a signal φ12.
It includes transistors 14 and 15. Then, data represented by the input signal DIN can be written into the memory cell 41 via the bit lines B and B#, and a signal DIN# obtained by inverting the human input signal DIN can be output to the bit line selection circuit 2. . Further, the data written in the memory cell 41 can be read as the expected value signal E, and this signal E can be inverted and output as the signal E# to the bit line selection circuit 2. The bit line selection circuit 2 includes AND (A N D ) circuits 21 and 22 that receive a signal φ21, and an inverter 23 connected between the input terminals of the AND circuits 21 and 22. Then, in response to the signal DIN# or the expected value signal E# from the line data storage circuit 1, the bit line B of the memory cell 42 is
A pair of selection signals S and S# to select L or BL#
Output. The output judgment circuit 3 connects the power source and the output wire DOU.
A PMOS transistor 32 connected between the output line DUT and the ground is connected between the output line DUT and the ground. NMOS transistor 35 and output line DOUT
A phase 36 is connected between them. Therefore, this phase 36 can separate the output terminal of the output determination circuit 3 connected to the output line DOUT from the NMOS transistor 35 and, furthermore, from the pair of bit lines BL and BL#.

The gate of the NMO8) transistor 35 is connected in parallel to the bit lines BL and BL# via NMO8) transistors 33 and 34. The above NMOS transistor 33.34
are controlled by selection signals S and S# from bit line selection circuit 2, respectively.

Further, this output determination circuit 3 is connected between the gate of the NMOS transistor 35 and the ground, and is connected to a signal φ31.
The NMOS transistor 31 is controlled by the NMOS transistor 31. This DRAM operates as follows based on the operation timing shown in FIG. Note that the broken lines in FIG. 2 indicate the timing of the write operation, and the solid lines indicate the timing of the read operation.

First, the write operation will be explained.

Precharge state (i at the operation timing shown in Figure 2)
In the leftmost state), the signal φ21 is at the low (I, ) level, and the outputs of the AND circuits 21 and 22 of the bit line selection circuit 2 are both at the level ■.Therefore, the NMOS transistor 3334 of the output determination circuit 3 is is also in a non-conducting state. Further, the signal φ31 is at a high (H) level, and the signal φ32 is at an L level.

When the write operation starts, the input signal DIN changes to H or L level depending on the input data. Then, the signal φII rises and the line data storage circuit 1
NMO8) transistor 11 becomes conductive, and input signal DIN is latched by inverters 12 and 13. After that, when the signal φ21 rises to the H state, the input signal DTN goes to the I level, that is, DIN# goes to the L level.
In the case of the level, the selection signals S and S# are respectively L level and H
level. Therefore, NMO8) transistor 34
becomes conductive, and the bit line B L # is pulled down to the GND level. On the other hand, the NMOS transistor 33
Since is in a non-conductive state, the bit line BL remains at its original precharge state level (normally a level of 1/2 Vcc is used). On the other hand, input signal D
When IN is at L level, that is, signal DIN# is at H level, selection signals S and S# are at H level and L level, respectively. Therefore, the NMO8) transistor 33 becomes conductive, and the bit line BL is lowered to the GND level. On the other hand, since the NMOS transistor 34 is in a non-conductive state, the bit line BL# remains at the level of the original 1 2 precharge state.

In parallel with this operation on the memory cell 42 side, the signal φ■2 is raised on the memory cell 41 side, the NMOS transistors 14 and 15 of the line data storage circuit 1 become conductive, and the incoming data is transferred to the bit line B. , B#. Note that when the input signal DIN is at H level, the bit lines B and B# are at H level and L level, respectively, and when the input signal DIN is at L level, the bit lines B and B# are at H level and L level, respectively.
are 1. Level: H level. Word line WL
is turned on, the sense amplifier 5152 of the sense amplifier array 5 is driven, and the levels of the bit line pair BB#; bit line pair BL, BL# are amplified to a level sufficient to be written to the memory cell 4142. be done. Finally, the word line WL is brought down, and the write operation to the memory cell 4.1.42 is completed. In this way, the memory cell 414 is connected via each pair of bit lines BB# and BLBL#.
The same data is written to 2, . . . at the same time.

Next, the read operation and determination operation will be explained.

When the read operation starts, as shown in FIG. 2, the word line WL is raised, the sense amplifier 5152 is driven, and the data written in the memory cells 41 and 42 is transferred to the bit line pair B, B#, The bit line pairs BL and BL# are respectively read out. Furthermore, the signal φ12 is raised,
Expected value signal E representing data written in memory cell 41 is inverted and output to bit line selection circuit 2 as signal E#. Then, when entering the determination operation, after the signal φ31 goes to L level and the signal φ32 goes to H level,
Signal φ21 is raised.

Here, when the input data written to the memory cell 41 is logic "1", the expected value signal E becomes the H level, that is, the signal E# becomes the L level. At this time, selection signals S and S# become L level and H level, respectively. Therefore, the NMOS transistor 34 of the output determination circuit 3 becomes conductive, and the level of the bit line BL# is input to the gate of the NMOS transistor 35. If reading from the memory cell 42 is performed normally, the data line BL# should be at L level. When data line BL# is at L level, NMOS transistor 35 has its gate supplied with L level and remains non-conductive. therefore,
An H level indicating a match is output to the output line DOUT. On the other hand, when the reading of the memory cell 42 is erroneous, the data line BL# is at H level. Therefore, the NMOS transistor 35 is conductive and
An L level indicating a mismatch is output on the output line DOUT.

On the other hand, the data written in the memory cell 41 is at logic “0”.
”, the expected value signal E,')<L level, that is, the signal E# becomes H level.At this time, the selection signals S, S
# becomes H level and L level, respectively.

Therefore, the NMOS transistor 3 of the output determination circuit 3
3 becomes conductive, and the level of bit line BL is input to the gate of NMOS transistor 35. If memory cell 42
If reading is performed normally, the data line BL should be at L level. When data line BL is at L level, L level is applied to the gate of NMOS transistor 35, and it remains non-conductive. Therefore, an H level indicating a match is output to the output line DOUT. On the other hand, when the reading of the memory cell 42 is erroneous, the data line BL is at H level. The NMOS) transistor 35 becomes conductive, and an L level indicating a mismatch is output to the output line DOUT.

In this way, this DRAM has memory cells 41.4
The same human data written at the same time in 2 is at the logical level.
Regardless of whether it is "0" or "1", a signal indicating a match is output when the memory cell 42 is read normally, and a mismatch is output when the memory cell 42 is read incorrectly. By providing the NMOS transistors 3334 and 35 of the output determination circuit 3 and the phase 36 for each of the other memory cells (not shown) that are simultaneously selected by the word line WL and operating them simultaneously, 1. Fifteen memory cells corresponding to a row can be tested simultaneously. Therefore, an operation test can be performed at high speed.

In addition, the bit line connected to the memory cell for which reading was erroneous among the memory cells for one row is phase 36.
By cutting , it can be separated from the output line DOUT. Therefore, even if a defective bit line exists, one row of memory cells connected to the same word line WL can be simultaneously tested in a short time.

It is assumed that the memory cells 4] and 42 are connected only to one bit line B, BL, respectively, of each pair of bit lines B, B#, PL, BL# that operate complementary to each other. For example, as shown in FIG. 3, this case corresponds to the case where the memory cell M is laterally squeezed by a MOS transistor and a capacitor connected in series, and a cell plate voltage is applied to one terminal of the capacitor. However, the present invention is not limited to this.
As shown in the figure, it can also be applied to the case where the bit lines BL and BL# are connected to both (see US Pat. No. 4,796,2922).

Further, in the above embodiment, the phase 36 is connected between the NMOS transistor 35 and the output line DOUT, but the connection position of the phase 36 is not limited to this, and it may be connected as shown in FIGS. 6 and 7. good. The one shown in Fig. 6.7 differs from Fig. 1 only in the connection position of the phases.
The rest is exactly the same as in Figure 1. Phase 3 shown in Figure 6
6 has one end connected to the gate of the NMOS transistor 35, and the other end connected to the bit lines BL and BL#.

In addition, the one shown in FIG. 7 uses two phases 36, one of which is connected to the gate of the NMOS transistor 35 and the other is connected to the gate of the NMOS transistor 35.
) transistor 33, and the other is connected between the gate of the NMOS) transistor 35 and the NMOS) transistor 34. The point is that it is sufficient if the pair of bit lines BL and BL# can be separated from the output horn line DOUT.

<Effects of the Invention> As is clear from the above, the semiconductor memory device of the present invention outputs an expected value signal representing data written in a specific memory cell via a bit line connected to this memory cell. A line data storage circuit receives the expected value signal from the line data storage circuit, and depending on the level of the expected value signal, selects one of the bit lines of the memory cell other than the above memory cell or A bit line selection circuit that selects the other bit line, and a bit line selection circuit that is written to the above memory cell in parallel with the above specific memory cell, and should represent the same data as the expected value signal written to the above specific memory cell. A signal is detected via one bit line selected by the bit line selection circuit when the expected value signal is at a high level, while the signal is detected via one bit line selected by the bit line selection circuit when the expected value signal is at a low level. an output determination circuit that detects via the other bit line and outputs a signal representing coincidence or mismatch between the signal and the expected value signal to an output terminal connected to the output line; and a pair of bits in the memory cell described above. Since it is provided with a phase that can separate the line and the output terminal of the output determination circuit, one line can be tested in parallel, and therefore, the operation test can be performed at high speed.

In addition, the bit line connected to the memory cell that was read incorrectly can be separated from the output line by cutting the phase, so even if there is a defective bit line, one row of memory cells can be tested at the same time. If you can and want to do it, you can shorten the test time.

[Brief explanation of drawings]

FIG. 1 shows a DRA of an embodiment of the semiconductor memory device of the present invention.
FIG. 2 is a diagram showing the operation timing of the DRAM, FIG. 3, FIG. 4, and FIG. 5 are diagrams showing states in which memory cells are connected to bit lines, and FIG. 6, FIG. FIG. 7 is a diagram showing a DRAM as a modification of the semiconductor memory device of the present invention. DESCRIPTION OF SYMBOLS 1... Line data storage circuit, 2... Bit line selection circuit, 3... Output determination circuit, 4...
Memory cell array, 5...Sense amplifier array, 36...Fukose 41
42...Memory cell, 51.52...Sense amplifier, B, B#, BL, BL#...Bit line.

Claims (1)

[Claims] (1) A semiconductor memory device that can write and read the same data in parallel to multiple memory cells via each pair of bit lines that operate in a complementary manner, with an expected value representing the data written to a specific memory cell. A line data storage circuit that outputs a signal via a bit line connected to this memory cell, and a line data storage circuit that receives the expected value signal from the line data storage circuit and selects a memory cell other than the above memory cell depending on the level of the expected value signal. a bit line selection circuit that selects one or the other bit line of a pair of bit lines of the other memory cell; and a bit line selection circuit that writes to the other memory cell in parallel with the specific memory cell, A signal that should represent the same data as the expected value signal written in the expected value signal is detected via one of the bit lines selected by the bit line selection circuit when the expected value signal is at a high level. When the signal is at a low level, it is detected via the other bit line selected by the bit line selection circuit, and a signal indicating whether the signal matches or does not match the expected value signal is output to an output terminal connected to the output line. A semiconductor memory device comprising: an output determination circuit; and a phase capable of separating a pair of bit lines of the other memory cell from an output terminal of the output determination circuit.