JPH0432063A - Joint recording circuit device for video tape recorder - Google Patents

Abstract

PURPOSE:To perform smooth joint recording by generating a delay trapezoidal wave signal which has the phase delayed by the phase difference between a reproduced control signal and a capstan FG frequency divided signal in the assembling mode and sampling this generated signal as the signal to be sampled to generate a capstan phase error signal. CONSTITUTION:A phase difference detecting part 2 which detects the phase difference between the capstan FG frequency divided signal and the reproduced control signal in the assembling mode and a delay means 3 which delays the phase of the capstan trapezoidal wave signal to generate the delay trapezoidal wave signal are provided. A sampling and holding circuit 5 is provided which samples the trapezoidal wave signal by the reproduced control signal in the assembling mode and uses the delay trapezoidal wave signal as the signal to be sampled to generate the capstan phase error signal after switching to the recording mode. Thus, the phase deviation of the capstan phase error signal between the assembling mode and the recording mode is eliminated to perform smooth joint recording.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a video tape recorder (hereinafter referred to as VTR).
This invention relates to a continuous shooting circuit device.

[Prior Art] When performing splicing operation on a VTR, in order to match the so-called track phase at the splice of recorded information, after recording stops, the recording tape is slightly returned in the opposite direction to the transport direction to align the recording stop point with the next one. A so-called assemble mode is adopted in which the deviation from the recording start point is controlled on a servo mechanism.

When transitioning from this assemble mode to a recording mode in which information is recorded on a magnetic tape, the transition of the sampling point that determines the phase error of the capstan motor is performed by resetting the capstan FG frequency division signal using the playback control signal. .

[The invention or the problem to be solved] Somehow, the capstan F is activated by the playback control signal.
The method of resetting the G-divided signal has the problem that, in principle, a phase shift occurs depending on the capstan FG frequency, and smooth continuous shooting cannot be performed.

The present invention has been made to solve these problems, and an object of the present invention is to provide a VTR continuous shooting circuit device that can perform smooth continuous shooting when transitioning from an assemble mode to a recording mode.

[Means for Solving the Problems] The present invention includes a phase difference detection unit that detects a phase difference between a capstan FG frequency division signal and a reproduction control signal for sampling the FG frequency division signal in an assemble mode. , a delay means for creating a delayed FG frequency division signal by delaying the phase of the cab scan FG frequency division signal regarding the phase difference sent out by the phase difference detection section, and a reproduction control of the FG frequency division signal which is the sampled signal in the assemble mode. A sample hold function that samples the signal and creates a capstan phase error signal, and after transitioning to recording mode, uses the delayed FG divided signal as the sampled signal and samples the capstan frequency signal to create a capstan phase error signal. It is characterized by comprising a circuit.

[Operation] In the assemble mode, the sample and hold circuit samples the FG frequency divided signal, which is the sampled signal, using the reproduction control signal to create a capstan phase error signal. The phase difference detection section detects the rising edge of the capstan FG frequency division signal and the FG signal in the assemble mode.
The delay means detects a phase difference between the frequency-divided signal and the reproduction control signal that samples the frequency-divided signal, and the delay means delays the phase of the FG frequency-divided signal supplied from the phase difference detection section so that the phase difference supplied from the phase difference detection section is eliminated. Create a frequency-divided signal in advance.

Therefore, after shifting from the assemble mode to the recording mode, the sample and hold circuit samples the delayed FG frequency divided signal at the rising edge of the pulse of the capstan FG frequency divided signal to generate a capstan phase error signal. There is no phase shift in the capstan phase error signal between the assemble mode and the record mode. Therefore, the above-mentioned components function so that smooth continuous shooting can be performed.

Furthermore, since the above-mentioned components do not reset the capstan frequency signal with the reproduction control signal, they act so that a phase shift depending on the capstan FG frequency does not occur.

[Embodiment] In FIG. 1 showing an embodiment of the splicing circuit device of the present invention, the single-handed contact 7a of the switch 7 is supplied with a reproduction control signal supplied from the magnetic tape during reproduction, and other inputs are Contact point 7b has a capstan F that divides the capstan frequency signal sent from the capstan motor.
A frequency-divided signal sent out by the G frequency divider 6 is supplied. Such a switch 7 connects an output line to the input contact 7a side in the assemble mode in response to a mode switching signal sent by a control section 8 constituted by a microcomputer, for example, and when the assemble mode shifts to the recording mode. An output line is connected to the input contact 7b side. The output side of such a switch 7 is connected to a sample and hold circuit 5.

Further, the output side of the cab scan FG frequency divider 6 is connected to the other input side of an AND circuit 23 to which a high (H) level signal is supplied to one input terminal only in the assemble mode. Therefore, the AND circuit 23 sends out an H level signal to the latch circuit 22 in synchronization with the rising edge of the pulse signal supplied from the capstan FG frequency divider 6 in the assemble mode.

The output side of the counter 21, which counts clock pulses supplied using the reproduction control signal as a reset signal, is connected to a latch circuit 22 which latches the supplied count value with a signal supplied from an AND circuit 23. Ru. That is, the latch circuit 22 latches the count value supplied from the counter 21 at the time when an H level signal is supplied from the AND circuit 22 in the assemble mode as described above. The output side of such a launch circuit 22 is supplied with a latched count value, and a delay circuit that delays the phase of the FG frequency division signal supplied from the CabScun FG frequency division signal generation circuit 1 by a time corresponding to this count value. Connected to means 3. Note that the counter 21, latch circuit 22, and AND circuit 23 described above form the phase difference detection section 2.

The single-handed contact 4a of the switch 4 is connected to the output side of a capstan FG frequency division signal generation circuit 1 which has a known configuration and generates an FG frequency division signal from which a phase shift is detected. On the other hand, the other input contact 4b of the switch 4 has
The output side of the delay circuit 3 described above is connected. In such a switch 4, the output line is connected to the input contact 4a side in the assemble mode, and the output line is connected to the input contact 4b side when the assemble mode shifts to the recording mode, according to a mode switching signal sent from the control unit 8. be done.

The output side of such a switch 4 is connected to a sample and hold circuit 5.

The operation of the continuous shooting circuit device configured as described above will be described below. Furthermore, the operation of the assemble mode itself,
Known techniques are used for the control method of the rotating drum system, the creation of the capstan FG frequency division signal, and the like. That is, the capstan FG frequency division signal is adjusted and delayed by the playback control signal in the assemble mode so that when the center point of the slope portion of the FG frequency division signal is sampled, a normal tracking state is achieved. do.

The control section 18 sends a mode switching signal to the switches 4 and 7 according to the assemble mode or the recording mode. Therefore, in the assemble mode, switches 4 and 7 are
The mode switching signal allows switching to the contact 4a side and the contact 7a side, respectively.

Therefore, the second signal sent from the FG frequency division signal generation circuit 1
The FG frequency-divided signal shown in FIG. Further, the sample bold circuit 5 is supplied with a reproduction control signal shown in FIG. 2 obtained by reproducing the magnetic tape through the contact 7a of the switch 7.

Therefore, as shown in FIGS. 2a and 2b, the sample-and-hold circuit 5 samples and holds the slope portion 10 of the FG frequency-divided signal according to the reproduction control signal to create a capstan phase error signal in the assemble mode.

Further, in the assemble mode, the counter 21 counts clock signal pulses that are also supplied, which are reset by the supplied reproduction control signal, and sends the counted value to the latch circuit 22. Furthermore, since it is in the assemble mode, an H level signal is supplied to one input terminal of the AND circuit 23. and sends an H level signal to the latch circuit 22.

Therefore, as shown in FIGS. 2A and 2C, after the latch circuit 22 is reset by the reproduction control signal,
When a signal is supplied from the ND circuit 22, that is, when the capstan FG frequency division signal rises, the count value is latched and the count value is sent to the delay means 3. Incidentally, as shown in FIGS. 2A and 2C, the above count value corresponds to the phase difference between the reproduction control signal shown in FIG. 2S and the capstan FG frequency division signal shown in FIG. 2C.

The delay means 3 outputs a second signal corresponding to the supplied count value.
For the time t shown in FIG. C, the phase of the FG frequency division signal supplied from the FG frequency division signal generation circuit 1 is delayed as shown in FIG.
The signal is sent to the input contact 4b.

Next, when shifting from the assemble mode to the recording mode, a mode switching signal is supplied from the control section 8 to the switches 4 and 7, and the switches 4 and 7 switch the contacts from the contacts 4a and 7.
Switch from a to contacts 4b and 7b, respectively.

Therefore, in the recording mode, the sample hold circuit 5
, the delayed FG frequency-divided signal sent from the delay means 3 is supplied as a sampled signal via the contact 4b of the switch 4, and the capstan FG frequency-divided signal is supplied from the capstan FG frequency divider 6 to the switch 7. is supplied via the contact 7b. Therefore, as shown in FIG. 2C and d, the sample-and-hold circuit 5 samples and holds the slope portion 11 of the delayed FG frequency-divided signal at the rising edge of the capstan FC frequency-divided signal, thereby creating a new capstan phase in the recording mode. Create an error signal.

Note that the transition from the assemble mode to the recording mode described above is executed after the servo system is locked in the assemble mode, and the phase difference detected by the phase difference detection section 2 is latched immediately before the mode transition due to its configuration. The count value latched by the circuit 22 becomes valid.

In this way, in the assemble mode, the sample and hold circuit samples the FG frequency divided signal, which is the sampled signal, using the reproduction control signal to create a capstan phase error signal.

And when transitioning from assemble mode to recording mode,
The phase difference detection section 2 and the delay means 3 delay the phase of the FG frequency division signal by the phase difference between the reproduction control signal and the capstan FG frequency division signal before the mode transition, and create a delayed FG frequency division signal.

And after transitioning to recording mode, this delayed FG
The frequency-divided signal is sent to the sample-and-hold circuit 5 as a sampled signal. The sample and hold circuit 5 samples the delayed FG frequency division signal at the rising edge of the capstan FG frequency division signal with no change in phase in the assemble mode and recording mode. The phase of will not change. Therefore, smooth continuous shooting can be performed.

Furthermore, since the capstan FG frequency division signal is not reset by the playback control signal as in the past, the phase shift does not depend on the capstan FG frequency, and there is a great advantage that any capstan FG frequency can be selected. Obtainable.

[Effects of the Invention] As described in detail above, according to the present invention, in the assemble mode, the phase difference between the reproduction control signal for sampling the FG frequency divided signal, which is the sampled signal, and the capstan FG frequency divided signal is detected. Then, a delayed FG frequency divided signal whose phase is delayed by the detected phase difference is created, and when transitioning from assemble mode to recording mode, the delayed FG frequency divided signal is used as a sampled signal in assemble mode and recording mode. By creating a capstan phase error signal by sampling with a capstan F'G divided signal with no change in phase, there is no phase shift in the capstan phase error signal when transitioning from assemble mode to recording mode. You can perform smooth continuous shots. Further, since the capstan FG frequency division signal is not reset by the reproduction control signal as in the prior art, the phase shift of the capstan phase error signal does not depend on the capstan FG signal frequency. Therefore, the frequency of the capstan PC signal can be freely set.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the continuous shooting circuit device of the present invention, and FIG. 2 is a time chart showing the operation of the circuit device shown in FIG. 2. Phase difference detection section, 3. Delay means, 4 and 7.-
Switch, 8. Control unit, 21. Counter, 22. Latch circuit, 23. AND circuit.

Claims (1)

[Claims] (1) In the assemble mode, the capstan FG
a phase difference detection section that detects a phase difference between the frequency-divided signal and a reproduction control signal for sampling the trapezoidal wave signal; A delay means for creating a delayed trapezoidal wave signal, and a trapezoidal wave signal, which is a sampled signal, in the assemble mode is sampled using a playback control signal to create a capstan phase error signal, and after transitioning to the recording mode, the delayed trapezoidal wave signal is generated. a sample hold circuit that takes the signal as a sampled signal and samples it with a capstan FG frequency divided signal to create a capstan phase error signal;
A splicing circuit device for a video tape recorder, characterized by comprising: