JPH04319783A - Information processor - Google Patents

Abstract

PURPOSE:To realize a by-pass functin and to simplify the hardware without providing a speical by-pass channel for the data having the destination information different from a self-processor in the multi processor constitution having processors provided with the pipeline constitution and connected serially through each input output control part. CONSTITUTION:The information processor is equipped with a PE# register 1 to set a self-processor number (PE#) and a comparator 2 to compare a destination PE# added to an input packet with a self PE# set at the PE# register 1 by a bit iunit and device the coincidence or noncoincidence at the input control part of each processor, and a through flag 3 to prohibit the processing at each processing part and pass through an input packet as it is provided at the pipeline channel of each processor. When it is shown that the output of the comparator 2 is not for the self-processor, the through flag 3 is set.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to an information processing device having a multi-processor configuration in which each processor has a pipeline configuration and is connected in series via each input/output control unit, and in particular, the present invention relates to an information processing device having a multi-processor configuration in which each processor has a pipeline configuration and is connected in series via each input/output control unit. It is concerned with the processing mechanism of data with .

0002

[Prior Art] This type of information processing device is known as a "data flow type processor LSI aimed at the field of image processing" (
Nikkei Electronics, April 9, 1984 issue, pp1
81-218) is known.

FIG. 4 is a block diagram showing the internal configuration of the data flow type processor described in the above-mentioned document.
Link table LT and function table FT, which are program areas made up of AM, data memory DM, which is an internal memory also made up of RAM, and an arithmetic control unit for generating DM addresses and controlling flow. AG&FC and token buffer FIFO queue Q
It consists of the same output queue OQ, and a processing unit PU that actually performs data calculations. Among these, link table LT, function table FT (calculation control unit AG&FC), data memory DM, queue Q, and processing unit The PU constitutes a ring-shaped variable pipeline. Further, a bypass path is provided from the input control section IC to the output control section OC. In this type of processor, the input bus of the input control unit IC is connected to the output control unit OC of another processor.
By connecting the output buses of , a multiprocessor configuration as shown in FIG. 5 can be easily realized.

The detailed functions and operations of the above-mentioned parts are described in detail in the above-mentioned documents, so they will be omitted here, and the parts related to the present application will be briefly explained. The input control unit IC takes in data called a token (packet) from the outside and inputs the MN (destination module number, also called destination processor number) field and CTL of the token.
The input token is identified using the F (control information) field, and subsequent processing is determined. The input control unit IC has a 4-bit register called the MN register, and the upper 4 bits of data on the input data bus IDB are written into the register as a module number at the time of initial setting. When a token is input from the outside (host or previous processor), the input control unit IC compares the contents of the MN register with the value of the MN field of the token. If the two do not match, the token is transferred to the output control unit OC via the bypass, and the output control unit OC, which includes a merging circuit with the bypass, uses this token as passing data and transfers it to the outside (next stage processor). or host). If there is a match, the token is taken internally and subjected to various processing in the corresponding processing unit according to the contents of the CTLF field.The token that has gone around the pipeline ring several times and completed the specified processing is transferred to the pipeline ring. Output queue OQ,
It is output to the outside (next-stage processor or host) via the output control unit OC.

[0005]

[Problems to be Solved by the Invention] As described above, in a multiprocessor configuration, when data arrives with destination information different from that of its own processor, the conventional device transfers the data from the input control section to the output control section via bypass. was. Therefore, a bypass path is required to connect the input control section and the output control section, and a merging circuit for the bypass path is also required in the output control section, resulting in the problem of complicated hardware.

[0006] Accordingly, an object of the present invention is to realize a bypass function without providing a special bypass path, thereby simplifying the hardware.

[0007]

[Means for Solving the Problems] The present invention includes an input control section that inputs data from the outside, a plurality of processing sections having a pipeline configuration that performs various processing on the input data, and a plurality of processing sections that input data from the processing sections. Information on a multiprocessor configuration in which a plurality of processors each having an output control unit that outputs to the outside are connected in series, and a destination processor number that specifies the processor for processing the data is added to data input from one end of the processor. In the processing device, a setting means sets the own processor number in the input control unit of each processor, and the input data is set based on the destination processor number added to the input data and the own processor number set in the setting means. In addition, a through flag is provided in the pipeline path of each processor to prohibit processing in each processing unit and allow the input data to pass through as is. , the through flag is set when the output of the determining means indicates that it is not addressed to the own processor.

[0008]

[Operation] In the present invention, when data with a different destination processor number arrives, the input control unit sets the through flag attached to the pipeline path, and the input data passes through each processing unit in the pipeline configuration. , In other words, it passes through without any processing and is output to the outside, so the bypass function can be realized without the need for a special bypass path, and the merging circuit in the output control section is also unnecessary, so hardware ware is simplified.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing only the part related to the present application in an input control section of each processor according to an embodiment of the present invention. Note that an input packet input from outside the processor (corresponding to the token described above) has a destination processor number (PE#) for specifying the processor for processing the input packet in a multiprocessor configuration, and control information (CTLF).
) and an instruction code, and a data section that includes operand data to be processed. In the figure, 1 is a PE# register which is a setting means for setting the own processor number, and has the same bit width as the destination PE# added to the input packet. 2 inputs the contents of the PE# register 1 and the destination PE# field of the input packet, compares them bit by bit, and outputs if all bits match, that is, if the input packet is addressed to the own processor. If even one bit does not match, that is, if the input packet is not addressed to the processor itself, the output is set to "1", which corresponds to the determination means of the present invention. 3 is a 1-bit through flag newly installed in the pipeline route in order to prohibit processing of input packets that are not addressed to the own processor in each processing unit in the processor and allow the input packets to pass through. By writing the output of the comparator 2, the through flag 3 is set when the input packet is not addressed to the own processor.

Note that the PE# register 1 and comparator 2
As mentioned above, there are similar devices in conventional devices, so they can be used, but the comparator 2 of this embodiment, for example, as shown in FIG. This can be easily realized using exclusive OR) gates 21 to 2n and an OR gate 20 whose outputs are inputs.

FIG. 3 is a conceptual diagram showing each processing section of the pipeline configuration in this processor. In the figure, 31
32 is a processing unit, and 32 is a decoder that decodes the tag part of the input packet and determines whether or not to perform processing on the input packet, and when processing is performed, outputs a decoding result indicating that. The processing unit 31 is activated, and if no processing is to be performed, processing in the processing unit 31 is prohibited and input packets are passed through. These processing section 31 and decoder 32 are conventionally provided as a pipeline configuration. On the other hand, 33 is a processing unit 31 and a decoder 32 in this embodiment.
The decoding result from the decoder 32 is input to one input terminal, and the through flag added to the input packet is input to the other inverting input terminal. When the input packet is not addressed to the own processor and the through flag is set to "1", the AND gate 33 does not open, and regardless of the decoding result of the decoder 32, processing in the processing unit 31 is prohibited, and the input packet is The packet passes through without any processing.

In the above configuration, when an input packet from the host arrives at the first stage processor of the multiprocessor configuration as shown in FIG. The local PE# added to the input packet is compared with the destination PE# added to the input packet. If they match, that is, if the input packet is addressed to the own processor, the through flag 3 is not set; if they do not match, the input packet is If the data is not addressed to the own processor, the through flag 3 is set to "1" and the data is sent to the in-processor processing unit via the pipeline path. In each processing unit of the pipeline configuration, if the through flag 3 is not set, the corresponding processing is performed in each processing unit as before, but if the through flag 3 is set, the input packet is passed to all processing units. The input signal is passed through and output from the output control unit OC to the next processor in the same state as input. Similar processing is performed in subsequent processors, and the destination P
A processor with a matching E# performs a predetermined process, and packets passed through by other processors are returned to the host.

As described above, according to this embodiment, the bypass function can be realized using the pipeline route without requiring a special bypass route, so that the input control unit IC and the output control unit as shown in FIG. In addition to eliminating the need for a bypass path between OCs, the convergence circuit in the output control unit OC is also no longer required, and by reusing the conventional one, the only thing that is actually added is one bit added to the pipeline path. It requires only 1 route and a small number of logic circuits, which greatly simplifies the hardware.

In the above embodiments, the present invention has been described as being applied to a data flow type processor having a multi-processor configuration, but it is also applicable as long as at least each processor has a pipeline configuration.

[0015] Furthermore, in the above embodiment, the PE in the packet
Although we have shown only an example where # is given by the host (computer), each PE processes the packet and updates the destination PE # of the packet, and other PEs in the multiprocessor
Needless to say, the packet can be sent to E.

[0016]

As described above, according to the present invention, there is provided a setting means for setting the own processor number in the input control section of each processor, and a setting means for setting the destination processor number added to the input data and the setting means. and determining means for determining whether input data is addressed to the own processor based on the set own processor number, and prohibits processing in each processing section in the pipeline path of each processor. A through flag is provided to allow the input data to pass through as is, and the through flag is set when the output of the determination means is not addressed to the own processor, so bypassing is possible without the need for a special bypass path. The function can be realized,
Since the merging circuit of the output control section is also not required, there is an effect that the hardware is simplified.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing main parts of an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific configuration of a comparator according to an embodiment.

FIG. 3 is a conceptual diagram showing each processing unit in the pipeline configuration of the embodiment.

FIG. 4 is a block diagram showing a conventional example.

FIG. 5 is a block diagram showing a multiprocessor configuration.

[Explanation of symbols]

1 PE# register (setting means) 2 Comparator (judgment means) 3 Through flag 20 OR gate 21~2n EXOR gate 31 Processing section 32 Decoder 33 AND gate IC input control section OC output control section

Claims (1)

[Claims] [Claim 1] An input control unit that inputs data from the outside, a plurality of processing units that have a pipeline configuration that performs various processes on the input data, and an output control unit that outputs data from the processing units to the outside. In an information processing device with a multi-processor configuration, in which a plurality of processors having a A setting means for setting the own processor number in the control unit, and a setting means for setting the own processor number in the control unit, and a setting means for setting the own processor number in the control unit, and a setting means for setting the own processor number such that the input data is addressed to the own processor based on the destination processor number added to the input data and the own processor number set in the above setting means. In addition, a through flag is provided in the pipeline path of each processor to prohibit processing in each processing unit and allow the input data to pass through as is, so that the output of the determination means is self-directed. An information processing device characterized in that the through flag is set when indicating that the destination is not addressed to a processor.